1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * linux/drivers/video/cyber2000fb.h |
4 | * |
5 | * Copyright (C) 1998-2000 Russell King |
6 | * |
7 | * Integraphics Cyber2000 frame buffer device |
8 | */ |
9 | |
10 | /* |
11 | * Internal CyberPro sizes and offsets. |
12 | */ |
13 | #define MMIO_OFFSET 0x00800000 |
14 | #define MMIO_SIZE 0x000c0000 |
15 | |
16 | #define NR_PALETTE 256 |
17 | |
18 | #if defined(DEBUG) && defined(CONFIG_DEBUG_LL) |
19 | static void debug_printf(char *fmt, ...) |
20 | { |
21 | extern void printascii(const char *); |
22 | char buffer[128]; |
23 | va_list ap; |
24 | |
25 | va_start(ap, fmt); |
26 | vsprintf(buffer, fmt, ap); |
27 | va_end(ap); |
28 | |
29 | printascii(buffer); |
30 | } |
31 | #else |
32 | #define debug_printf(x...) do { } while (0) |
33 | #endif |
34 | |
35 | #define RAMDAC_RAMPWRDN 0x01 |
36 | #define RAMDAC_DAC8BIT 0x02 |
37 | #define RAMDAC_VREFEN 0x04 |
38 | #define RAMDAC_BYPASS 0x10 |
39 | #define RAMDAC_DACPWRDN 0x40 |
40 | |
41 | #define EXT_CRT_VRTOFL 0x11 |
42 | #define EXT_CRT_VRTOFL_LINECOMP10 0x10 |
43 | #define EXT_CRT_VRTOFL_INTERLACE 0x20 |
44 | |
45 | #define EXT_CRT_IRQ 0x12 |
46 | #define EXT_CRT_IRQ_ENABLE 0x01 |
47 | #define EXT_CRT_IRQ_ACT_HIGH 0x04 |
48 | |
49 | #define EXT_CRT_TEST 0x13 |
50 | |
51 | #define EXT_SYNC_CTL 0x16 |
52 | #define EXT_SYNC_CTL_HS_NORMAL 0x00 |
53 | #define EXT_SYNC_CTL_HS_0 0x01 |
54 | #define EXT_SYNC_CTL_HS_1 0x02 |
55 | #define EXT_SYNC_CTL_HS_HSVS 0x03 |
56 | #define EXT_SYNC_CTL_VS_NORMAL 0x00 |
57 | #define EXT_SYNC_CTL_VS_0 0x04 |
58 | #define EXT_SYNC_CTL_VS_1 0x08 |
59 | #define EXT_SYNC_CTL_VS_COMP 0x0c |
60 | |
61 | #define EXT_BUS_CTL 0x30 |
62 | #define EXT_BUS_CTL_LIN_1MB 0x00 |
63 | #define EXT_BUS_CTL_LIN_2MB 0x01 |
64 | #define EXT_BUS_CTL_LIN_4MB 0x02 |
65 | #define EXT_BUS_CTL_ZEROWAIT 0x04 |
66 | #define EXT_BUS_CTL_PCIBURST_WRITE 0x20 |
67 | #define EXT_BUS_CTL_PCIBURST_READ 0x80 /* CyberPro 5000 only */ |
68 | |
69 | #define EXT_SEG_WRITE_PTR 0x31 |
70 | #define EXT_SEG_READ_PTR 0x32 |
71 | #define EXT_BIU_MISC 0x33 |
72 | #define EXT_BIU_MISC_LIN_ENABLE 0x01 |
73 | #define EXT_BIU_MISC_COP_ENABLE 0x04 |
74 | #define EXT_BIU_MISC_COP_BFC 0x08 |
75 | |
76 | #define EXT_FUNC_CTL 0x3c |
77 | #define EXT_FUNC_CTL_EXTREGENBL 0x80 /* enable access to 0xbcxxx */ |
78 | |
79 | #define PCI_BM_CTL 0x3e |
80 | #define PCI_BM_CTL_ENABLE 0x01 /* enable bus-master */ |
81 | #define PCI_BM_CTL_BURST 0x02 /* enable burst */ |
82 | #define PCI_BM_CTL_BACK2BACK 0x04 /* enable back to back */ |
83 | #define PCI_BM_CTL_DUMMY 0x08 /* insert dummy cycle */ |
84 | |
85 | #define X_V2_VID_MEM_START 0x40 |
86 | #define X_V2_VID_SRC_WIDTH 0x43 |
87 | #define X_V2_X_START 0x45 |
88 | #define X_V2_X_END 0x47 |
89 | #define X_V2_Y_START 0x49 |
90 | #define X_V2_Y_END 0x4b |
91 | #define X_V2_VID_SRC_WIN_WIDTH 0x4d |
92 | |
93 | #define Y_V2_DDA_X_INC 0x43 |
94 | #define Y_V2_DDA_Y_INC 0x47 |
95 | #define Y_V2_VID_FIFO_CTL 0x49 |
96 | #define Y_V2_VID_FMT 0x4b |
97 | #define Y_V2_VID_DISP_CTL1 0x4c |
98 | #define Y_V2_VID_FIFO_CTL1 0x4d |
99 | |
100 | #define J_X2_VID_MEM_START 0x40 |
101 | #define J_X2_VID_SRC_WIDTH 0x43 |
102 | #define J_X2_X_START 0x47 |
103 | #define J_X2_X_END 0x49 |
104 | #define J_X2_Y_START 0x4b |
105 | #define J_X2_Y_END 0x4d |
106 | #define J_X2_VID_SRC_WIN_WIDTH 0x4f |
107 | |
108 | #define K_X2_DDA_X_INIT 0x40 |
109 | #define K_X2_DDA_X_INC 0x42 |
110 | #define K_X2_DDA_Y_INIT 0x44 |
111 | #define K_X2_DDA_Y_INC 0x46 |
112 | #define K_X2_VID_FMT 0x48 |
113 | #define K_X2_VID_DISP_CTL1 0x49 |
114 | |
115 | #define K_CAP_X2_CTL1 0x49 |
116 | |
117 | #define CURS_H_START 0x50 |
118 | #define CURS_H_PRESET 0x52 |
119 | #define CURS_V_START 0x53 |
120 | #define CURS_V_PRESET 0x55 |
121 | #define CURS_CTL 0x56 |
122 | |
123 | #define EXT_ATTRIB_CTL 0x57 |
124 | #define EXT_ATTRIB_CTL_EXT 0x01 |
125 | |
126 | #define EXT_OVERSCAN_RED 0x58 |
127 | #define EXT_OVERSCAN_GREEN 0x59 |
128 | #define EXT_OVERSCAN_BLUE 0x5a |
129 | |
130 | #define CAP_X_START 0x60 |
131 | #define CAP_X_END 0x62 |
132 | #define CAP_Y_START 0x64 |
133 | #define CAP_Y_END 0x66 |
134 | #define CAP_DDA_X_INIT 0x68 |
135 | #define CAP_DDA_X_INC 0x6a |
136 | #define CAP_DDA_Y_INIT 0x6c |
137 | #define CAP_DDA_Y_INC 0x6e |
138 | |
139 | #define EXT_MEM_CTL0 0x70 |
140 | #define EXT_MEM_CTL0_7CLK 0x01 |
141 | #define EXT_MEM_CTL0_RAS_1 0x02 |
142 | #define EXT_MEM_CTL0_RAS2CAS_1 0x04 |
143 | #define EXT_MEM_CTL0_MULTCAS 0x08 |
144 | #define EXT_MEM_CTL0_ASYM 0x10 |
145 | #define EXT_MEM_CTL0_CAS1ON 0x20 |
146 | #define EXT_MEM_CTL0_FIFOFLUSH 0x40 |
147 | #define EXT_MEM_CTL0_SEQRESET 0x80 |
148 | |
149 | #define EXT_MEM_CTL1 0x71 |
150 | #define EXT_MEM_CTL1_PAR 0x00 |
151 | #define EXT_MEM_CTL1_SERPAR 0x01 |
152 | #define EXT_MEM_CTL1_SER 0x03 |
153 | #define EXT_MEM_CTL1_SYNC 0x04 |
154 | #define EXT_MEM_CTL1_VRAM 0x08 |
155 | #define EXT_MEM_CTL1_4K_REFRESH 0x10 |
156 | #define EXT_MEM_CTL1_256Kx4 0x00 |
157 | #define EXT_MEM_CTL1_512Kx8 0x40 |
158 | #define EXT_MEM_CTL1_1Mx16 0x60 |
159 | |
160 | #define EXT_MEM_CTL2 0x72 |
161 | #define MEM_CTL2_SIZE_1MB 0x00 |
162 | #define MEM_CTL2_SIZE_2MB 0x01 |
163 | #define MEM_CTL2_SIZE_4MB 0x02 |
164 | #define MEM_CTL2_SIZE_MASK 0x03 |
165 | #define MEM_CTL2_64BIT 0x04 |
166 | |
167 | #define EXT_HIDDEN_CTL1 0x73 |
168 | |
169 | #define EXT_FIFO_CTL 0x74 |
170 | |
171 | #define EXT_SEQ_MISC 0x77 |
172 | #define EXT_SEQ_MISC_8 0x01 |
173 | #define EXT_SEQ_MISC_16_RGB565 0x02 |
174 | #define EXT_SEQ_MISC_32 0x03 |
175 | #define EXT_SEQ_MISC_24_RGB888 0x04 |
176 | #define EXT_SEQ_MISC_16_RGB555 0x06 |
177 | #define EXT_SEQ_MISC_8_RGB332 0x09 |
178 | #define EXT_SEQ_MISC_16_RGB444 0x0a |
179 | |
180 | #define EXT_HIDDEN_CTL4 0x7a |
181 | |
182 | #define CURS_MEM_START 0x7e /* bits 23..12 */ |
183 | |
184 | #define CAP_PIP_X_START 0x80 |
185 | #define CAP_PIP_X_END 0x82 |
186 | #define CAP_PIP_Y_START 0x84 |
187 | #define CAP_PIP_Y_END 0x86 |
188 | |
189 | #define EXT_CAP_CTL1 0x88 |
190 | |
191 | #define EXT_CAP_CTL2 0x89 |
192 | #define EXT_CAP_CTL2_ODDFRAMEIRQ 0x01 |
193 | #define EXT_CAP_CTL2_ANYFRAMEIRQ 0x02 |
194 | |
195 | #define BM_CTRL0 0x9c |
196 | #define BM_CTRL1 0x9d |
197 | |
198 | #define EXT_CAP_MODE1 0xa4 |
199 | #define EXT_CAP_MODE1_8BIT 0x01 /* enable 8bit capture mode */ |
200 | #define EXT_CAP_MODE1_CCIR656 0x02 /* CCIR656 mode */ |
201 | #define EXT_CAP_MODE1_IGNOREVGT 0x04 /* ignore VGT */ |
202 | #define EXT_CAP_MODE1_ALTFIFO 0x10 /* use alternate FIFO for capture */ |
203 | #define EXT_CAP_MODE1_SWAPUV 0x20 /* swap UV bytes */ |
204 | #define EXT_CAP_MODE1_MIRRORY 0x40 /* mirror vertically */ |
205 | #define EXT_CAP_MODE1_MIRRORX 0x80 /* mirror horizontally */ |
206 | |
207 | #define EXT_CAP_MODE2 0xa5 |
208 | #define EXT_CAP_MODE2_CCIRINVOE 0x01 |
209 | #define EXT_CAP_MODE2_CCIRINVVGT 0x02 |
210 | #define EXT_CAP_MODE2_CCIRINVHGT 0x04 |
211 | #define EXT_CAP_MODE2_CCIRINVDG 0x08 |
212 | #define EXT_CAP_MODE2_DATEND 0x10 |
213 | #define EXT_CAP_MODE2_CCIRDGH 0x20 |
214 | #define EXT_CAP_MODE2_FIXSONY 0x40 |
215 | #define EXT_CAP_MODE2_SYNCFREEZE 0x80 |
216 | |
217 | #define EXT_TV_CTL 0xae |
218 | |
219 | #define EXT_DCLK_MULT 0xb0 |
220 | #define EXT_DCLK_DIV 0xb1 |
221 | #define EXT_DCLK_DIV_VFSEL 0x20 |
222 | #define EXT_MCLK_MULT 0xb2 |
223 | #define EXT_MCLK_DIV 0xb3 |
224 | |
225 | #define EXT_LATCH1 0xb5 |
226 | #define EXT_LATCH1_VAFC_EN 0x01 /* enable VAFC */ |
227 | |
228 | #define EXT_FEATURE 0xb7 |
229 | #define EXT_FEATURE_BUS_MASK 0x07 /* host bus mask */ |
230 | #define EXT_FEATURE_BUS_PCI 0x00 |
231 | #define EXT_FEATURE_BUS_VL_STD 0x04 |
232 | #define EXT_FEATURE_BUS_VL_LINEAR 0x05 |
233 | #define EXT_FEATURE_1682 0x20 /* IGS 1682 compatibility */ |
234 | |
235 | #define EXT_LATCH2 0xb6 |
236 | #define EXT_LATCH2_I2C_CLKEN 0x10 |
237 | #define EXT_LATCH2_I2C_CLK 0x20 |
238 | #define EXT_LATCH2_I2C_DATEN 0x40 |
239 | #define EXT_LATCH2_I2C_DAT 0x80 |
240 | |
241 | #define EXT_XT_CTL 0xbe |
242 | #define EXT_XT_CAP16 0x04 |
243 | #define EXT_XT_LINEARFB 0x08 |
244 | #define EXT_XT_PAL 0x10 |
245 | |
246 | #define EXT_MEM_START 0xc0 /* ext start address 21 bits */ |
247 | #define HOR_PHASE_SHIFT 0xc2 /* high 3 bits */ |
248 | #define EXT_SRC_WIDTH 0xc3 /* ext offset phase 10 bits */ |
249 | #define EXT_SRC_HEIGHT 0xc4 /* high 6 bits */ |
250 | #define EXT_X_START 0xc5 /* ext->screen, 16 bits */ |
251 | #define EXT_X_END 0xc7 /* ext->screen, 16 bits */ |
252 | #define EXT_Y_START 0xc9 /* ext->screen, 16 bits */ |
253 | #define EXT_Y_END 0xcb /* ext->screen, 16 bits */ |
254 | #define EXT_SRC_WIN_WIDTH 0xcd /* 8 bits */ |
255 | #define EXT_COLOUR_COMPARE 0xce /* 24 bits */ |
256 | #define EXT_DDA_X_INIT 0xd1 /* ext->screen 16 bits */ |
257 | #define EXT_DDA_X_INC 0xd3 /* ext->screen 16 bits */ |
258 | #define EXT_DDA_Y_INIT 0xd5 /* ext->screen 16 bits */ |
259 | #define EXT_DDA_Y_INC 0xd7 /* ext->screen 16 bits */ |
260 | |
261 | #define EXT_VID_FIFO_CTL 0xd9 |
262 | |
263 | #define EXT_VID_FMT 0xdb |
264 | #define EXT_VID_FMT_YUV422 0x00 /* formats - does this cause conversion? */ |
265 | #define EXT_VID_FMT_RGB555 0x01 |
266 | #define EXT_VID_FMT_RGB565 0x02 |
267 | #define EXT_VID_FMT_RGB888_24 0x03 |
268 | #define EXT_VID_FMT_RGB888_32 0x04 |
269 | #define EXT_VID_FMT_RGB8 0x05 |
270 | #define EXT_VID_FMT_RGB4444 0x06 |
271 | #define EXT_VID_FMT_RGB8T 0x07 |
272 | #define EXT_VID_FMT_DUP_PIX_ZOON 0x08 /* duplicate pixel zoom */ |
273 | #define EXT_VID_FMT_MOD_3RD_PIX 0x20 /* modify 3rd duplicated pixel */ |
274 | #define EXT_VID_FMT_DBL_H_PIX 0x40 /* double horiz pixels */ |
275 | #define EXT_VID_FMT_YUV128 0x80 /* YUV data offset by 128 */ |
276 | |
277 | #define EXT_VID_DISP_CTL1 0xdc |
278 | #define EXT_VID_DISP_CTL1_INTRAM 0x01 /* video pixels go to internal RAM */ |
279 | #define EXT_VID_DISP_CTL1_IGNORE_CCOMP 0x02 /* ignore colour compare registers */ |
280 | #define EXT_VID_DISP_CTL1_NOCLIP 0x04 /* do not clip to 16235,16240 */ |
281 | #define EXT_VID_DISP_CTL1_UV_AVG 0x08 /* U/V data is averaged */ |
282 | #define EXT_VID_DISP_CTL1_Y128 0x10 /* Y data offset by 128 (if YUV128 set) */ |
283 | #define EXT_VID_DISP_CTL1_VINTERPOL_OFF 0x20 /* disable vertical interpolation */ |
284 | #define EXT_VID_DISP_CTL1_FULL_WIN 0x40 /* video out window full */ |
285 | #define EXT_VID_DISP_CTL1_ENABLE_WINDOW 0x80 /* enable video window */ |
286 | |
287 | #define EXT_VID_FIFO_CTL1 0xdd |
288 | #define EXT_VID_FIFO_CTL1_OE_HIGH 0x02 |
289 | #define EXT_VID_FIFO_CTL1_INTERLEAVE 0x04 /* enable interleaved memory read */ |
290 | |
291 | #define EXT_ROM_UCB4GH 0xe5 |
292 | #define EXT_ROM_UCB4GH_FREEZE 0x02 /* capture frozen */ |
293 | #define EXT_ROM_UCB4GH_ODDFRAME 0x04 /* 1 = odd frame captured */ |
294 | #define EXT_ROM_UCB4GH_1HL 0x08 /* first horizonal line after VGT falling edge */ |
295 | #define EXT_ROM_UCB4GH_ODD 0x10 /* odd frame indicator */ |
296 | #define EXT_ROM_UCB4GH_INTSTAT 0x20 /* video interrupt */ |
297 | |
298 | #define VFAC_CTL1 0xe8 |
299 | #define VFAC_CTL1_CAPTURE 0x01 /* capture enable (only when VSYNC high)*/ |
300 | #define VFAC_CTL1_VFAC_ENABLE 0x02 /* vfac enable */ |
301 | #define VFAC_CTL1_FREEZE_CAPTURE 0x04 /* freeze capture */ |
302 | #define VFAC_CTL1_FREEZE_CAPTURE_SYNC 0x08 /* sync freeze capture */ |
303 | #define VFAC_CTL1_VALIDFRAME_SRC 0x10 /* select valid frame source */ |
304 | #define VFAC_CTL1_PHILIPS 0x40 /* select Philips mode */ |
305 | #define VFAC_CTL1_MODVINTERPOLCLK 0x80 /* modify vertical interpolation clocl */ |
306 | |
307 | #define VFAC_CTL2 0xe9 |
308 | #define VFAC_CTL2_INVERT_VIDDATAVALID 0x01 /* invert video data valid */ |
309 | #define VFAC_CTL2_INVERT_GRAPHREADY 0x02 /* invert graphic ready output sig */ |
310 | #define VFAC_CTL2_INVERT_DATACLK 0x04 /* invert data clock signal */ |
311 | #define VFAC_CTL2_INVERT_HSYNC 0x08 /* invert hsync input */ |
312 | #define VFAC_CTL2_INVERT_VSYNC 0x10 /* invert vsync input */ |
313 | #define VFAC_CTL2_INVERT_FRAME 0x20 /* invert frame odd/even input */ |
314 | #define VFAC_CTL2_INVERT_BLANK 0x40 /* invert blank output */ |
315 | #define VFAC_CTL2_INVERT_OVSYNC 0x80 /* invert other vsync input */ |
316 | |
317 | #define VFAC_CTL3 0xea |
318 | #define VFAC_CTL3_CAP_LARGE_FIFO 0x01 /* large capture fifo */ |
319 | #define VFAC_CTL3_CAP_INTERLACE 0x02 /* capture odd and even fields */ |
320 | #define VFAC_CTL3_CAP_HOLD_4NS 0x00 /* hold capture data for 4ns */ |
321 | #define VFAC_CTL3_CAP_HOLD_2NS 0x04 /* hold capture data for 2ns */ |
322 | #define VFAC_CTL3_CAP_HOLD_6NS 0x08 /* hold capture data for 6ns */ |
323 | #define VFAC_CTL3_CAP_HOLD_0NS 0x0c /* hold capture data for 0ns */ |
324 | #define VFAC_CTL3_CHROMAKEY 0x20 /* capture data will be chromakeyed */ |
325 | #define VFAC_CTL3_CAP_IRQ 0x40 /* enable capture interrupt */ |
326 | |
327 | #define CAP_MEM_START 0xeb /* 18 bits */ |
328 | #define CAP_MAP_WIDTH 0xed /* high 6 bits */ |
329 | #define CAP_PITCH 0xee /* 8 bits */ |
330 | |
331 | #define CAP_CTL_MISC 0xef |
332 | #define CAP_CTL_MISC_HDIV 0x01 |
333 | #define CAP_CTL_MISC_HDIV4 0x02 |
334 | #define CAP_CTL_MISC_ODDEVEN 0x04 |
335 | #define CAP_CTL_MISC_HSYNCDIV2 0x08 |
336 | #define CAP_CTL_MISC_SYNCTZHIGH 0x10 |
337 | #define CAP_CTL_MISC_SYNCTZOR 0x20 |
338 | #define CAP_CTL_MISC_DISPUSED 0x80 |
339 | |
340 | #define REG_BANK 0xfa |
341 | #define REG_BANK_X 0x00 |
342 | #define REG_BANK_Y 0x01 |
343 | #define REG_BANK_W 0x02 |
344 | #define REG_BANK_T 0x03 |
345 | #define REG_BANK_J 0x04 |
346 | #define REG_BANK_K 0x05 |
347 | |
348 | /* |
349 | * Bus-master |
350 | */ |
351 | #define BM_VID_ADDR_LOW 0xbc040 |
352 | #define BM_VID_ADDR_HIGH 0xbc044 |
353 | #define BM_ADDRESS_LOW 0xbc080 |
354 | #define BM_ADDRESS_HIGH 0xbc084 |
355 | #define BM_LENGTH 0xbc088 |
356 | #define BM_CONTROL 0xbc08c |
357 | #define BM_CONTROL_ENABLE 0x01 /* enable transfer */ |
358 | #define BM_CONTROL_IRQEN 0x02 /* enable IRQ at end of transfer */ |
359 | #define BM_CONTROL_INIT 0x04 /* initialise status & count */ |
360 | #define BM_COUNT 0xbc090 /* read-only */ |
361 | |
362 | /* |
363 | * TV registers |
364 | */ |
365 | #define TV_VBLANK_EVEN_START 0xbe43c |
366 | #define TV_VBLANK_EVEN_END 0xbe440 |
367 | #define TV_VBLANK_ODD_START 0xbe444 |
368 | #define TV_VBLANK_ODD_END 0xbe448 |
369 | #define TV_SYNC_YGAIN 0xbe44c |
370 | #define TV_UV_GAIN 0xbe450 |
371 | #define TV_PED_UVDET 0xbe454 |
372 | #define TV_UV_BURST_AMP 0xbe458 |
373 | #define TV_HSYNC_START 0xbe45c |
374 | #define TV_HSYNC_END 0xbe460 |
375 | #define TV_Y_DELAY1 0xbe464 |
376 | #define TV_Y_DELAY2 0xbe468 |
377 | #define TV_UV_DELAY1 0xbe46c |
378 | #define TV_BURST_START 0xbe470 |
379 | #define TV_BURST_END 0xbe474 |
380 | #define TV_HBLANK_START 0xbe478 |
381 | #define TV_HBLANK_END 0xbe47c |
382 | #define TV_PED_EVEN_START 0xbe480 |
383 | #define TV_PED_EVEN_END 0xbe484 |
384 | #define TV_PED_ODD_START 0xbe488 |
385 | #define TV_PED_ODD_END 0xbe48c |
386 | #define TV_VSYNC_EVEN_START 0xbe490 |
387 | #define TV_VSYNC_EVEN_END 0xbe494 |
388 | #define TV_VSYNC_ODD_START 0xbe498 |
389 | #define TV_VSYNC_ODD_END 0xbe49c |
390 | #define TV_SCFL 0xbe4a0 |
391 | #define TV_SCFH 0xbe4a4 |
392 | #define TV_SCP 0xbe4a8 |
393 | #define TV_DELAYBYPASS 0xbe4b4 |
394 | #define TV_EQL_END 0xbe4bc |
395 | #define TV_SERR_START 0xbe4c0 |
396 | #define TV_SERR_END 0xbe4c4 |
397 | #define TV_CTL 0xbe4dc /* reflects a previous register- MVFCLR, MVPCLR etc P241*/ |
398 | #define TV_VSYNC_VGA_HS 0xbe4e8 |
399 | #define TV_FLICK_XMIN 0xbe514 |
400 | #define TV_FLICK_XMAX 0xbe518 |
401 | #define TV_FLICK_YMIN 0xbe51c |
402 | #define TV_FLICK_YMAX 0xbe520 |
403 | |
404 | /* |
405 | * Graphics Co-processor |
406 | */ |
407 | #define CO_REG_CONTROL 0xbf011 |
408 | #define CO_CTRL_BUSY 0x80 |
409 | #define CO_CTRL_CMDFULL 0x04 |
410 | #define CO_CTRL_FIFOEMPTY 0x02 |
411 | #define CO_CTRL_READY 0x01 |
412 | |
413 | #define CO_REG_SRC_WIDTH 0xbf018 |
414 | #define CO_REG_PIXFMT 0xbf01c |
415 | #define CO_PIXFMT_32BPP 0x03 |
416 | #define CO_PIXFMT_24BPP 0x02 |
417 | #define CO_PIXFMT_16BPP 0x01 |
418 | #define CO_PIXFMT_8BPP 0x00 |
419 | |
420 | #define CO_REG_FGMIX 0xbf048 |
421 | #define CO_FG_MIX_ZERO 0x00 |
422 | #define CO_FG_MIX_SRC_AND_DST 0x01 |
423 | #define CO_FG_MIX_SRC_AND_NDST 0x02 |
424 | #define CO_FG_MIX_SRC 0x03 |
425 | #define CO_FG_MIX_NSRC_AND_DST 0x04 |
426 | #define CO_FG_MIX_DST 0x05 |
427 | #define CO_FG_MIX_SRC_XOR_DST 0x06 |
428 | #define CO_FG_MIX_SRC_OR_DST 0x07 |
429 | #define CO_FG_MIX_NSRC_AND_NDST 0x08 |
430 | #define CO_FG_MIX_SRC_XOR_NDST 0x09 |
431 | #define CO_FG_MIX_NDST 0x0a |
432 | #define CO_FG_MIX_SRC_OR_NDST 0x0b |
433 | #define CO_FG_MIX_NSRC 0x0c |
434 | #define CO_FG_MIX_NSRC_OR_DST 0x0d |
435 | #define CO_FG_MIX_NSRC_OR_NDST 0x0e |
436 | #define CO_FG_MIX_ONES 0x0f |
437 | |
438 | #define CO_REG_FGCOLOUR 0xbf058 |
439 | #define CO_REG_BGCOLOUR 0xbf05c |
440 | #define CO_REG_PIXWIDTH 0xbf060 |
441 | #define CO_REG_PIXHEIGHT 0xbf062 |
442 | #define CO_REG_X_PHASE 0xbf078 |
443 | #define CO_REG_CMD_L 0xbf07c |
444 | #define CO_CMD_L_PATTERN_FGCOL 0x8000 |
445 | #define CO_CMD_L_INC_LEFT 0x0004 |
446 | #define CO_CMD_L_INC_UP 0x0002 |
447 | |
448 | #define CO_REG_CMD_H 0xbf07e |
449 | #define CO_CMD_H_BGSRCMAP 0x8000 /* otherwise bg colour */ |
450 | #define CO_CMD_H_FGSRCMAP 0x2000 /* otherwise fg colour */ |
451 | #define CO_CMD_H_BLITTER 0x0800 |
452 | |
453 | #define CO_REG_SRC1_PTR 0xbf170 |
454 | #define CO_REG_SRC2_PTR 0xbf174 |
455 | #define CO_REG_DEST_PTR 0xbf178 |
456 | #define CO_REG_DEST_WIDTH 0xbf218 |
457 | |
458 | /* |
459 | * Private structure |
460 | */ |
461 | struct cfb_info; |
462 | |
463 | struct cyberpro_info { |
464 | struct device *dev; |
465 | struct i2c_adapter *i2c; |
466 | unsigned char __iomem *regs; |
467 | char __iomem *fb; |
468 | char dev_name[32]; |
469 | unsigned int fb_size; |
470 | unsigned int chip_id; |
471 | unsigned int irq; |
472 | |
473 | /* |
474 | * The following is a pointer to be passed into the |
475 | * functions below. The modules outside the main |
476 | * cyber2000fb.c driver have no knowledge as to what |
477 | * is within this structure. |
478 | */ |
479 | struct cfb_info *info; |
480 | }; |
481 | |
482 | #define ID_IGA_1682 0 |
483 | #define ID_CYBERPRO_2000 1 |
484 | #define ID_CYBERPRO_2010 2 |
485 | #define ID_CYBERPRO_5000 3 |
486 | |
487 | /* |
488 | * Note! Writing to the Cyber20x0 registers from an interrupt |
489 | * routine is definitely a bad idea atm. |
490 | */ |
491 | int cyber2000fb_attach(struct cyberpro_info *info, int idx); |
492 | void cyber2000fb_detach(int idx); |
493 | void cyber2000fb_enable_extregs(struct cfb_info *cfb); |
494 | void cyber2000fb_disable_extregs(struct cfb_info *cfb); |
495 | |