| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * drivers/video/geode/display_gx1.h |
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| 4 | * -- Geode GX1 display controller |
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| 5 | * |
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| 6 | * Copyright (C) 2005 Arcom Control Systems Ltd. |
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| 7 | * |
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| 8 | * Based on AMD's original 2.4 driver: |
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| 9 | * Copyright (C) 2004 Advanced Micro Devices, Inc. |
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| 10 | */ |
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| 11 | #ifndef __DISPLAY_GX1_H__ |
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| 12 | #define __DISPLAY_GX1_H__ |
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| 13 | |
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| 14 | unsigned gx1_gx_base(void); |
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| 15 | int gx1_frame_buffer_size(void); |
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| 16 | |
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| 17 | extern const struct geode_dc_ops gx1_dc_ops; |
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| 18 | |
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| 19 | /* GX1 configuration I/O registers */ |
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| 20 | |
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| 21 | #define CONFIG_CCR3 0xc3 |
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| 22 | # define CONFIG_CCR3_MAPEN 0x10 |
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| 23 | #define CONFIG_GCR 0xb8 |
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| 24 | |
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| 25 | /* Memory controller registers */ |
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| 26 | |
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| 27 | #define MC_BANK_CFG 0x08 |
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| 28 | # define MC_BCFG_DIMM0_SZ_MASK 0x00000700 |
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| 29 | # define MC_BCFG_DIMM0_PG_SZ_MASK 0x00000070 |
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| 30 | # define MC_BCFG_DIMM0_PG_SZ_NO_DIMM 0x00000070 |
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| 31 | |
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| 32 | #define MC_GBASE_ADD 0x14 |
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| 33 | # define MC_GADD_GBADD_MASK 0x000003ff |
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| 34 | |
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| 35 | /* Display controller registers */ |
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| 36 | |
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| 37 | #define DC_PAL_ADDRESS 0x70 |
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| 38 | #define DC_PAL_DATA 0x74 |
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| 39 | |
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| 40 | #define DC_UNLOCK 0x00 |
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| 41 | # define DC_UNLOCK_CODE 0x00004758 |
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| 42 | |
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| 43 | #define DC_GENERAL_CFG 0x04 |
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| 44 | # define DC_GCFG_DFLE 0x00000001 |
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| 45 | # define DC_GCFG_CURE 0x00000002 |
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| 46 | # define DC_GCFG_VCLK_DIV 0x00000004 |
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| 47 | # define DC_GCFG_PLNO 0x00000004 |
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| 48 | # define DC_GCFG_PPC 0x00000008 |
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| 49 | # define DC_GCFG_CMPE 0x00000010 |
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| 50 | # define DC_GCFG_DECE 0x00000020 |
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| 51 | # define DC_GCFG_DCLK_MASK 0x000000C0 |
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| 52 | # define DC_GCFG_DCLK_DIV_1 0x00000080 |
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| 53 | # define DC_GCFG_DFHPSL_MASK 0x00000F00 |
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| 54 | # define DC_GCFG_DFHPSL_POS 8 |
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| 55 | # define DC_GCFG_DFHPEL_MASK 0x0000F000 |
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| 56 | # define DC_GCFG_DFHPEL_POS 12 |
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| 57 | # define DC_GCFG_CIM_MASK 0x00030000 |
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| 58 | # define DC_GCFG_CIM_POS 16 |
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| 59 | # define DC_GCFG_FDTY 0x00040000 |
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| 60 | # define DC_GCFG_RTPM 0x00080000 |
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| 61 | # define DC_GCFG_DAC_RS_MASK 0x00700000 |
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| 62 | # define DC_GCFG_DAC_RS_POS 20 |
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| 63 | # define DC_GCFG_CKWR 0x00800000 |
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| 64 | # define DC_GCFG_LDBL 0x01000000 |
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| 65 | # define DC_GCFG_DIAG 0x02000000 |
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| 66 | # define DC_GCFG_CH4S 0x04000000 |
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| 67 | # define DC_GCFG_SSLC 0x08000000 |
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| 68 | # define DC_GCFG_VIDE 0x10000000 |
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| 69 | # define DC_GCFG_VRDY 0x20000000 |
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| 70 | # define DC_GCFG_DPCK 0x40000000 |
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| 71 | # define DC_GCFG_DDCK 0x80000000 |
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| 72 | |
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| 73 | #define DC_TIMING_CFG 0x08 |
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| 74 | # define DC_TCFG_FPPE 0x00000001 |
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| 75 | # define DC_TCFG_HSYE 0x00000002 |
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| 76 | # define DC_TCFG_VSYE 0x00000004 |
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| 77 | # define DC_TCFG_BLKE 0x00000008 |
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| 78 | # define DC_TCFG_DDCK 0x00000010 |
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| 79 | # define DC_TCFG_TGEN 0x00000020 |
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| 80 | # define DC_TCFG_VIEN 0x00000040 |
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| 81 | # define DC_TCFG_BLNK 0x00000080 |
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| 82 | # define DC_TCFG_CHSP 0x00000100 |
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| 83 | # define DC_TCFG_CVSP 0x00000200 |
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| 84 | # define DC_TCFG_FHSP 0x00000400 |
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| 85 | # define DC_TCFG_FVSP 0x00000800 |
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| 86 | # define DC_TCFG_FCEN 0x00001000 |
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| 87 | # define DC_TCFG_CDCE 0x00002000 |
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| 88 | # define DC_TCFG_PLNR 0x00002000 |
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| 89 | # define DC_TCFG_INTL 0x00004000 |
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| 90 | # define DC_TCFG_PXDB 0x00008000 |
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| 91 | # define DC_TCFG_BKRT 0x00010000 |
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| 92 | # define DC_TCFG_PSD_MASK 0x000E0000 |
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| 93 | # define DC_TCFG_PSD_POS 17 |
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| 94 | # define DC_TCFG_DDCI 0x08000000 |
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| 95 | # define DC_TCFG_SENS 0x10000000 |
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| 96 | # define DC_TCFG_DNA 0x20000000 |
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| 97 | # define DC_TCFG_VNA 0x40000000 |
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| 98 | # define DC_TCFG_VINT 0x80000000 |
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| 99 | |
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| 100 | #define DC_OUTPUT_CFG 0x0C |
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| 101 | # define DC_OCFG_8BPP 0x00000001 |
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| 102 | # define DC_OCFG_555 0x00000002 |
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| 103 | # define DC_OCFG_PCKE 0x00000004 |
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| 104 | # define DC_OCFG_FRME 0x00000008 |
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| 105 | # define DC_OCFG_DITE 0x00000010 |
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| 106 | # define DC_OCFG_2PXE 0x00000020 |
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| 107 | # define DC_OCFG_2XCK 0x00000040 |
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| 108 | # define DC_OCFG_2IND 0x00000080 |
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| 109 | # define DC_OCFG_34ADD 0x00000100 |
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| 110 | # define DC_OCFG_FRMS 0x00000200 |
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| 111 | # define DC_OCFG_CKSL 0x00000400 |
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| 112 | # define DC_OCFG_PRMP 0x00000800 |
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| 113 | # define DC_OCFG_PDEL 0x00001000 |
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| 114 | # define DC_OCFG_PDEH 0x00002000 |
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| 115 | # define DC_OCFG_CFRW 0x00004000 |
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| 116 | # define DC_OCFG_DIAG 0x00008000 |
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| 117 | |
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| 118 | #define DC_FB_ST_OFFSET 0x10 |
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| 119 | #define DC_CB_ST_OFFSET 0x14 |
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| 120 | #define DC_CURS_ST_OFFSET 0x18 |
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| 121 | #define DC_ICON_ST_OFFSET 0x1C |
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| 122 | #define DC_VID_ST_OFFSET 0x20 |
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| 123 | #define DC_LINE_DELTA 0x24 |
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| 124 | #define DC_BUF_SIZE 0x28 |
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| 125 | |
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| 126 | #define DC_H_TIMING_1 0x30 |
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| 127 | #define DC_H_TIMING_2 0x34 |
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| 128 | #define DC_H_TIMING_3 0x38 |
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| 129 | #define DC_FP_H_TIMING 0x3C |
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| 130 | |
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| 131 | #define DC_V_TIMING_1 0x40 |
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| 132 | #define DC_V_TIMING_2 0x44 |
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| 133 | #define DC_V_TIMING_3 0x48 |
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| 134 | #define DC_FP_V_TIMING 0x4C |
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| 135 | |
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| 136 | #define DC_CURSOR_X 0x50 |
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| 137 | #define DC_ICON_X 0x54 |
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| 138 | #define DC_V_LINE_CNT 0x54 |
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| 139 | #define DC_CURSOR_Y 0x58 |
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| 140 | #define DC_ICON_Y 0x5C |
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| 141 | #define DC_SS_LINE_CMP 0x5C |
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| 142 | #define DC_CURSOR_COLOR 0x60 |
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| 143 | #define DC_ICON_COLOR 0x64 |
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| 144 | #define DC_BORDER_COLOR 0x68 |
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| 145 | #define DC_PAL_ADDRESS 0x70 |
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| 146 | #define DC_PAL_DATA 0x74 |
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| 147 | #define DC_DFIFO_DIAG 0x78 |
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| 148 | #define DC_CFIFO_DIAG 0x7C |
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| 149 | |
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| 150 | #endif /* !__DISPLAY_GX1_H__ */ |
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| 151 | |
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