| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. |
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| 4 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. |
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| 5 | |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __ACCEL_H__ |
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| 9 | #define __ACCEL_H__ |
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| 10 | |
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| 11 | #define FB_ACCEL_VIA_UNICHROME 50 |
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| 12 | |
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| 13 | /* MMIO Base Address Definition */ |
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| 14 | #define MMIO_VGABASE 0x8000 |
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| 15 | #define MMIO_CR_READ (MMIO_VGABASE + 0x3D4) |
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| 16 | #define MMIO_CR_WRITE (MMIO_VGABASE + 0x3D5) |
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| 17 | #define MMIO_SR_READ (MMIO_VGABASE + 0x3C4) |
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| 18 | #define MMIO_SR_WRITE (MMIO_VGABASE + 0x3C5) |
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| 19 | |
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| 20 | /* HW Cursor Status Define */ |
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| 21 | #define HW_Cursor_ON 0 |
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| 22 | #define HW_Cursor_OFF 1 |
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| 23 | |
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| 24 | #define CURSOR_SIZE (8 * 1024) |
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| 25 | #define VQ_SIZE (256 * 1024) |
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| 26 | |
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| 27 | #define VIA_MMIO_BLTBASE 0x200000 |
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| 28 | #define VIA_MMIO_BLTSIZE 0x200000 |
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| 29 | |
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| 30 | /* Defines for 2D registers */ |
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| 31 | #define VIA_REG_GECMD 0x000 |
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| 32 | #define VIA_REG_GEMODE 0x004 |
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| 33 | #define VIA_REG_SRCPOS 0x008 |
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| 34 | #define VIA_REG_DSTPOS 0x00C |
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| 35 | /* width and height */ |
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| 36 | #define VIA_REG_DIMENSION 0x010 |
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| 37 | #define VIA_REG_PATADDR 0x014 |
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| 38 | #define VIA_REG_FGCOLOR 0x018 |
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| 39 | #define VIA_REG_BGCOLOR 0x01C |
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| 40 | /* top and left of clipping */ |
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| 41 | #define VIA_REG_CLIPTL 0x020 |
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| 42 | /* bottom and right of clipping */ |
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| 43 | #define VIA_REG_CLIPBR 0x024 |
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| 44 | #define VIA_REG_OFFSET 0x028 |
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| 45 | /* color key control */ |
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| 46 | #define VIA_REG_KEYCONTROL 0x02C |
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| 47 | #define VIA_REG_SRCBASE 0x030 |
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| 48 | #define VIA_REG_DSTBASE 0x034 |
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| 49 | /* pitch of src and dst */ |
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| 50 | #define VIA_REG_PITCH 0x038 |
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| 51 | #define VIA_REG_MONOPAT0 0x03C |
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| 52 | #define VIA_REG_MONOPAT1 0x040 |
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| 53 | /* from 0x100 to 0x1ff */ |
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| 54 | #define VIA_REG_COLORPAT 0x100 |
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| 55 | |
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| 56 | /* defines for VIA 2D registers for vt3353/3409 (M1 engine)*/ |
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| 57 | #define VIA_REG_GECMD_M1 0x000 |
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| 58 | #define VIA_REG_GEMODE_M1 0x004 |
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| 59 | #define VIA_REG_GESTATUS_M1 0x004 /* as same as VIA_REG_GEMODE */ |
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| 60 | #define VIA_REG_PITCH_M1 0x008 /* pitch of src and dst */ |
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| 61 | #define VIA_REG_DIMENSION_M1 0x00C /* width and height */ |
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| 62 | #define VIA_REG_DSTPOS_M1 0x010 |
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| 63 | #define VIA_REG_LINE_XY_M1 0x010 |
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| 64 | #define VIA_REG_DSTBASE_M1 0x014 |
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| 65 | #define VIA_REG_SRCPOS_M1 0x018 |
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| 66 | #define VIA_REG_LINE_K1K2_M1 0x018 |
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| 67 | #define VIA_REG_SRCBASE_M1 0x01C |
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| 68 | #define VIA_REG_PATADDR_M1 0x020 |
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| 69 | #define VIA_REG_MONOPAT0_M1 0x024 |
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| 70 | #define VIA_REG_MONOPAT1_M1 0x028 |
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| 71 | #define VIA_REG_OFFSET_M1 0x02C |
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| 72 | #define VIA_REG_LINE_ERROR_M1 0x02C |
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| 73 | #define VIA_REG_CLIPTL_M1 0x040 /* top and left of clipping */ |
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| 74 | #define VIA_REG_CLIPBR_M1 0x044 /* bottom and right of clipping */ |
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| 75 | #define VIA_REG_KEYCONTROL_M1 0x048 /* color key control */ |
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| 76 | #define VIA_REG_FGCOLOR_M1 0x04C |
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| 77 | #define VIA_REG_DSTCOLORKEY_M1 0x04C /* as same as VIA_REG_FG */ |
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| 78 | #define VIA_REG_BGCOLOR_M1 0x050 |
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| 79 | #define VIA_REG_SRCCOLORKEY_M1 0x050 /* as same as VIA_REG_BG */ |
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| 80 | #define VIA_REG_MONOPATFGC_M1 0x058 /* Add BG color of Pattern. */ |
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| 81 | #define VIA_REG_MONOPATBGC_M1 0x05C /* Add FG color of Pattern. */ |
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| 82 | #define VIA_REG_COLORPAT_M1 0x100 /* from 0x100 to 0x1ff */ |
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| 83 | |
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| 84 | /* VIA_REG_PITCH(0x38): Pitch Setting */ |
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| 85 | #define VIA_PITCH_ENABLE 0x80000000 |
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| 86 | |
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| 87 | /* defines for VIA HW cursor registers */ |
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| 88 | #define VIA_REG_CURSOR_MODE 0x2D0 |
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| 89 | #define VIA_REG_CURSOR_POS 0x2D4 |
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| 90 | #define VIA_REG_CURSOR_ORG 0x2D8 |
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| 91 | #define VIA_REG_CURSOR_BG 0x2DC |
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| 92 | #define VIA_REG_CURSOR_FG 0x2E0 |
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| 93 | |
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| 94 | /* VIA_REG_GEMODE(0x04): GE mode */ |
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| 95 | #define VIA_GEM_8bpp 0x00000000 |
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| 96 | #define VIA_GEM_16bpp 0x00000100 |
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| 97 | #define VIA_GEM_32bpp 0x00000300 |
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| 98 | |
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| 99 | /* VIA_REG_GECMD(0x00): 2D Engine Command */ |
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| 100 | #define VIA_GEC_NOOP 0x00000000 |
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| 101 | #define VIA_GEC_BLT 0x00000001 |
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| 102 | #define VIA_GEC_LINE 0x00000005 |
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| 103 | |
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| 104 | /* Rotate Command */ |
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| 105 | #define VIA_GEC_ROT 0x00000008 |
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| 106 | |
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| 107 | #define VIA_GEC_SRC_XY 0x00000000 |
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| 108 | #define VIA_GEC_SRC_LINEAR 0x00000010 |
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| 109 | #define VIA_GEC_DST_XY 0x00000000 |
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| 110 | #define VIA_GEC_DST_LINRAT 0x00000020 |
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| 111 | |
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| 112 | #define VIA_GEC_SRC_FB 0x00000000 |
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| 113 | #define VIA_GEC_SRC_SYS 0x00000040 |
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| 114 | #define VIA_GEC_DST_FB 0x00000000 |
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| 115 | #define VIA_GEC_DST_SYS 0x00000080 |
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| 116 | |
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| 117 | /* source is mono */ |
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| 118 | #define VIA_GEC_SRC_MONO 0x00000100 |
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| 119 | /* pattern is mono */ |
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| 120 | #define VIA_GEC_PAT_MONO 0x00000200 |
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| 121 | /* mono src is opaque */ |
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| 122 | #define VIA_GEC_MSRC_OPAQUE 0x00000000 |
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| 123 | /* mono src is transparent */ |
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| 124 | #define VIA_GEC_MSRC_TRANS 0x00000400 |
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| 125 | /* pattern is in frame buffer */ |
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| 126 | #define VIA_GEC_PAT_FB 0x00000000 |
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| 127 | /* pattern is from reg setting */ |
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| 128 | #define VIA_GEC_PAT_REG 0x00000800 |
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| 129 | |
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| 130 | #define VIA_GEC_CLIP_DISABLE 0x00000000 |
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| 131 | #define VIA_GEC_CLIP_ENABLE 0x00001000 |
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| 132 | |
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| 133 | #define VIA_GEC_FIXCOLOR_PAT 0x00002000 |
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| 134 | |
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| 135 | #define VIA_GEC_INCX 0x00000000 |
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| 136 | #define VIA_GEC_DECY 0x00004000 |
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| 137 | #define VIA_GEC_INCY 0x00000000 |
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| 138 | #define VIA_GEC_DECX 0x00008000 |
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| 139 | /* mono pattern is opaque */ |
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| 140 | #define VIA_GEC_MPAT_OPAQUE 0x00000000 |
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| 141 | /* mono pattern is transparent */ |
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| 142 | #define VIA_GEC_MPAT_TRANS 0x00010000 |
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| 143 | |
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| 144 | #define VIA_GEC_MONO_UNPACK 0x00000000 |
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| 145 | #define VIA_GEC_MONO_PACK 0x00020000 |
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| 146 | #define VIA_GEC_MONO_DWORD 0x00000000 |
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| 147 | #define VIA_GEC_MONO_WORD 0x00040000 |
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| 148 | #define VIA_GEC_MONO_BYTE 0x00080000 |
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| 149 | |
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| 150 | #define VIA_GEC_LASTPIXEL_ON 0x00000000 |
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| 151 | #define VIA_GEC_LASTPIXEL_OFF 0x00100000 |
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| 152 | #define VIA_GEC_X_MAJOR 0x00000000 |
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| 153 | #define VIA_GEC_Y_MAJOR 0x00200000 |
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| 154 | #define VIA_GEC_QUICK_START 0x00800000 |
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| 155 | |
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| 156 | /* defines for VIA 3D registers */ |
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| 157 | #define VIA_REG_STATUS 0x400 |
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| 158 | #define VIA_REG_CR_TRANSET 0x41C |
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| 159 | #define VIA_REG_CR_TRANSPACE 0x420 |
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| 160 | #define VIA_REG_TRANSET 0x43C |
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| 161 | #define VIA_REG_TRANSPACE 0x440 |
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| 162 | |
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| 163 | /* VIA_REG_STATUS(0x400): Engine Status */ |
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| 164 | |
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| 165 | /* Command Regulator is busy */ |
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| 166 | #define VIA_CMD_RGTR_BUSY 0x00000080 |
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| 167 | /* 2D Engine is busy */ |
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| 168 | #define VIA_2D_ENG_BUSY 0x00000002 |
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| 169 | /* 3D Engine is busy */ |
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| 170 | #define VIA_3D_ENG_BUSY 0x00000001 |
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| 171 | /* Virtual Queue is busy */ |
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| 172 | #define VIA_VR_QUEUE_BUSY 0x00020000 |
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| 173 | |
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| 174 | /* VIA_REG_STATUS(0x400): Engine Status for H5 */ |
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| 175 | #define VIA_CMD_RGTR_BUSY_H5 0x00000010 /* Command Regulator is busy */ |
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| 176 | #define VIA_2D_ENG_BUSY_H5 0x00000002 /* 2D Engine is busy */ |
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| 177 | #define VIA_3D_ENG_BUSY_H5 0x00001FE1 /* 3D Engine is busy */ |
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| 178 | #define VIA_VR_QUEUE_BUSY_H5 0x00000004 /* Virtual Queue is busy */ |
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| 179 | |
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| 180 | /* VIA_REG_STATUS(0x400): Engine Status for VT3353/3409 */ |
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| 181 | #define VIA_CMD_RGTR_BUSY_M1 0x00000010 /* Command Regulator is busy */ |
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| 182 | #define VIA_2D_ENG_BUSY_M1 0x00000002 /* 2D Engine is busy */ |
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| 183 | #define VIA_3D_ENG_BUSY_M1 0x00001FE1 /* 3D Engine is busy */ |
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| 184 | #define VIA_VR_QUEUE_BUSY_M1 0x00000004 /* Virtual Queue is busy */ |
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| 185 | |
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| 186 | #define MAXLOOP 0xFFFFFF |
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| 187 | |
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| 188 | #define VIA_BITBLT_COLOR 1 |
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| 189 | #define VIA_BITBLT_MONO 2 |
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| 190 | #define VIA_BITBLT_FILL 3 |
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| 191 | |
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| 192 | int viafb_setup_engine(struct fb_info *info); |
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| 193 | void viafb_reset_engine(struct viafb_par *viapar); |
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| 194 | void viafb_show_hw_cursor(struct fb_info *info, int Status); |
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| 195 | void viafb_wait_engine_idle(struct fb_info *info); |
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| 196 | |
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| 197 | #endif /* __ACCEL_H__ */ |
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| 198 | |
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