1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. |
4 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. |
5 | |
6 | */ |
7 | |
8 | #include <linux/via-core.h> |
9 | #include "global.h" |
10 | |
11 | struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01}, |
12 | {VIASR, SR15, 0x02, 0x02}, |
13 | {VIASR, SR16, 0xBF, 0x08}, |
14 | {VIASR, SR17, 0xFF, 0x1F}, |
15 | {VIASR, SR18, 0xFF, 0x4E}, |
16 | {VIASR, SR1A, 0xFB, 0x08}, |
17 | {VIASR, SR1E, 0x0F, 0x01}, |
18 | {VIASR, SR2A, 0xFF, 0x00}, |
19 | {VIACR, CR32, 0xFF, 0x00}, |
20 | {VIACR, CR33, 0xFF, 0x00}, |
21 | {VIACR, CR35, 0xFF, 0x00}, |
22 | {VIACR, CR36, 0x08, 0x00}, |
23 | {VIACR, CR69, 0xFF, 0x00}, |
24 | {VIACR, CR6A, 0xFF, 0x40}, |
25 | {VIACR, CR6B, 0xFF, 0x00}, |
26 | {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ |
27 | {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ |
28 | {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ |
29 | {VIACR, CR8B, 0xFF, 0x69}, /* LCD Power Sequence Control 0 */ |
30 | {VIACR, CR8C, 0xFF, 0x57}, /* LCD Power Sequence Control 1 */ |
31 | {VIACR, CR8D, 0xFF, 0x00}, /* LCD Power Sequence Control 2 */ |
32 | {VIACR, CR8E, 0xFF, 0x7B}, /* LCD Power Sequence Control 3 */ |
33 | {VIACR, CR8F, 0xFF, 0x03}, /* LCD Power Sequence Control 4 */ |
34 | {VIACR, CR90, 0xFF, 0x30}, /* LCD Power Sequence Control 5 */ |
35 | {VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */ |
36 | {VIACR, CR96, 0xFF, 0x00}, |
37 | {VIACR, CR97, 0xFF, 0x00}, |
38 | {VIACR, CR99, 0xFF, 0x00}, |
39 | {VIACR, CR9B, 0xFF, 0x00} |
40 | }; |
41 | |
42 | /* Video Mode Table for VT3314 chipset*/ |
43 | /* Common Setting for Video Mode */ |
44 | struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01}, |
45 | {VIASR, SR15, 0x02, 0x02}, |
46 | {VIASR, SR16, 0xBF, 0x08}, |
47 | {VIASR, SR17, 0xFF, 0x1F}, |
48 | {VIASR, SR18, 0xFF, 0x4E}, |
49 | {VIASR, SR1A, 0xFB, 0x82}, |
50 | {VIASR, SR1B, 0xFF, 0xF0}, |
51 | {VIASR, SR1F, 0xFF, 0x00}, |
52 | {VIASR, SR1E, 0xFF, 0x01}, |
53 | {VIASR, SR22, 0xFF, 0x1F}, |
54 | {VIASR, SR2A, 0x0F, 0x00}, |
55 | {VIASR, SR2E, 0xFF, 0xFF}, |
56 | {VIASR, SR3F, 0xFF, 0xFF}, |
57 | {VIASR, SR40, 0xF7, 0x00}, |
58 | {VIASR, CR30, 0xFF, 0x04}, |
59 | {VIACR, CR32, 0xFF, 0x00}, |
60 | {VIACR, CR33, 0x7F, 0x00}, |
61 | {VIACR, CR35, 0xFF, 0x00}, |
62 | {VIACR, CR36, 0xFF, 0x31}, |
63 | {VIACR, CR41, 0xFF, 0x80}, |
64 | {VIACR, CR42, 0xFF, 0x00}, |
65 | {VIACR, CR55, 0x80, 0x00}, |
66 | {VIACR, CR5D, 0x80, 0x00}, /*Horizontal Retrace Start bit[11] should be 0*/ |
67 | {VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */ |
68 | {VIACR, CR69, 0xFF, 0x00}, |
69 | {VIACR, CR6A, 0xFD, 0x40}, |
70 | {VIACR, CR6B, 0xFF, 0x00}, |
71 | {VIACR, CR77, 0xFF, 0x00}, /* LCD scaling Factor */ |
72 | {VIACR, CR78, 0xFF, 0x00}, /* LCD scaling Factor */ |
73 | {VIACR, CR79, 0xFF, 0x00}, /* LCD scaling Factor */ |
74 | {VIACR, CR9F, 0x03, 0x00}, /* LCD scaling Factor */ |
75 | {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ |
76 | {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ |
77 | {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ |
78 | {VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */ |
79 | {VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */ |
80 | {VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */ |
81 | {VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */ |
82 | {VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */ |
83 | {VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */ |
84 | {VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */ |
85 | {VIACR, CR96, 0xFF, 0x00}, |
86 | {VIACR, CR97, 0xFF, 0x00}, |
87 | {VIACR, CR99, 0xFF, 0x00}, |
88 | {VIACR, CR9B, 0xFF, 0x00}, |
89 | {VIACR, CR9D, 0xFF, 0x80}, |
90 | {VIACR, CR9E, 0xFF, 0x80} |
91 | }; |
92 | |
93 | struct io_reg KM400_ModeXregs[] = { |
94 | {VIASR, SR10, 0xFF, 0x01}, /* Unlock Register */ |
95 | {VIASR, SR16, 0xFF, 0x08}, /* Display FIFO threshold Control */ |
96 | {VIASR, SR17, 0xFF, 0x1F}, /* Display FIFO Control */ |
97 | {VIASR, SR18, 0xFF, 0x4E}, /* GFX PREQ threshold */ |
98 | {VIASR, SR1A, 0xFF, 0x0a}, /* GFX PREQ threshold */ |
99 | {VIASR, SR1F, 0xFF, 0x00}, /* Memory Control 0 */ |
100 | {VIASR, SR1B, 0xFF, 0xF0}, /* Power Management Control 0 */ |
101 | {VIASR, SR1E, 0xFF, 0x01}, /* Power Management Control */ |
102 | {VIASR, SR20, 0xFF, 0x00}, /* Sequencer Arbiter Control 0 */ |
103 | {VIASR, SR21, 0xFF, 0x00}, /* Sequencer Arbiter Control 1 */ |
104 | {VIASR, SR22, 0xFF, 0x1F}, /* Display Arbiter Control 1 */ |
105 | {VIASR, SR2A, 0xFF, 0x00}, /* Power Management Control 5 */ |
106 | {VIASR, SR2D, 0xFF, 0xFF}, /* Power Management Control 1 */ |
107 | {VIASR, SR2E, 0xFF, 0xFF}, /* Power Management Control 2 */ |
108 | {VIACR, CR33, 0xFF, 0x00}, |
109 | {VIACR, CR55, 0x80, 0x00}, |
110 | {VIACR, CR5D, 0x80, 0x00}, |
111 | {VIACR, CR36, 0xFF, 0x01}, /* Power Mangement 3 */ |
112 | {VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */ |
113 | {VIACR, CR6A, 0x20, 0x20}, /* Extended FIFO On */ |
114 | {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ |
115 | {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ |
116 | {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ |
117 | {VIACR, CR8B, 0xFF, 0x2D}, /* LCD Power Sequence Control 0 */ |
118 | {VIACR, CR8C, 0xFF, 0x2D}, /* LCD Power Sequence Control 1 */ |
119 | {VIACR, CR8D, 0xFF, 0xC8}, /* LCD Power Sequence Control 2 */ |
120 | {VIACR, CR8E, 0xFF, 0x36}, /* LCD Power Sequence Control 3 */ |
121 | {VIACR, CR8F, 0xFF, 0x00}, /* LCD Power Sequence Control 4 */ |
122 | {VIACR, CR90, 0xFF, 0x10}, /* LCD Power Sequence Control 5 */ |
123 | {VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */ |
124 | {VIACR, CR96, 0xFF, 0x03}, /* DVP0 ; DVP0 Clock Skew */ |
125 | {VIACR, CR97, 0xFF, 0x03}, /* DFP high ; DFPH Clock Skew */ |
126 | {VIACR, CR99, 0xFF, 0x03}, /* DFP low ; DFPL Clock Skew*/ |
127 | {VIACR, CR9B, 0xFF, 0x07} /* DVI on DVP1 ; DVP1 Clock Skew*/ |
128 | }; |
129 | |
130 | /* For VT3324: Common Setting for Video Mode */ |
131 | struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01}, |
132 | {VIASR, SR15, 0x02, 0x02}, |
133 | {VIASR, SR16, 0xBF, 0x08}, |
134 | {VIASR, SR17, 0xFF, 0x1F}, |
135 | {VIASR, SR18, 0xFF, 0x4E}, |
136 | {VIASR, SR1A, 0xFB, 0x08}, |
137 | {VIASR, SR1B, 0xFF, 0xF0}, |
138 | {VIASR, SR1E, 0xFF, 0x01}, |
139 | {VIASR, SR2A, 0xFF, 0x00}, |
140 | {VIASR, SR2D, 0xC0, 0xC0}, /* delayed E3_ECK */ |
141 | {VIACR, CR32, 0xFF, 0x00}, |
142 | {VIACR, CR33, 0xFF, 0x00}, |
143 | {VIACR, CR35, 0xFF, 0x00}, |
144 | {VIACR, CR36, 0x08, 0x00}, |
145 | {VIACR, CR47, 0xC8, 0x00}, /* Clear VCK Plus. */ |
146 | {VIACR, CR69, 0xFF, 0x00}, |
147 | {VIACR, CR6A, 0xFF, 0x40}, |
148 | {VIACR, CR6B, 0xFF, 0x00}, |
149 | {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ |
150 | {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ |
151 | {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ |
152 | {VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */ |
153 | {VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */ |
154 | {VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */ |
155 | {VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */ |
156 | {VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */ |
157 | {VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */ |
158 | {VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */ |
159 | {VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */ |
160 | {VIACR, CR96, 0xFF, 0x00}, |
161 | {VIACR, CR97, 0xFF, 0x00}, |
162 | {VIACR, CR99, 0xFF, 0x00}, |
163 | {VIACR, CR9B, 0xFF, 0x00} |
164 | }; |
165 | |
166 | struct io_reg VX855_ModeXregs[] = { |
167 | {VIASR, SR10, 0xFF, 0x01}, |
168 | {VIASR, SR15, 0x02, 0x02}, |
169 | {VIASR, SR16, 0xBF, 0x08}, |
170 | {VIASR, SR17, 0xFF, 0x1F}, |
171 | {VIASR, SR18, 0xFF, 0x4E}, |
172 | {VIASR, SR1A, 0xFB, 0x08}, |
173 | {VIASR, SR1B, 0xFF, 0xF0}, |
174 | {VIASR, SR1E, 0x07, 0x01}, |
175 | {VIASR, SR2A, 0xF0, 0x00}, |
176 | {VIASR, SR58, 0xFF, 0x00}, |
177 | {VIASR, SR59, 0xFF, 0x00}, |
178 | {VIASR, SR2D, 0xC0, 0xC0}, /* delayed E3_ECK */ |
179 | {VIACR, CR32, 0xFF, 0x00}, |
180 | {VIACR, CR33, 0x7F, 0x00}, |
181 | {VIACR, CR35, 0xFF, 0x00}, |
182 | {VIACR, CR36, 0x08, 0x00}, |
183 | {VIACR, CR69, 0xFF, 0x00}, |
184 | {VIACR, CR6A, 0xFD, 0x60}, |
185 | {VIACR, CR6B, 0xFF, 0x00}, |
186 | {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ |
187 | {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ |
188 | {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ |
189 | {VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */ |
190 | {VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */ |
191 | {VIACR, CR96, 0xFF, 0x00}, |
192 | {VIACR, CR97, 0xFF, 0x00}, |
193 | {VIACR, CR99, 0xFF, 0x00}, |
194 | {VIACR, CR9B, 0xFF, 0x00}, |
195 | {VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */ |
196 | }; |
197 | |
198 | /* Video Mode Table */ |
199 | /* Common Setting for Video Mode */ |
200 | struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00}, |
201 | {VIASR, SR2A, 0x0F, 0x00}, |
202 | {VIASR, SR15, 0x02, 0x02}, |
203 | {VIASR, SR16, 0xBF, 0x08}, |
204 | {VIASR, SR17, 0xFF, 0x1F}, |
205 | {VIASR, SR18, 0xFF, 0x4E}, |
206 | {VIASR, SR1A, 0xFB, 0x08}, |
207 | |
208 | {VIACR, CR32, 0xFF, 0x00}, |
209 | {VIACR, CR35, 0xFF, 0x00}, |
210 | {VIACR, CR36, 0x08, 0x00}, |
211 | {VIACR, CR6A, 0xFF, 0x80}, |
212 | {VIACR, CR6A, 0xFF, 0xC0}, |
213 | |
214 | {VIACR, CR55, 0x80, 0x00}, |
215 | {VIACR, CR5D, 0x80, 0x00}, |
216 | |
217 | {VIAGR, GR20, 0xFF, 0x00}, |
218 | {VIAGR, GR21, 0xFF, 0x00}, |
219 | {VIAGR, GR22, 0xFF, 0x00}, |
220 | |
221 | }; |
222 | |
223 | /* Mode:1024X768 */ |
224 | struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C}, |
225 | {VIASR, 0x18, 0xFF, 0x4C} |
226 | }; |
227 | |
228 | struct patch_table res_patch_table[] = { |
229 | {ARRAY_SIZE(PM1024x768), PM1024x768} |
230 | }; |
231 | |
232 | /* struct VPITTable { |
233 | unsigned char Misc; |
234 | unsigned char SR[StdSR]; |
235 | unsigned char CR[StdCR]; |
236 | unsigned char GR[StdGR]; |
237 | unsigned char AR[StdAR]; |
238 | };*/ |
239 | |
240 | struct VPITTable VPIT = { |
241 | /* Msic */ |
242 | 0xC7, |
243 | /* Sequencer */ |
244 | {0x01, 0x0F, 0x00, 0x0E}, |
245 | /* Graphic Controller */ |
246 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF}, |
247 | /* Attribute Controller */ |
248 | {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
249 | 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, |
250 | 0x01, 0x00, 0x0F, 0x00} |
251 | }; |
252 | |
253 | /********************/ |
254 | /* Mode Table */ |
255 | /********************/ |
256 | |
257 | static const struct fb_videomode viafb_modes[] = { |
258 | {NULL, .name: 60, .refresh: 480, .xres: 640, .yres: 40285, .pixclock: 72, .left_margin: 24, .right_margin: 19, .upper_margin: 1, .lower_margin: 48, .hsync_len: 3, FB_SYNC_VERT_HIGH_ACT, .sync: 0, .vmode: 0}, |
259 | {NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2, 0, 0, 0}, |
260 | {NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3, 0, 0, 0}, |
261 | {NULL, 85, 640, 480, 27780, 80, 56, 25, 1, 56, 3, 0, 0, 0}, |
262 | {NULL, 100, 640, 480, 23167, 104, 40, 25, 1, 64, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
263 | {NULL, 120, 640, 480, 19081, 104, 40, 31, 1, 64, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
264 | {NULL, 60, 720, 480, 37426, 88, 16, 13, 1, 72, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
265 | {NULL, 60, 720, 576, 30611, 96, 24, 17, 1, 72, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
266 | {NULL, 60, 800, 600, 25131, 88, 40, 23, 1, 128, 4, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
267 | {NULL, 75, 800, 600, 20202, 160, 16, 21, 1, 80, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
268 | {NULL, 85, 800, 600, 17790, 152, 32, 27, 1, 64, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
269 | {NULL, 100, 800, 600, 14667, 136, 48, 32, 1, 88, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
270 | {NULL, 120, 800, 600, 11911, 144, 56, 39, 1, 88, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
271 | {NULL, 60, 800, 480, 33602, 96, 24, 10, 3, 72, 7, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
272 | {NULL, 60, 848, 480, 31565, 104, 24, 12, 3, 80, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
273 | {NULL, 60, 856, 480, 31517, 104, 16, 13, 1, 88, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
274 | {NULL, 60, 1024, 512, 24218, 136, 32, 15, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
275 | {NULL, 60, 1024, 600, 20423, 144, 40, 18, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
276 | {NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6, 0, 0, 0}, |
277 | {NULL, 75, 1024, 768, 12703, 176, 16, 28, 1, 96, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
278 | {NULL, 85, 1024, 768, 10581, 208, 48, 36, 1, 96, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
279 | {NULL, 100, 1024, 768, 8825, 184, 72, 42, 1, 112, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
280 | {NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
281 | {NULL, 60, 1280, 768, 12478, 200, 64, 23, 1, 136, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
282 | {NULL, 50, 1280, 768, 15342, 184, 56, 19, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
283 | {NULL, 60, 960, 600, 21964, 128, 32, 15, 3, 96, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
284 | {NULL, 60, 1000, 600, 20803, 144, 40, 18, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
285 | {NULL, 60, 1024, 576, 21278, 144, 40, 17, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
286 | {NULL, 60, 1088, 612, 18825, 152, 48, 16, 3, 104, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
287 | {NULL, 60, 1152, 720, 14974, 168, 56, 19, 3, 112, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
288 | {NULL, 60, 1200, 720, 14248, 184, 56, 22, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
289 | {NULL, 49, 1200, 900, 17703, 21, 11, 1, 1, 32, 10, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
290 | {NULL, 60, 1280, 600, 16259, 184, 56, 18, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
291 | {NULL, 60, 1280, 800, 11938, 200, 72, 22, 3, 128, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
292 | {NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
293 | {NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
294 | {NULL, 75, 1280, 1024, 7409, 248, 16, 38, 1, 144, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
295 | {NULL, 85, 1280, 1024, 6351, 224, 64, 44, 1, 160, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
296 | {NULL, 60, 1360, 768, 11759, 208, 72, 22, 3, 136, 5, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
297 | {NULL, 60, 1368, 768, 11646, 216, 72, 23, 1, 144, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
298 | {NULL, 50, 1368, 768, 14301, 200, 56, 19, 1, 144, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
299 | {NULL, 60, 1368, 768, 11646, 216, 72, 23, 1, 144, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
300 | {NULL, 60, 1440, 900, 9372, 232, 80, 25, 3, 152, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
301 | {NULL, 75, 1440, 900, 7311, 248, 96, 33, 3, 152, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
302 | {NULL, 60, 1440, 1040, 7993, 248, 96, 33, 1, 152, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
303 | {NULL, 60, 1600, 900, 8449, 256, 88, 26, 3, 168, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
304 | {NULL, 60, 1600, 1024, 7333, 272, 104, 32, 1, 168, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
305 | {NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
306 | {NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
307 | {NULL, 60, 1680, 1050, 6832, 280, 104, 30, 3, 176, 6, 0, 0, 0}, |
308 | {NULL, 75, 1680, 1050, 5339, 296, 120, 40, 3, 176, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
309 | {NULL, 60, 1792, 1344, 4883, 328, 128, 46, 1, 200, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
310 | {NULL, 60, 1856, 1392, 4581, 352, 96, 43, 1, 224, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
311 | {NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 208, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
312 | {NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
313 | {NULL, 60, 2048, 1536, 3738, 376, 152, 49, 3, 224, 4, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
314 | {NULL, 60, 1280, 720, 13484, 216, 112, 20, 5, 40, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
315 | {NULL, 50, 1280, 720, 16538, 176, 48, 17, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
316 | {NULL, 60, 1920, 1080, 5776, 328, 128, 32, 3, 200, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
317 | {NULL, 60, 1920, 1200, 5164, 336, 136, 36, 3, 200, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
318 | {NULL, 60, 1400, 1050, 8210, 232, 88, 32, 3, 144, 4, FB_SYNC_VERT_HIGH_ACT, 0, 0}, |
319 | {NULL, 75, 1400, 1050, 6398, 248, 104, 42, 3, 144, 4, FB_SYNC_VERT_HIGH_ACT, 0, 0} }; |
320 | |
321 | static const struct fb_videomode viafb_rb_modes[] = { |
322 | {NULL, 60, 1360, 768, 13879, 80, 48, 14, 3, 32, 5, FB_SYNC_HOR_HIGH_ACT, 0, 0}, |
323 | {NULL, 60, 1440, 900, 11249, 80, 48, 17, 3, 32, 6, FB_SYNC_HOR_HIGH_ACT, 0, 0}, |
324 | {NULL, 60, 1400, 1050, 9892, 80, 48, 23, 3, 32, 4, FB_SYNC_HOR_HIGH_ACT, 0, 0}, |
325 | {NULL, 60, 1600, 900, 10226, 80, 48, 18, 3, 32, 5, FB_SYNC_HOR_HIGH_ACT, 0, 0}, |
326 | {NULL, 60, 1680, 1050, 8387, 80, 48, 21, 3, 32, 6, FB_SYNC_HOR_HIGH_ACT, 0, 0}, |
327 | {NULL, 60, 1920, 1080, 7212, 80, 48, 23, 3, 32, 5, FB_SYNC_HOR_HIGH_ACT, 0, 0}, |
328 | {NULL, 60, 1920, 1200, 6488, 80, 48, 26, 3, 32, 6, FB_SYNC_HOR_HIGH_ACT, 0, 0} }; |
329 | |
330 | int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs); |
331 | int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs); |
332 | int NUM_TOTAL_KM400_ModeXregs = ARRAY_SIZE(KM400_ModeXregs); |
333 | int NUM_TOTAL_CX700_ModeXregs = ARRAY_SIZE(CX700_ModeXregs); |
334 | int NUM_TOTAL_VX855_ModeXregs = ARRAY_SIZE(VX855_ModeXregs); |
335 | int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs); |
336 | int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table); |
337 | |
338 | |
339 | static const struct fb_videomode *get_best_mode( |
340 | const struct fb_videomode *modes, int n, |
341 | int hres, int vres, int refresh) |
342 | { |
343 | const struct fb_videomode *best = NULL; |
344 | int i; |
345 | |
346 | for (i = 0; i < n; i++) { |
347 | if (modes[i].xres != hres || modes[i].yres != vres) |
348 | continue; |
349 | |
350 | if (!best || abs(modes[i].refresh - refresh) < |
351 | abs(best->refresh - refresh)) |
352 | best = &modes[i]; |
353 | } |
354 | |
355 | return best; |
356 | } |
357 | |
358 | const struct fb_videomode *viafb_get_best_mode(int hres, int vres, int refresh) |
359 | { |
360 | return get_best_mode(modes: viafb_modes, ARRAY_SIZE(viafb_modes), |
361 | hres, vres, refresh); |
362 | } |
363 | |
364 | const struct fb_videomode *viafb_get_best_rb_mode(int hres, int vres, |
365 | int refresh) |
366 | { |
367 | return get_best_mode(modes: viafb_rb_modes, ARRAY_SIZE(viafb_rb_modes), |
368 | hres, vres, refresh); |
369 | } |
370 | |