| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * GOVR registers list for WM8505 chips |
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| 4 | * |
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| 5 | * Copyright (C) 2010 Ed Spiridonov <edo.rus@gmail.com> |
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| 6 | * Based on VIA/WonderMedia wm8510-govrh-reg.h |
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| 7 | * http://github.com/projectgus/kernel_wm8505/blob/wm8505_2.6.29/ |
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| 8 | * drivers/video/wmt/register/wm8510/wm8510-govrh-reg.h |
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| 9 | */ |
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| 10 | |
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| 11 | #ifndef _WM8505FB_REGS_H |
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| 12 | #define _WM8505FB_REGS_H |
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| 13 | |
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| 14 | /* |
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| 15 | * Color space select register, default value 0x1c |
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| 16 | * BIT0 GOVRH_DVO_YUV2RGB_ENABLE |
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| 17 | * BIT1 GOVRH_VGA_YUV2RGB_ENABLE |
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| 18 | * BIT2 GOVRH_RGB_MODE |
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| 19 | * BIT3 GOVRH_DAC_CLKINV |
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| 20 | * BIT4 GOVRH_BLANK_ZERO |
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| 21 | */ |
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| 22 | #define WMT_GOVR_COLORSPACE 0x1e4 |
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| 23 | /* |
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| 24 | * Another colorspace select register, default value 1 |
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| 25 | * BIT0 GOVRH_DVO_RGB |
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| 26 | * BIT1 GOVRH_DVO_YUV422 |
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| 27 | */ |
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| 28 | #define WMT_GOVR_COLORSPACE1 0x30 |
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| 29 | |
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| 30 | #define WMT_GOVR_CONTRAST 0x1b8 |
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| 31 | #define WMT_GOVR_BRGHTNESS 0x1bc /* incompatible with RGB? */ |
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| 32 | |
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| 33 | /* Framubeffer address */ |
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| 34 | #define WMT_GOVR_FBADDR 0x90 |
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| 35 | #define WMT_GOVR_FBADDR1 0x94 /* UV offset in YUV mode */ |
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| 36 | |
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| 37 | /* Offset of visible window */ |
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| 38 | #define WMT_GOVR_XPAN 0xa4 |
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| 39 | #define WMT_GOVR_YPAN 0xa0 |
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| 40 | |
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| 41 | #define WMT_GOVR_XRES 0x98 |
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| 42 | #define WMT_GOVR_XRES_VIRTUAL 0x9c |
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| 43 | |
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| 44 | #define WMT_GOVR_MIF_ENABLE 0x80 |
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| 45 | #define WMT_GOVR_FHI 0xa8 |
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| 46 | #define WMT_GOVR_REG_UPDATE 0xe4 |
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| 47 | |
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| 48 | /* |
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| 49 | * BIT0 GOVRH_DVO_OUTWIDTH |
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| 50 | * BIT1 GOVRH_DVO_SYNC_POLAR |
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| 51 | * BIT2 GOVRH_DVO_ENABLE |
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| 52 | */ |
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| 53 | #define WMT_GOVR_DVO_SET 0x148 |
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| 54 | |
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| 55 | /* Timing generator? */ |
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| 56 | #define WMT_GOVR_TG 0x100 |
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| 57 | |
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| 58 | /* Timings */ |
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| 59 | #define WMT_GOVR_TIMING_H_ALL 0x108 |
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| 60 | #define WMT_GOVR_TIMING_V_ALL 0x10c |
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| 61 | #define WMT_GOVR_TIMING_V_START 0x110 |
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| 62 | #define WMT_GOVR_TIMING_V_END 0x114 |
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| 63 | #define WMT_GOVR_TIMING_H_START 0x118 |
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| 64 | #define WMT_GOVR_TIMING_H_END 0x11c |
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| 65 | #define WMT_GOVR_TIMING_V_SYNC 0x128 |
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| 66 | #define WMT_GOVR_TIMING_H_SYNC 0x12c |
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| 67 | |
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| 68 | #endif /* _WM8505FB_REGS_H */ |
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| 69 | |
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