1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Imagination Technologies PowerDown Controller Watchdog Timer. |
4 | * |
5 | * Copyright (c) 2014 Imagination Technologies Ltd. |
6 | * |
7 | * Based on drivers/watchdog/sunxi_wdt.c Copyright (c) 2013 Carlo Caione |
8 | * 2012 Henrik Nordstrom |
9 | * |
10 | * Notes |
11 | * ----- |
12 | * The timeout value is rounded to the next power of two clock cycles. |
13 | * This is configured using the PDC_WDT_CONFIG register, according to this |
14 | * formula: |
15 | * |
16 | * timeout = 2^(delay + 1) clock cycles |
17 | * |
18 | * Where 'delay' is the value written in PDC_WDT_CONFIG register. |
19 | * |
20 | * Therefore, the hardware only allows to program watchdog timeouts, expressed |
21 | * as a power of two number of watchdog clock cycles. The current implementation |
22 | * guarantees that the actual watchdog timeout will be _at least_ the value |
23 | * programmed in the imgpdg_wdt driver. |
24 | * |
25 | * The following table shows how the user-configured timeout relates |
26 | * to the actual hardware timeout (watchdog clock @ 40000 Hz): |
27 | * |
28 | * input timeout | WD_DELAY | actual timeout |
29 | * ----------------------------------- |
30 | * 10 | 18 | 13 seconds |
31 | * 20 | 19 | 26 seconds |
32 | * 30 | 20 | 52 seconds |
33 | * 60 | 21 | 104 seconds |
34 | * |
35 | * Albeit coarse, this granularity would suffice most watchdog uses. |
36 | * If the platform allows it, the user should be able to change the watchdog |
37 | * clock rate and achieve a finer timeout granularity. |
38 | */ |
39 | |
40 | #include <linux/clk.h> |
41 | #include <linux/io.h> |
42 | #include <linux/log2.h> |
43 | #include <linux/module.h> |
44 | #include <linux/mod_devicetable.h> |
45 | #include <linux/platform_device.h> |
46 | #include <linux/slab.h> |
47 | #include <linux/watchdog.h> |
48 | |
49 | /* registers */ |
50 | #define PDC_WDT_SOFT_RESET 0x00 |
51 | #define PDC_WDT_CONFIG 0x04 |
52 | #define PDC_WDT_CONFIG_ENABLE BIT(31) |
53 | #define PDC_WDT_CONFIG_DELAY_MASK 0x1f |
54 | |
55 | #define PDC_WDT_TICKLE1 0x08 |
56 | #define PDC_WDT_TICKLE1_MAGIC 0xabcd1234 |
57 | #define PDC_WDT_TICKLE2 0x0c |
58 | #define PDC_WDT_TICKLE2_MAGIC 0x4321dcba |
59 | |
60 | #define PDC_WDT_TICKLE_STATUS_MASK 0x7 |
61 | #define PDC_WDT_TICKLE_STATUS_SHIFT 0 |
62 | #define PDC_WDT_TICKLE_STATUS_HRESET 0x0 /* Hard reset */ |
63 | #define PDC_WDT_TICKLE_STATUS_TIMEOUT 0x1 /* Timeout */ |
64 | #define PDC_WDT_TICKLE_STATUS_TICKLE 0x2 /* Tickled incorrectly */ |
65 | #define PDC_WDT_TICKLE_STATUS_SRESET 0x3 /* Soft reset */ |
66 | #define PDC_WDT_TICKLE_STATUS_USER 0x4 /* User reset */ |
67 | |
68 | /* Timeout values are in seconds */ |
69 | #define PDC_WDT_MIN_TIMEOUT 1 |
70 | #define PDC_WDT_DEF_TIMEOUT 64 |
71 | |
72 | static int heartbeat; |
73 | module_param(heartbeat, int, 0); |
74 | MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds " |
75 | "(default=" __MODULE_STRING(PDC_WDT_DEF_TIMEOUT) ")" ); |
76 | |
77 | static bool nowayout = WATCHDOG_NOWAYOUT; |
78 | module_param(nowayout, bool, 0); |
79 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " |
80 | "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")" ); |
81 | |
82 | struct pdc_wdt_dev { |
83 | struct watchdog_device wdt_dev; |
84 | struct clk *wdt_clk; |
85 | struct clk *sys_clk; |
86 | void __iomem *base; |
87 | }; |
88 | |
89 | static int pdc_wdt_keepalive(struct watchdog_device *wdt_dev) |
90 | { |
91 | struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdd: wdt_dev); |
92 | |
93 | writel(PDC_WDT_TICKLE1_MAGIC, addr: wdt->base + PDC_WDT_TICKLE1); |
94 | writel(PDC_WDT_TICKLE2_MAGIC, addr: wdt->base + PDC_WDT_TICKLE2); |
95 | |
96 | return 0; |
97 | } |
98 | |
99 | static int pdc_wdt_stop(struct watchdog_device *wdt_dev) |
100 | { |
101 | unsigned int val; |
102 | struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdd: wdt_dev); |
103 | |
104 | val = readl(addr: wdt->base + PDC_WDT_CONFIG); |
105 | val &= ~PDC_WDT_CONFIG_ENABLE; |
106 | writel(val, addr: wdt->base + PDC_WDT_CONFIG); |
107 | |
108 | /* Must tickle to finish the stop */ |
109 | pdc_wdt_keepalive(wdt_dev); |
110 | |
111 | return 0; |
112 | } |
113 | |
114 | static void __pdc_wdt_set_timeout(struct pdc_wdt_dev *wdt) |
115 | { |
116 | unsigned long clk_rate = clk_get_rate(clk: wdt->wdt_clk); |
117 | unsigned int val; |
118 | |
119 | val = readl(addr: wdt->base + PDC_WDT_CONFIG) & ~PDC_WDT_CONFIG_DELAY_MASK; |
120 | val |= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1; |
121 | writel(val, addr: wdt->base + PDC_WDT_CONFIG); |
122 | } |
123 | |
124 | static int pdc_wdt_set_timeout(struct watchdog_device *wdt_dev, |
125 | unsigned int new_timeout) |
126 | { |
127 | struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdd: wdt_dev); |
128 | |
129 | wdt->wdt_dev.timeout = new_timeout; |
130 | |
131 | __pdc_wdt_set_timeout(wdt); |
132 | |
133 | return 0; |
134 | } |
135 | |
136 | /* Start the watchdog timer (delay should already be set) */ |
137 | static int pdc_wdt_start(struct watchdog_device *wdt_dev) |
138 | { |
139 | unsigned int val; |
140 | struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdd: wdt_dev); |
141 | |
142 | __pdc_wdt_set_timeout(wdt); |
143 | |
144 | val = readl(addr: wdt->base + PDC_WDT_CONFIG); |
145 | val |= PDC_WDT_CONFIG_ENABLE; |
146 | writel(val, addr: wdt->base + PDC_WDT_CONFIG); |
147 | |
148 | return 0; |
149 | } |
150 | |
151 | static int pdc_wdt_restart(struct watchdog_device *wdt_dev, |
152 | unsigned long action, void *data) |
153 | { |
154 | struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdd: wdt_dev); |
155 | |
156 | /* Assert SOFT_RESET */ |
157 | writel(val: 0x1, addr: wdt->base + PDC_WDT_SOFT_RESET); |
158 | |
159 | return 0; |
160 | } |
161 | |
162 | static const struct watchdog_info pdc_wdt_info = { |
163 | .identity = "IMG PDC Watchdog" , |
164 | .options = WDIOF_SETTIMEOUT | |
165 | WDIOF_KEEPALIVEPING | |
166 | WDIOF_MAGICCLOSE, |
167 | }; |
168 | |
169 | static const struct watchdog_ops pdc_wdt_ops = { |
170 | .owner = THIS_MODULE, |
171 | .start = pdc_wdt_start, |
172 | .stop = pdc_wdt_stop, |
173 | .ping = pdc_wdt_keepalive, |
174 | .set_timeout = pdc_wdt_set_timeout, |
175 | .restart = pdc_wdt_restart, |
176 | }; |
177 | |
178 | static int pdc_wdt_probe(struct platform_device *pdev) |
179 | { |
180 | struct device *dev = &pdev->dev; |
181 | u64 div; |
182 | int val; |
183 | unsigned long clk_rate; |
184 | struct pdc_wdt_dev *pdc_wdt; |
185 | |
186 | pdc_wdt = devm_kzalloc(dev, size: sizeof(*pdc_wdt), GFP_KERNEL); |
187 | if (!pdc_wdt) |
188 | return -ENOMEM; |
189 | |
190 | pdc_wdt->base = devm_platform_ioremap_resource(pdev, index: 0); |
191 | if (IS_ERR(ptr: pdc_wdt->base)) |
192 | return PTR_ERR(ptr: pdc_wdt->base); |
193 | |
194 | pdc_wdt->sys_clk = devm_clk_get_enabled(dev, id: "sys" ); |
195 | if (IS_ERR(ptr: pdc_wdt->sys_clk)) { |
196 | dev_err(dev, "failed to get the sys clock\n" ); |
197 | return PTR_ERR(ptr: pdc_wdt->sys_clk); |
198 | } |
199 | |
200 | pdc_wdt->wdt_clk = devm_clk_get_enabled(dev, id: "wdt" ); |
201 | if (IS_ERR(ptr: pdc_wdt->wdt_clk)) { |
202 | dev_err(dev, "failed to get the wdt clock\n" ); |
203 | return PTR_ERR(ptr: pdc_wdt->wdt_clk); |
204 | } |
205 | |
206 | /* We use the clock rate to calculate the max timeout */ |
207 | clk_rate = clk_get_rate(clk: pdc_wdt->wdt_clk); |
208 | if (clk_rate == 0) { |
209 | dev_err(dev, "failed to get clock rate\n" ); |
210 | return -EINVAL; |
211 | } |
212 | |
213 | if (order_base_2(clk_rate) > PDC_WDT_CONFIG_DELAY_MASK + 1) { |
214 | dev_err(dev, "invalid clock rate\n" ); |
215 | return -EINVAL; |
216 | } |
217 | |
218 | if (order_base_2(clk_rate) == 0) |
219 | pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT + 1; |
220 | else |
221 | pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT; |
222 | |
223 | pdc_wdt->wdt_dev.info = &pdc_wdt_info; |
224 | pdc_wdt->wdt_dev.ops = &pdc_wdt_ops; |
225 | |
226 | div = 1ULL << (PDC_WDT_CONFIG_DELAY_MASK + 1); |
227 | do_div(div, clk_rate); |
228 | pdc_wdt->wdt_dev.max_timeout = div; |
229 | pdc_wdt->wdt_dev.timeout = PDC_WDT_DEF_TIMEOUT; |
230 | pdc_wdt->wdt_dev.parent = dev; |
231 | watchdog_set_drvdata(wdd: &pdc_wdt->wdt_dev, data: pdc_wdt); |
232 | |
233 | watchdog_init_timeout(wdd: &pdc_wdt->wdt_dev, timeout_parm: heartbeat, dev); |
234 | |
235 | pdc_wdt_stop(wdt_dev: &pdc_wdt->wdt_dev); |
236 | |
237 | /* Find what caused the last reset */ |
238 | val = readl(addr: pdc_wdt->base + PDC_WDT_TICKLE1); |
239 | val = (val & PDC_WDT_TICKLE_STATUS_MASK) >> PDC_WDT_TICKLE_STATUS_SHIFT; |
240 | switch (val) { |
241 | case PDC_WDT_TICKLE_STATUS_TICKLE: |
242 | case PDC_WDT_TICKLE_STATUS_TIMEOUT: |
243 | pdc_wdt->wdt_dev.bootstatus |= WDIOF_CARDRESET; |
244 | dev_info(dev, "watchdog module last reset due to timeout\n" ); |
245 | break; |
246 | case PDC_WDT_TICKLE_STATUS_HRESET: |
247 | dev_info(dev, |
248 | "watchdog module last reset due to hard reset\n" ); |
249 | break; |
250 | case PDC_WDT_TICKLE_STATUS_SRESET: |
251 | dev_info(dev, |
252 | "watchdog module last reset due to soft reset\n" ); |
253 | break; |
254 | case PDC_WDT_TICKLE_STATUS_USER: |
255 | dev_info(dev, |
256 | "watchdog module last reset due to user reset\n" ); |
257 | break; |
258 | default: |
259 | dev_info(dev, "contains an illegal status code (%08x)\n" , val); |
260 | break; |
261 | } |
262 | |
263 | watchdog_set_nowayout(wdd: &pdc_wdt->wdt_dev, nowayout); |
264 | watchdog_set_restart_priority(wdd: &pdc_wdt->wdt_dev, priority: 128); |
265 | |
266 | platform_set_drvdata(pdev, data: pdc_wdt); |
267 | |
268 | watchdog_stop_on_reboot(wdd: &pdc_wdt->wdt_dev); |
269 | watchdog_stop_on_unregister(wdd: &pdc_wdt->wdt_dev); |
270 | return devm_watchdog_register_device(dev, &pdc_wdt->wdt_dev); |
271 | } |
272 | |
273 | static const struct of_device_id pdc_wdt_match[] = { |
274 | { .compatible = "img,pdc-wdt" }, |
275 | {} |
276 | }; |
277 | MODULE_DEVICE_TABLE(of, pdc_wdt_match); |
278 | |
279 | static struct platform_driver pdc_wdt_driver = { |
280 | .driver = { |
281 | .name = "imgpdc-wdt" , |
282 | .of_match_table = pdc_wdt_match, |
283 | }, |
284 | .probe = pdc_wdt_probe, |
285 | }; |
286 | module_platform_driver(pdc_wdt_driver); |
287 | |
288 | MODULE_AUTHOR("Jude Abraham <Jude.Abraham@imgtec.com>" ); |
289 | MODULE_AUTHOR("Naidu Tellapati <Naidu.Tellapati@imgtec.com>" ); |
290 | MODULE_DESCRIPTION("Imagination Technologies PDC Watchdog Timer Driver" ); |
291 | MODULE_LICENSE("GPL v2" ); |
292 | |