1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
4 | */ |
5 | |
6 | #ifndef __DW_HDMI__ |
7 | #define __DW_HDMI__ |
8 | |
9 | #include <sound/hdmi-codec.h> |
10 | |
11 | struct drm_display_info; |
12 | struct drm_display_mode; |
13 | struct drm_encoder; |
14 | struct dw_hdmi; |
15 | struct platform_device; |
16 | |
17 | /** |
18 | * DOC: Supported input formats and encodings |
19 | * |
20 | * Depending on the Hardware configuration of the Controller IP, it supports |
21 | * a subset of the following input formats and encodings on its internal |
22 | * 48bit bus. |
23 | * |
24 | * +----------------------+----------------------------------+------------------------------+ |
25 | * | Format Name | Format Code | Encodings | |
26 | * +----------------------+----------------------------------+------------------------------+ |
27 | * | RGB 4:4:4 8bit | ``MEDIA_BUS_FMT_RGB888_1X24`` | ``V4L2_YCBCR_ENC_DEFAULT`` | |
28 | * +----------------------+----------------------------------+------------------------------+ |
29 | * | RGB 4:4:4 10bits | ``MEDIA_BUS_FMT_RGB101010_1X30`` | ``V4L2_YCBCR_ENC_DEFAULT`` | |
30 | * +----------------------+----------------------------------+------------------------------+ |
31 | * | RGB 4:4:4 12bits | ``MEDIA_BUS_FMT_RGB121212_1X36`` | ``V4L2_YCBCR_ENC_DEFAULT`` | |
32 | * +----------------------+----------------------------------+------------------------------+ |
33 | * | RGB 4:4:4 16bits | ``MEDIA_BUS_FMT_RGB161616_1X48`` | ``V4L2_YCBCR_ENC_DEFAULT`` | |
34 | * +----------------------+----------------------------------+------------------------------+ |
35 | * | YCbCr 4:4:4 8bit | ``MEDIA_BUS_FMT_YUV8_1X24`` | ``V4L2_YCBCR_ENC_601`` | |
36 | * | | | or ``V4L2_YCBCR_ENC_709`` | |
37 | * | | | or ``V4L2_YCBCR_ENC_XV601`` | |
38 | * | | | or ``V4L2_YCBCR_ENC_XV709`` | |
39 | * +----------------------+----------------------------------+------------------------------+ |
40 | * | YCbCr 4:4:4 10bits | ``MEDIA_BUS_FMT_YUV10_1X30`` | ``V4L2_YCBCR_ENC_601`` | |
41 | * | | | or ``V4L2_YCBCR_ENC_709`` | |
42 | * | | | or ``V4L2_YCBCR_ENC_XV601`` | |
43 | * | | | or ``V4L2_YCBCR_ENC_XV709`` | |
44 | * +----------------------+----------------------------------+------------------------------+ |
45 | * | YCbCr 4:4:4 12bits | ``MEDIA_BUS_FMT_YUV12_1X36`` | ``V4L2_YCBCR_ENC_601`` | |
46 | * | | | or ``V4L2_YCBCR_ENC_709`` | |
47 | * | | | or ``V4L2_YCBCR_ENC_XV601`` | |
48 | * | | | or ``V4L2_YCBCR_ENC_XV709`` | |
49 | * +----------------------+----------------------------------+------------------------------+ |
50 | * | YCbCr 4:4:4 16bits | ``MEDIA_BUS_FMT_YUV16_1X48`` | ``V4L2_YCBCR_ENC_601`` | |
51 | * | | | or ``V4L2_YCBCR_ENC_709`` | |
52 | * | | | or ``V4L2_YCBCR_ENC_XV601`` | |
53 | * | | | or ``V4L2_YCBCR_ENC_XV709`` | |
54 | * +----------------------+----------------------------------+------------------------------+ |
55 | * | YCbCr 4:2:2 8bit | ``MEDIA_BUS_FMT_UYVY8_1X16`` | ``V4L2_YCBCR_ENC_601`` | |
56 | * | | | or ``V4L2_YCBCR_ENC_709`` | |
57 | * +----------------------+----------------------------------+------------------------------+ |
58 | * | YCbCr 4:2:2 10bits | ``MEDIA_BUS_FMT_UYVY10_1X20`` | ``V4L2_YCBCR_ENC_601`` | |
59 | * | | | or ``V4L2_YCBCR_ENC_709`` | |
60 | * +----------------------+----------------------------------+------------------------------+ |
61 | * | YCbCr 4:2:2 12bits | ``MEDIA_BUS_FMT_UYVY12_1X24`` | ``V4L2_YCBCR_ENC_601`` | |
62 | * | | | or ``V4L2_YCBCR_ENC_709`` | |
63 | * +----------------------+----------------------------------+------------------------------+ |
64 | * | YCbCr 4:2:0 8bit | ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` | ``V4L2_YCBCR_ENC_601`` | |
65 | * | | | or ``V4L2_YCBCR_ENC_709`` | |
66 | * +----------------------+----------------------------------+------------------------------+ |
67 | * | YCbCr 4:2:0 10bits | ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``| ``V4L2_YCBCR_ENC_601`` | |
68 | * | | | or ``V4L2_YCBCR_ENC_709`` | |
69 | * +----------------------+----------------------------------+------------------------------+ |
70 | * | YCbCr 4:2:0 12bits | ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``| ``V4L2_YCBCR_ENC_601`` | |
71 | * | | | or ``V4L2_YCBCR_ENC_709`` | |
72 | * +----------------------+----------------------------------+------------------------------+ |
73 | * | YCbCr 4:2:0 16bits | ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``| ``V4L2_YCBCR_ENC_601`` | |
74 | * | | | or ``V4L2_YCBCR_ENC_709`` | |
75 | * +----------------------+----------------------------------+------------------------------+ |
76 | */ |
77 | |
78 | enum { |
79 | DW_HDMI_RES_8, |
80 | DW_HDMI_RES_10, |
81 | DW_HDMI_RES_12, |
82 | DW_HDMI_RES_MAX, |
83 | }; |
84 | |
85 | enum dw_hdmi_phy_type { |
86 | DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00, |
87 | DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2, |
88 | DW_HDMI_PHY_DWC_MHL_PHY = 0xc2, |
89 | DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2, |
90 | DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2, |
91 | DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3, |
92 | DW_HDMI_PHY_VENDOR_PHY = 0xfe, |
93 | }; |
94 | |
95 | struct dw_hdmi_mpll_config { |
96 | unsigned long mpixelclock; |
97 | struct { |
98 | u16 cpce; |
99 | u16 gmp; |
100 | } res[DW_HDMI_RES_MAX]; |
101 | }; |
102 | |
103 | struct dw_hdmi_curr_ctrl { |
104 | unsigned long mpixelclock; |
105 | u16 curr[DW_HDMI_RES_MAX]; |
106 | }; |
107 | |
108 | struct dw_hdmi_phy_config { |
109 | unsigned long mpixelclock; |
110 | u16 sym_ctr; /*clock symbol and transmitter control*/ |
111 | u16 term; /*transmission termination value*/ |
112 | u16 vlev_ctr; /* voltage level control */ |
113 | }; |
114 | |
115 | struct dw_hdmi_phy_ops { |
116 | int (*init)(struct dw_hdmi *hdmi, void *data, |
117 | const struct drm_display_info *display, |
118 | const struct drm_display_mode *mode); |
119 | void (*disable)(struct dw_hdmi *hdmi, void *data); |
120 | enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data); |
121 | void (*update_hpd)(struct dw_hdmi *hdmi, void *data, |
122 | bool force, bool disabled, bool rxsense); |
123 | void (*setup_hpd)(struct dw_hdmi *hdmi, void *data); |
124 | }; |
125 | |
126 | struct dw_hdmi_plat_data { |
127 | struct regmap *regm; |
128 | |
129 | unsigned int output_port; |
130 | |
131 | unsigned long input_bus_encoding; |
132 | bool use_drm_infoframe; |
133 | bool ycbcr_420_allowed; |
134 | |
135 | /* |
136 | * Private data passed to all the .mode_valid() and .configure_phy() |
137 | * callback functions. |
138 | */ |
139 | void *priv_data; |
140 | |
141 | /* Platform-specific mode validation (optional). */ |
142 | enum drm_mode_status (*mode_valid)(struct dw_hdmi *hdmi, void *data, |
143 | const struct drm_display_info *info, |
144 | const struct drm_display_mode *mode); |
145 | |
146 | /* Platform-specific audio enable/disable (optional) */ |
147 | void (*enable_audio)(struct dw_hdmi *hdmi, int channel, |
148 | int width, int rate, int non_pcm); |
149 | void (*disable_audio)(struct dw_hdmi *hdmi); |
150 | |
151 | /* Vendor PHY support */ |
152 | const struct dw_hdmi_phy_ops *phy_ops; |
153 | const char *phy_name; |
154 | void *phy_data; |
155 | unsigned int phy_force_vendor; |
156 | |
157 | /* Synopsys PHY support */ |
158 | const struct dw_hdmi_mpll_config *mpll_cfg; |
159 | const struct dw_hdmi_curr_ctrl *cur_ctr; |
160 | const struct dw_hdmi_phy_config *phy_config; |
161 | int (*configure_phy)(struct dw_hdmi *hdmi, void *data, |
162 | unsigned long mpixelclock); |
163 | |
164 | unsigned int disable_cec : 1; |
165 | }; |
166 | |
167 | struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, |
168 | const struct dw_hdmi_plat_data *plat_data); |
169 | void dw_hdmi_remove(struct dw_hdmi *hdmi); |
170 | void dw_hdmi_unbind(struct dw_hdmi *hdmi); |
171 | struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, |
172 | struct drm_encoder *encoder, |
173 | const struct dw_hdmi_plat_data *plat_data); |
174 | |
175 | void dw_hdmi_resume(struct dw_hdmi *hdmi); |
176 | |
177 | void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense); |
178 | |
179 | int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn, |
180 | struct device *codec_dev); |
181 | void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm); |
182 | void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width); |
183 | void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); |
184 | void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt); |
185 | void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, u8 *channel_status); |
186 | void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca); |
187 | void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); |
188 | void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); |
189 | void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi, |
190 | const struct drm_display_info *display); |
191 | |
192 | /* PHY configuration */ |
193 | void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address); |
194 | void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, |
195 | unsigned char addr); |
196 | |
197 | void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi); |
198 | |
199 | void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable); |
200 | void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable); |
201 | void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi); |
202 | |
203 | enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, |
204 | void *data); |
205 | void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, |
206 | bool force, bool disabled, bool rxsense); |
207 | void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data); |
208 | |
209 | bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi); |
210 | |
211 | #endif /* __IMX_HDMI_H__ */ |
212 | |