1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/delay.h>
27#include <linux/i2c.h>
28
29#include <drm/display/drm_dp.h>
30#include <drm/drm_connector.h>
31
32struct drm_device;
33struct drm_dp_aux;
34struct drm_panel;
35
36bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
37 int lane_count);
38bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
39 int lane_count);
40u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
41 int lane);
42u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
43 int lane);
44u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
45 int lane);
46
47int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
48 enum drm_dp_phy dp_phy, bool uhbr);
49int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
50 enum drm_dp_phy dp_phy, bool uhbr);
51
52void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
54void drm_dp_lttpr_link_train_clock_recovery_delay(void);
55void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
57void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
58 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
59
60int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
61bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
62 int lane_count);
63bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
64 int lane_count);
65bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
66bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
67bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]);
68
69u8 drm_dp_link_rate_to_bw_code(int link_rate);
70int drm_dp_bw_code_to_link_rate(u8 link_bw);
71
72const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
73
74/**
75 * struct drm_dp_vsc_sdp - drm DP VSC SDP
76 *
77 * This structure represents a DP VSC SDP of drm
78 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
79 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
80 *
81 * @sdp_type: secondary-data packet type
82 * @revision: revision number
83 * @length: number of valid data bytes
84 * @pixelformat: pixel encoding format
85 * @colorimetry: colorimetry format
86 * @bpc: bit per color
87 * @dynamic_range: dynamic range information
88 * @content_type: CTA-861-G defines content types and expected processing by a sink device
89 */
90struct drm_dp_vsc_sdp {
91 unsigned char sdp_type;
92 unsigned char revision;
93 unsigned char length;
94 enum dp_pixelformat pixelformat;
95 enum dp_colorimetry colorimetry;
96 int bpc;
97 enum dp_dynamic_range dynamic_range;
98 enum dp_content_type content_type;
99};
100
101void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
102 const struct drm_dp_vsc_sdp *vsc);
103
104int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
105
106static inline int
107drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
108{
109 return drm_dp_bw_code_to_link_rate(link_bw: dpcd[DP_MAX_LINK_RATE]);
110}
111
112static inline u8
113drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
114{
115 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
116}
117
118static inline bool
119drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
120{
121 return dpcd[DP_DPCD_REV] >= 0x11 &&
122 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
123}
124
125static inline bool
126drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
127{
128 return dpcd[DP_DPCD_REV] >= 0x11 &&
129 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
130}
131
132static inline bool
133drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
134{
135 return dpcd[DP_DPCD_REV] >= 0x12 &&
136 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
137}
138
139static inline bool
140drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
141{
142 return dpcd[DP_DPCD_REV] >= 0x11 ||
143 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5;
144}
145
146static inline bool
147drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
148{
149 return dpcd[DP_DPCD_REV] >= 0x14 &&
150 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
151}
152
153static inline u8
154drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
155{
156 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
157 DP_TRAINING_PATTERN_MASK;
158}
159
160static inline bool
161drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
162{
163 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
164}
165
166/* DP/eDP DSC support */
167u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
168 bool is_edp);
169u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
170int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
171 u8 dsc_bpc[3]);
172
173static inline bool
174drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
175{
176 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
177 DP_DSC_DECOMPRESSION_IS_SUPPORTED;
178}
179
180static inline u16
181drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
182{
183 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
184 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
185 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8);
186}
187
188static inline u32
189drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
190{
191 /* Max Slicewidth = Number of Pixels * 320 */
192 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
193 DP_DSC_SLICE_WIDTH_MULTIPLIER;
194}
195
196/**
197 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format
198 * @dsc_dpcd : DSC-capability DPCDs of the sink
199 * @output_format: output_format which is to be checked
200 *
201 * Returns true if the sink supports DSC with the given output_format, false otherwise.
202 */
203static inline bool
204drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format)
205{
206 return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format;
207}
208
209/* Forward Error Correction Support on DP 1.4 */
210static inline bool
211drm_dp_sink_supports_fec(const u8 fec_capable)
212{
213 return fec_capable & DP_FEC_CAPABLE;
214}
215
216static inline bool
217drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
218{
219 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
220}
221
222static inline bool
223drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
224{
225 return dpcd[DP_EDP_CONFIGURATION_CAP] &
226 DP_ALTERNATE_SCRAMBLER_RESET_CAP;
227}
228
229/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
230static inline bool
231drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
232{
233 return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
234 DP_MSA_TIMING_PAR_IGNORED;
235}
236
237/**
238 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
239 * @edp_dpcd: The DPCD to check
240 *
241 * Note that currently this function will return %false for panels which support various DPCD
242 * backlight features but which require the brightness be set through PWM, and don't support setting
243 * the brightness level via the DPCD.
244 *
245 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
246 * otherwise
247 */
248static inline bool
249drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
250{
251 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
252}
253
254/*
255 * DisplayPort AUX channel
256 */
257
258/**
259 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
260 * @address: address of the (first) register to access
261 * @request: contains the type of transaction (see DP_AUX_* macros)
262 * @reply: upon completion, contains the reply type of the transaction
263 * @buffer: pointer to a transmission or reception buffer
264 * @size: size of @buffer
265 */
266struct drm_dp_aux_msg {
267 unsigned int address;
268 u8 request;
269 u8 reply;
270 void *buffer;
271 size_t size;
272};
273
274struct cec_adapter;
275struct drm_connector;
276struct drm_edid;
277
278/**
279 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
280 * @lock: mutex protecting this struct
281 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
282 * @connector: the connector this CEC adapter is associated with
283 * @unregister_work: unregister the CEC adapter
284 */
285struct drm_dp_aux_cec {
286 struct mutex lock;
287 struct cec_adapter *adap;
288 struct drm_connector *connector;
289 struct delayed_work unregister_work;
290};
291
292/**
293 * struct drm_dp_aux - DisplayPort AUX channel
294 *
295 * An AUX channel can also be used to transport I2C messages to a sink. A
296 * typical application of that is to access an EDID that's present in the sink
297 * device. The @transfer() function can also be used to execute such
298 * transactions. The drm_dp_aux_register() function registers an I2C adapter
299 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call
300 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long
301 * transfers by default; if a partial response is received, the adapter will
302 * drop down to the size given by the partial response for this transaction
303 * only.
304 */
305struct drm_dp_aux {
306 /**
307 * @name: user-visible name of this AUX channel and the
308 * I2C-over-AUX adapter.
309 *
310 * It's also used to specify the name of the I2C adapter. If set
311 * to %NULL, dev_name() of @dev will be used.
312 */
313 const char *name;
314
315 /**
316 * @ddc: I2C adapter that can be used for I2C-over-AUX
317 * communication
318 */
319 struct i2c_adapter ddc;
320
321 /**
322 * @dev: pointer to struct device that is the parent for this
323 * AUX channel.
324 */
325 struct device *dev;
326
327 /**
328 * @drm_dev: pointer to the &drm_device that owns this AUX channel.
329 * Beware, this may be %NULL before drm_dp_aux_register() has been
330 * called.
331 *
332 * It should be set to the &drm_device that will be using this AUX
333 * channel as early as possible. For many graphics drivers this should
334 * happen before drm_dp_aux_init(), however it's perfectly fine to set
335 * this field later so long as it's assigned before calling
336 * drm_dp_aux_register().
337 */
338 struct drm_device *drm_dev;
339
340 /**
341 * @crtc: backpointer to the crtc that is currently using this
342 * AUX channel
343 */
344 struct drm_crtc *crtc;
345
346 /**
347 * @hw_mutex: internal mutex used for locking transfers.
348 *
349 * Note that if the underlying hardware is shared among multiple
350 * channels, the driver needs to do additional locking to
351 * prevent concurrent access.
352 */
353 struct mutex hw_mutex;
354
355 /**
356 * @crc_work: worker that captures CRCs for each frame
357 */
358 struct work_struct crc_work;
359
360 /**
361 * @crc_count: counter of captured frame CRCs
362 */
363 u8 crc_count;
364
365 /**
366 * @transfer: transfers a message representing a single AUX
367 * transaction.
368 *
369 * This is a hardware-specific implementation of how
370 * transactions are executed that the drivers must provide.
371 *
372 * A pointer to a &drm_dp_aux_msg structure describing the
373 * transaction is passed into this function. Upon success, the
374 * implementation should return the number of payload bytes that
375 * were transferred, or a negative error-code on failure.
376 *
377 * Helpers will propagate these errors, with the exception of
378 * the %-EBUSY error, which causes a transaction to be retried.
379 * On a short, helpers will return %-EPROTO to make it simpler
380 * to check for failure.
381 *
382 * The @transfer() function must only modify the reply field of
383 * the &drm_dp_aux_msg structure. The retry logic and i2c
384 * helpers assume this is the case.
385 *
386 * Also note that this callback can be called no matter the
387 * state @dev is in and also no matter what state the panel is
388 * in. It's expected:
389 *
390 * - If the @dev providing the AUX bus is currently unpowered then
391 * it will power itself up for the transfer.
392 *
393 * - If we're on eDP (using a drm_panel) and the panel is not in a
394 * state where it can respond (it's not powered or it's in a
395 * low power state) then this function may return an error, but
396 * not crash. It's up to the caller of this code to make sure that
397 * the panel is powered on if getting an error back is not OK. If a
398 * drm_panel driver is initiating a DP AUX transfer it may power
399 * itself up however it wants. All other code should ensure that
400 * the pre_enable() bridge chain (which eventually calls the
401 * drm_panel prepare function) has powered the panel.
402 */
403 ssize_t (*transfer)(struct drm_dp_aux *aux,
404 struct drm_dp_aux_msg *msg);
405
406 /**
407 * @wait_hpd_asserted: wait for HPD to be asserted
408 *
409 * This is mainly useful for eDP panels drivers to wait for an eDP
410 * panel to finish powering on. This is an optional function.
411 *
412 * This function will efficiently wait for the HPD signal to be
413 * asserted. The `wait_us` parameter that is passed in says that we
414 * know that the HPD signal is expected to be asserted within `wait_us`
415 * microseconds. This function could wait for longer than `wait_us` if
416 * the logic in the DP controller has a long debouncing time. The
417 * important thing is that if this function returns success that the
418 * DP controller is ready to send AUX transactions.
419 *
420 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time
421 * expired and HPD wasn't asserted. This function should not print
422 * timeout errors to the log.
423 *
424 * The semantics of this function are designed to match the
425 * readx_poll_timeout() function. That means a `wait_us` of 0 means
426 * to wait forever. Like readx_poll_timeout(), this function may sleep.
427 *
428 * NOTE: this function specifically reports the state of the HPD pin
429 * that's associated with the DP AUX channel. This is different from
430 * the HPD concept in much of the rest of DRM which is more about
431 * physical presence of a display. For eDP, for instance, a display is
432 * assumed always present even if the HPD pin is deasserted.
433 */
434 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us);
435
436 /**
437 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
438 */
439 unsigned i2c_nack_count;
440 /**
441 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
442 */
443 unsigned i2c_defer_count;
444 /**
445 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
446 */
447 struct drm_dp_aux_cec cec;
448 /**
449 * @is_remote: Is this AUX CH actually using sideband messaging.
450 */
451 bool is_remote;
452};
453
454int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset);
455ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
456 void *buffer, size_t size);
457ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
458 void *buffer, size_t size);
459
460/**
461 * drm_dp_dpcd_readb() - read a single byte from the DPCD
462 * @aux: DisplayPort AUX channel
463 * @offset: address of the register to read
464 * @valuep: location where the value of the register will be stored
465 *
466 * Returns the number of bytes transferred (1) on success, or a negative
467 * error code on failure.
468 */
469static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
470 unsigned int offset, u8 *valuep)
471{
472 return drm_dp_dpcd_read(aux, offset, buffer: valuep, size: 1);
473}
474
475/**
476 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
477 * @aux: DisplayPort AUX channel
478 * @offset: address of the register to write
479 * @value: value to write to the register
480 *
481 * Returns the number of bytes transferred (1) on success, or a negative
482 * error code on failure.
483 */
484static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
485 unsigned int offset, u8 value)
486{
487 return drm_dp_dpcd_write(aux, offset, buffer: &value, size: 1);
488}
489
490int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
491 u8 dpcd[DP_RECEIVER_CAP_SIZE]);
492
493int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
494 u8 status[DP_LINK_STATUS_SIZE]);
495
496int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
497 enum drm_dp_phy dp_phy,
498 u8 link_status[DP_LINK_STATUS_SIZE]);
499
500bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
501 u8 real_edid_checksum);
502
503int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
504 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
505 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
506bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
507 const u8 port_cap[4], u8 type);
508bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
509 const u8 port_cap[4],
510 const struct drm_edid *drm_edid);
511int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
512 const u8 port_cap[4]);
513int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
514 const u8 port_cap[4],
515 const struct drm_edid *drm_edid);
516int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
517 const u8 port_cap[4],
518 const struct drm_edid *drm_edid);
519int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
520 const u8 port_cap[4],
521 const struct drm_edid *drm_edid);
522bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
523 const u8 port_cap[4]);
524bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
525 const u8 port_cap[4]);
526struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
527 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
528 const u8 port_cap[4]);
529int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
530void drm_dp_downstream_debug(struct seq_file *m,
531 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
532 const u8 port_cap[4],
533 const struct drm_edid *drm_edid,
534 struct drm_dp_aux *aux);
535enum drm_mode_subconnector
536drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
537 const u8 port_cap[4]);
538void drm_dp_set_subconnector_property(struct drm_connector *connector,
539 enum drm_connector_status status,
540 const u8 *dpcd,
541 const u8 port_cap[4]);
542
543struct drm_dp_desc;
544bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
545 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
546 const struct drm_dp_desc *desc);
547int drm_dp_read_sink_count(struct drm_dp_aux *aux);
548
549int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
550 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
551 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
552int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
553 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
554 enum drm_dp_phy dp_phy,
555 u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
556int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
557int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
558int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
559bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
560bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
561
562void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
563void drm_dp_aux_init(struct drm_dp_aux *aux);
564int drm_dp_aux_register(struct drm_dp_aux *aux);
565void drm_dp_aux_unregister(struct drm_dp_aux *aux);
566
567int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
568int drm_dp_stop_crc(struct drm_dp_aux *aux);
569
570struct drm_dp_dpcd_ident {
571 u8 oui[3];
572 u8 device_id[6];
573 u8 hw_rev;
574 u8 sw_major_rev;
575 u8 sw_minor_rev;
576} __packed;
577
578/**
579 * struct drm_dp_desc - DP branch/sink device descriptor
580 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
581 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
582 */
583struct drm_dp_desc {
584 struct drm_dp_dpcd_ident ident;
585 u32 quirks;
586};
587
588int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
589 bool is_branch);
590
591/**
592 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
593 *
594 * Display Port sink and branch devices in the wild have a variety of bugs, try
595 * to collect them here. The quirks are shared, but it's up to the drivers to
596 * implement workarounds for them.
597 */
598enum drm_dp_quirk {
599 /**
600 * @DP_DPCD_QUIRK_CONSTANT_N:
601 *
602 * The device requires main link attributes Mvid and Nvid to be limited
603 * to 16 bits. So will give a constant value (0x8000) for compatability.
604 */
605 DP_DPCD_QUIRK_CONSTANT_N,
606 /**
607 * @DP_DPCD_QUIRK_NO_PSR:
608 *
609 * The device does not support PSR even if reports that it supports or
610 * driver still need to implement proper handling for such device.
611 */
612 DP_DPCD_QUIRK_NO_PSR,
613 /**
614 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
615 *
616 * The device does not set SINK_COUNT to a non-zero value.
617 * The driver should ignore SINK_COUNT during detection. Note that
618 * drm_dp_read_sink_count_cap() automatically checks for this quirk.
619 */
620 DP_DPCD_QUIRK_NO_SINK_COUNT,
621 /**
622 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
623 *
624 * The device supports MST DSC despite not supporting Virtual DPCD.
625 * The DSC caps can be read from the physical aux instead.
626 */
627 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
628 /**
629 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
630 *
631 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
632 * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
633 */
634 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
635};
636
637/**
638 * drm_dp_has_quirk() - does the DP device have a specific quirk
639 * @desc: Device descriptor filled by drm_dp_read_desc()
640 * @quirk: Quirk to query for
641 *
642 * Return true if DP device identified by @desc has @quirk.
643 */
644static inline bool
645drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
646{
647 return desc->quirks & BIT(quirk);
648}
649
650/**
651 * struct drm_edp_backlight_info - Probed eDP backlight info struct
652 * @pwmgen_bit_count: The pwmgen bit count
653 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
654 * @max: The maximum backlight level that may be set
655 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
656 * @aux_enable: Does the panel support the AUX enable cap?
657 * @aux_set: Does the panel support setting the brightness through AUX?
658 *
659 * This structure contains various data about an eDP backlight, which can be populated by using
660 * drm_edp_backlight_init().
661 */
662struct drm_edp_backlight_info {
663 u8 pwmgen_bit_count;
664 u8 pwm_freq_pre_divider;
665 u16 max;
666
667 bool lsb_reg_used : 1;
668 bool aux_enable : 1;
669 bool aux_set : 1;
670};
671
672int
673drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
674 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
675 u16 *current_level, u8 *current_mode);
676int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
677 u16 level);
678int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
679 u16 level);
680int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
681
682#if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
683 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)))
684
685int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux);
686
687#else
688
689static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel,
690 struct drm_dp_aux *aux)
691{
692 return 0;
693}
694
695#endif
696
697#ifdef CONFIG_DRM_DP_CEC
698void drm_dp_cec_irq(struct drm_dp_aux *aux);
699void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
700 struct drm_connector *connector);
701void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
702void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address);
703void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
704void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
705#else
706static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
707{
708}
709
710static inline void
711drm_dp_cec_register_connector(struct drm_dp_aux *aux,
712 struct drm_connector *connector)
713{
714}
715
716static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
717{
718}
719
720static inline void drm_dp_cec_attach(struct drm_dp_aux *aux,
721 u16 source_physical_address)
722{
723}
724
725static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
726 const struct edid *edid)
727{
728}
729
730static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
731{
732}
733
734#endif
735
736/**
737 * struct drm_dp_phy_test_params - DP Phy Compliance parameters
738 * @link_rate: Requested Link rate from DPCD 0x219
739 * @num_lanes: Number of lanes requested by sing through DPCD 0x220
740 * @phy_pattern: DP Phy test pattern from DPCD 0x248
741 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
742 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
743 * @enhanced_frame_cap: flag for enhanced frame capability.
744 */
745struct drm_dp_phy_test_params {
746 int link_rate;
747 u8 num_lanes;
748 u8 phy_pattern;
749 u8 hbr2_reset[2];
750 u8 custom80[10];
751 bool enhanced_frame_cap;
752};
753
754int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
755 struct drm_dp_phy_test_params *data);
756int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
757 struct drm_dp_phy_test_params *data, u8 dp_rev);
758int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
759 const u8 port_cap[4]);
760int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
761bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
762int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
763 u8 frl_mode);
764int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
765 u8 frl_type);
766int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
767int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
768
769bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
770int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
771void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
772 struct drm_connector *connector);
773bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
774int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
775int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
776int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
777int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
778int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
779int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
780bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
781 const u8 port_cap[4], u8 color_spc);
782int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
783
784#endif /* _DRM_DP_HELPER_H_ */
785

source code of linux/include/drm/display/drm_dp_helper.h