1// SPDX-License-Identifier: GPL-2.0+
2//
3// Device Tree binding constants for Actions Semi S900 Clock Management Unit
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Copyright (c) 2018 Linaro Ltd.
7
8#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
9#define __DT_BINDINGS_CLOCK_S900_CMU_H
10
11#define CLK_NONE 0
12
13/* fixed rate clocks */
14#define CLK_LOSC 1
15#define CLK_HOSC 2
16
17/* pll clocks */
18#define CLK_CORE_PLL 3
19#define CLK_DEV_PLL 4
20#define CLK_DDR_PLL 5
21#define CLK_NAND_PLL 6
22#define CLK_DISPLAY_PLL 7
23#define CLK_DSI_PLL 8
24#define CLK_ASSIST_PLL 9
25#define CLK_AUDIO_PLL 10
26
27/* system clock */
28#define CLK_CPU 15
29#define CLK_DEV 16
30#define CLK_NOC 17
31#define CLK_NOC_MUX 18
32#define CLK_NOC_DIV 19
33#define CLK_AHB 20
34#define CLK_APB 21
35#define CLK_DMAC 22
36
37/* peripheral device clock */
38#define CLK_GPIO 23
39
40#define CLK_BISP 24
41#define CLK_CSI0 25
42#define CLK_CSI1 26
43
44#define CLK_DE0 27
45#define CLK_DE1 28
46#define CLK_DE2 29
47#define CLK_DE3 30
48#define CLK_DSI 32
49
50#define CLK_GPU 33
51#define CLK_GPU_CORE 34
52#define CLK_GPU_MEM 35
53#define CLK_GPU_SYS 36
54
55#define CLK_HDE 37
56#define CLK_I2C0 38
57#define CLK_I2C1 39
58#define CLK_I2C2 40
59#define CLK_I2C3 41
60#define CLK_I2C4 42
61#define CLK_I2C5 43
62#define CLK_I2SRX 44
63#define CLK_I2STX 45
64#define CLK_IMX 46
65#define CLK_LCD 47
66#define CLK_NAND0 48
67#define CLK_NAND1 49
68#define CLK_PWM0 50
69#define CLK_PWM1 51
70#define CLK_PWM2 52
71#define CLK_PWM3 53
72#define CLK_PWM4 54
73#define CLK_PWM5 55
74#define CLK_SD0 56
75#define CLK_SD1 57
76#define CLK_SD2 58
77#define CLK_SD3 59
78#define CLK_SENSOR 60
79#define CLK_SPEED_SENSOR 61
80#define CLK_SPI0 62
81#define CLK_SPI1 63
82#define CLK_SPI2 64
83#define CLK_SPI3 65
84#define CLK_THERMAL_SENSOR 66
85#define CLK_UART0 67
86#define CLK_UART1 68
87#define CLK_UART2 69
88#define CLK_UART3 70
89#define CLK_UART4 71
90#define CLK_UART5 72
91#define CLK_UART6 73
92#define CLK_VCE 74
93#define CLK_VDE 75
94
95#define CLK_USB3_480MPLL0 76
96#define CLK_USB3_480MPHY0 77
97#define CLK_USB3_5GPHY 78
98#define CLK_USB3_CCE 79
99#define CLK_USB3_MAC 80
100
101#define CLK_TIMER 83
102
103#define CLK_HDMI_AUDIO 84
104
105#define CLK_24M 85
106
107#define CLK_EDP 86
108
109#define CLK_24M_EDP 87
110#define CLK_EDP_PLL 88
111#define CLK_EDP_LINK 89
112
113#define CLK_USB2H0_PLLEN 90
114#define CLK_USB2H0_PHY 91
115#define CLK_USB2H0_CCE 92
116#define CLK_USB2H1_PLLEN 93
117#define CLK_USB2H1_PHY 94
118#define CLK_USB2H1_CCE 95
119
120#define CLK_DDR0 96
121#define CLK_DDR1 97
122#define CLK_DMM 98
123
124#define CLK_ETH_MAC 99
125#define CLK_RMII_REF 100
126
127#define CLK_NR_CLKS (CLK_RMII_REF + 1)
128
129#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */
130

source code of linux/include/dt-bindings/clock/actions,s900-cmu.h