| 1 | /* |
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| 2 | * BSD LICENSE |
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| 3 | * |
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| 4 | * Copyright(c) 2015 Broadcom Corporation. All rights reserved. |
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| 5 | * |
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| 6 | * Redistribution and use in source and binary forms, with or without |
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| 7 | * modification, are permitted provided that the following conditions |
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| 8 | * are met: |
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| 9 | * |
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| 10 | * * Redistributions of source code must retain the above copyright |
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| 11 | * notice, this list of conditions and the following disclaimer. |
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| 12 | * * Redistributions in binary form must reproduce the above copyright |
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| 13 | * notice, this list of conditions and the following disclaimer in |
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| 14 | * the documentation and/or other materials provided with the |
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| 15 | * distribution. |
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| 16 | * * Neither the name of Broadcom Corporation nor the names of its |
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| 17 | * contributors may be used to endorse or promote products derived |
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| 18 | * from this software without specific prior written permission. |
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| 19 | * |
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| 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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| 21 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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| 22 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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| 23 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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| 24 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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| 25 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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| 26 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 27 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 28 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 30 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 31 | */ |
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| 32 | |
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| 33 | #ifndef _CLOCK_BCM_NSP_H |
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| 34 | #define _CLOCK_BCM_NSP_H |
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| 35 | |
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| 36 | /* GENPLL clock channel ID */ |
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| 37 | #define BCM_NSP_GENPLL 0 |
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| 38 | #define BCM_NSP_GENPLL_PHY_CLK 1 |
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| 39 | #define BCM_NSP_GENPLL_ENET_SW_CLK 2 |
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| 40 | #define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3 |
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| 41 | #define BCM_NSP_GENPLL_IPROCFAST_CLK 4 |
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| 42 | #define BCM_NSP_GENPLL_SATA1_CLK 5 |
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| 43 | #define BCM_NSP_GENPLL_SATA2_CLK 6 |
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| 44 | |
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| 45 | /* LCPLL0 clock channel ID */ |
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| 46 | #define BCM_NSP_LCPLL0 0 |
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| 47 | #define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1 |
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| 48 | #define BCM_NSP_LCPLL0_SDIO_CLK 2 |
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| 49 | #define BCM_NSP_LCPLL0_DDR_PHY_CLK 3 |
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| 50 | |
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| 51 | #endif /* _CLOCK_BCM_NSP_H */ |
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| 52 | |
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