1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd.
4 * https://www.samsung.com
5 * Copyright (c) 2017-2022 Tesla, Inc.
6 * https://www.tesla.com
7 *
8 * The constants defined in this header are being used in dts
9 * and fsd platform driver.
10 */
11
12#ifndef _DT_BINDINGS_CLOCK_FSD_H
13#define _DT_BINDINGS_CLOCK_FSD_H
14
15/* CMU */
16#define DOUT_CMU_PLL_SHARED0_DIV4 1
17#define DOUT_CMU_PERIC_SHARED1DIV36 2
18#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 3
19#define DOUT_CMU_PERIC_SHARED0DIV20 4
20#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 5
21#define DOUT_CMU_PLL_SHARED0_DIV6 6
22#define DOUT_CMU_FSYS0_SHARED1DIV4 7
23#define DOUT_CMU_FSYS0_SHARED0DIV4 8
24#define DOUT_CMU_FSYS1_SHARED0DIV8 9
25#define DOUT_CMU_FSYS1_SHARED0DIV4 10
26#define CMU_CPUCL_SWITCH_GATE 11
27#define DOUT_CMU_IMEM_TCUCLK 12
28#define DOUT_CMU_IMEM_ACLK 13
29#define DOUT_CMU_IMEM_DMACLK 14
30#define GAT_CMU_FSYS0_SHARED0DIV4 15
31#define CMU_NR_CLK 16
32
33/* PERIC */
34#define PERIC_SCLK_UART0 1
35#define PERIC_PCLK_UART0 2
36#define PERIC_SCLK_UART1 3
37#define PERIC_PCLK_UART1 4
38#define PERIC_DMA0_IPCLKPORT_ACLK 5
39#define PERIC_DMA1_IPCLKPORT_ACLK 6
40#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 7
41#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 8
42#define PERIC_PCLK_SPI0 9
43#define PERIC_SCLK_SPI0 10
44#define PERIC_PCLK_SPI1 11
45#define PERIC_SCLK_SPI1 12
46#define PERIC_PCLK_SPI2 13
47#define PERIC_SCLK_SPI2 14
48#define PERIC_PCLK_TDM0 15
49#define PERIC_PCLK_HSI2C0 16
50#define PERIC_PCLK_HSI2C1 17
51#define PERIC_PCLK_HSI2C2 18
52#define PERIC_PCLK_HSI2C3 19
53#define PERIC_PCLK_HSI2C4 20
54#define PERIC_PCLK_HSI2C5 21
55#define PERIC_PCLK_HSI2C6 22
56#define PERIC_PCLK_HSI2C7 23
57#define PERIC_MCAN0_IPCLKPORT_CCLK 24
58#define PERIC_MCAN0_IPCLKPORT_PCLK 25
59#define PERIC_MCAN1_IPCLKPORT_CCLK 26
60#define PERIC_MCAN1_IPCLKPORT_PCLK 27
61#define PERIC_MCAN2_IPCLKPORT_CCLK 28
62#define PERIC_MCAN2_IPCLKPORT_PCLK 29
63#define PERIC_MCAN3_IPCLKPORT_CCLK 30
64#define PERIC_MCAN3_IPCLKPORT_PCLK 31
65#define PERIC_PCLK_ADCIF 32
66#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 33
67#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 34
68#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 35
69#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 36
70#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 37
71#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 38
72#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 39
73#define PERIC_HCLK_TDM0 40
74#define PERIC_PCLK_TDM1 41
75#define PERIC_HCLK_TDM1 42
76#define PERIC_EQOS_PHYRXCLK_MUX 43
77#define PERIC_EQOS_PHYRXCLK 44
78#define PERIC_DOUT_RGMII_CLK 45
79#define PERIC_NR_CLK 46
80
81/* FSYS0 */
82#define UFS0_MPHY_REFCLK_IXTAL24 1
83#define UFS0_MPHY_REFCLK_IXTAL26 2
84#define UFS1_MPHY_REFCLK_IXTAL24 3
85#define UFS1_MPHY_REFCLK_IXTAL26 4
86#define UFS0_TOP0_HCLK_BUS 5
87#define UFS0_TOP0_ACLK 6
88#define UFS0_TOP0_CLK_UNIPRO 7
89#define UFS0_TOP0_FMP_CLK 8
90#define UFS1_TOP1_HCLK_BUS 9
91#define UFS1_TOP1_ACLK 10
92#define UFS1_TOP1_CLK_UNIPRO 11
93#define UFS1_TOP1_FMP_CLK 12
94#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 13
95#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 14
96#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 15
97#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 16
98#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17
99#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 18
100#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 19
101#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20
102#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21
103#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22
104#define FSYS0_NR_CLK 23
105
106/* FSYS1 */
107#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1
108#define PCIE_LINK0_IPCLKPORT_AUX_ACLK 2
109#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 3
110#define PCIE_LINK0_IPCLKPORT_SLV_ACLK 4
111#define PCIE_LINK1_IPCLKPORT_DBI_ACLK 5
112#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6
113#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7
114#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8
115#define FSYS1_NR_CLK 9
116
117/* IMEM */
118#define IMEM_DMA0_IPCLKPORT_ACLK 1
119#define IMEM_DMA1_IPCLKPORT_ACLK 2
120#define IMEM_WDT0_IPCLKPORT_PCLK 3
121#define IMEM_WDT1_IPCLKPORT_PCLK 4
122#define IMEM_WDT2_IPCLKPORT_PCLK 5
123#define IMEM_MCT_PCLK 6
124#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 7
125#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 8
126#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9
127#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10
128#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11
129#define IMEM_NR_CLK 12
130
131/* MFC */
132#define MFC_MFC_IPCLKPORT_ACLK 1
133#define MFC_NR_CLK 2
134
135/* CAM_CSI */
136#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1
137#define CAM_CSI0_1_IPCLKPORT_I_ACLK 2
138#define CAM_CSI0_2_IPCLKPORT_I_ACLK 3
139#define CAM_CSI0_3_IPCLKPORT_I_ACLK 4
140#define CAM_CSI1_0_IPCLKPORT_I_ACLK 5
141#define CAM_CSI1_1_IPCLKPORT_I_ACLK 6
142#define CAM_CSI1_2_IPCLKPORT_I_ACLK 7
143#define CAM_CSI1_3_IPCLKPORT_I_ACLK 8
144#define CAM_CSI2_0_IPCLKPORT_I_ACLK 9
145#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10
146#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11
147#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12
148#define CAM_CSI_NR_CLK 13
149
150#endif /*_DT_BINDINGS_CLOCK_FSD_H */
151

source code of linux/include/dt-bindings/clock/fsd-clk.h