| 1 | /* SPDX-License-Identifier: GPL-2.0+ OR MIT */ |
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| 2 | /* |
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| 3 | * Meson-G12A clock tree IDs |
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| 4 | * |
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| 5 | * Copyright (c) 2018 Amlogic, Inc. All rights reserved. |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __G12A_CLKC_H |
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| 9 | #define __G12A_CLKC_H |
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| 10 | |
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| 11 | #define CLKID_SYS_PLL 0 |
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| 12 | #define CLKID_FIXED_PLL 1 |
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| 13 | #define CLKID_FCLK_DIV2 2 |
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| 14 | #define CLKID_FCLK_DIV3 3 |
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| 15 | #define CLKID_FCLK_DIV4 4 |
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| 16 | #define CLKID_FCLK_DIV5 5 |
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| 17 | #define CLKID_FCLK_DIV7 6 |
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| 18 | #define CLKID_GP0_PLL 7 |
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| 19 | #define CLKID_MPEG_SEL 8 |
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| 20 | #define CLKID_MPEG_DIV 9 |
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| 21 | #define CLKID_CLK81 10 |
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| 22 | #define CLKID_MPLL0 11 |
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| 23 | #define CLKID_MPLL1 12 |
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| 24 | #define CLKID_MPLL2 13 |
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| 25 | #define CLKID_MPLL3 14 |
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| 26 | #define CLKID_DDR 15 |
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| 27 | #define CLKID_DOS 16 |
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| 28 | #define CLKID_AUDIO_LOCKER 17 |
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| 29 | #define CLKID_MIPI_DSI_HOST 18 |
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| 30 | #define CLKID_ETH_PHY 19 |
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| 31 | #define CLKID_ISA 20 |
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| 32 | #define CLKID_PL301 21 |
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| 33 | #define CLKID_PERIPHS 22 |
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| 34 | #define CLKID_SPICC0 23 |
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| 35 | #define CLKID_I2C 24 |
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| 36 | #define CLKID_SANA 25 |
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| 37 | #define CLKID_SD 26 |
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| 38 | #define CLKID_RNG0 27 |
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| 39 | #define CLKID_UART0 28 |
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| 40 | #define CLKID_SPICC1 29 |
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| 41 | #define CLKID_HIU_IFACE 30 |
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| 42 | #define CLKID_MIPI_DSI_PHY 31 |
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| 43 | #define CLKID_ASSIST_MISC 32 |
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| 44 | #define CLKID_SD_EMMC_A 33 |
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| 45 | #define CLKID_SD_EMMC_B 34 |
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| 46 | #define CLKID_SD_EMMC_C 35 |
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| 47 | #define CLKID_AUDIO_CODEC 36 |
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| 48 | #define CLKID_AUDIO 37 |
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| 49 | #define CLKID_ETH 38 |
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| 50 | #define CLKID_DEMUX 39 |
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| 51 | #define CLKID_AUDIO_IFIFO 40 |
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| 52 | #define CLKID_ADC 41 |
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| 53 | #define CLKID_UART1 42 |
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| 54 | #define CLKID_G2D 43 |
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| 55 | #define CLKID_RESET 44 |
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| 56 | #define CLKID_PCIE_COMB 45 |
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| 57 | #define CLKID_PARSER 46 |
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| 58 | #define CLKID_USB 47 |
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| 59 | #define CLKID_PCIE_PHY 48 |
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| 60 | #define CLKID_AHB_ARB0 49 |
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| 61 | #define CLKID_AHB_DATA_BUS 50 |
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| 62 | #define CLKID_AHB_CTRL_BUS 51 |
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| 63 | #define CLKID_HTX_HDCP22 52 |
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| 64 | #define CLKID_HTX_PCLK 53 |
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| 65 | #define CLKID_BT656 54 |
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| 66 | #define CLKID_USB1_DDR_BRIDGE 55 |
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| 67 | #define CLKID_MMC_PCLK 56 |
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| 68 | #define CLKID_UART2 57 |
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| 69 | #define CLKID_VPU_INTR 58 |
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| 70 | #define CLKID_GIC 59 |
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| 71 | #define CLKID_SD_EMMC_A_CLK0 60 |
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| 72 | #define CLKID_SD_EMMC_B_CLK0 61 |
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| 73 | #define CLKID_SD_EMMC_C_CLK0 62 |
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| 74 | #define CLKID_SD_EMMC_A_CLK0_SEL 63 |
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| 75 | #define CLKID_SD_EMMC_A_CLK0_DIV 64 |
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| 76 | #define CLKID_SD_EMMC_B_CLK0_SEL 65 |
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| 77 | #define CLKID_SD_EMMC_B_CLK0_DIV 66 |
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| 78 | #define CLKID_SD_EMMC_C_CLK0_SEL 67 |
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| 79 | #define CLKID_SD_EMMC_C_CLK0_DIV 68 |
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| 80 | #define CLKID_MPLL0_DIV 69 |
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| 81 | #define CLKID_MPLL1_DIV 70 |
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| 82 | #define CLKID_MPLL2_DIV 71 |
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| 83 | #define CLKID_MPLL3_DIV 72 |
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| 84 | #define CLKID_MPLL_PREDIV 73 |
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| 85 | #define CLKID_HIFI_PLL 74 |
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| 86 | #define CLKID_FCLK_DIV2_DIV 75 |
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| 87 | #define CLKID_FCLK_DIV3_DIV 76 |
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| 88 | #define CLKID_FCLK_DIV4_DIV 77 |
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| 89 | #define CLKID_FCLK_DIV5_DIV 78 |
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| 90 | #define CLKID_FCLK_DIV7_DIV 79 |
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| 91 | #define CLKID_VCLK2_VENCI0 80 |
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| 92 | #define CLKID_VCLK2_VENCI1 81 |
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| 93 | #define CLKID_VCLK2_VENCP0 82 |
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| 94 | #define CLKID_VCLK2_VENCP1 83 |
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| 95 | #define CLKID_VCLK2_VENCT0 84 |
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| 96 | #define CLKID_VCLK2_VENCT1 85 |
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| 97 | #define CLKID_VCLK2_OTHER 86 |
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| 98 | #define CLKID_VCLK2_ENCI 87 |
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| 99 | #define CLKID_VCLK2_ENCP 88 |
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| 100 | #define CLKID_DAC_CLK 89 |
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| 101 | #define CLKID_AOCLK 90 |
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| 102 | #define CLKID_IEC958 91 |
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| 103 | #define CLKID_ENC480P 92 |
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| 104 | #define CLKID_RNG1 93 |
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| 105 | #define CLKID_VCLK2_ENCT 94 |
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| 106 | #define CLKID_VCLK2_ENCL 95 |
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| 107 | #define CLKID_VCLK2_VENCLMMC 96 |
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| 108 | #define CLKID_VCLK2_VENCL 97 |
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| 109 | #define CLKID_VCLK2_OTHER1 98 |
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| 110 | #define CLKID_FCLK_DIV2P5 99 |
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| 111 | #define CLKID_FCLK_DIV2P5_DIV 100 |
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| 112 | #define CLKID_FIXED_PLL_DCO 101 |
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| 113 | #define CLKID_SYS_PLL_DCO 102 |
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| 114 | #define CLKID_GP0_PLL_DCO 103 |
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| 115 | #define CLKID_HIFI_PLL_DCO 104 |
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| 116 | #define CLKID_DMA 105 |
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| 117 | #define CLKID_EFUSE 106 |
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| 118 | #define CLKID_ROM_BOOT 107 |
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| 119 | #define CLKID_RESET_SEC 108 |
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| 120 | #define CLKID_SEC_AHB_APB3 109 |
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| 121 | #define CLKID_VPU_0_SEL 110 |
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| 122 | #define CLKID_VPU_0_DIV 111 |
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| 123 | #define CLKID_VPU_0 112 |
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| 124 | #define CLKID_VPU_1_SEL 113 |
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| 125 | #define CLKID_VPU_1_DIV 114 |
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| 126 | #define CLKID_VPU_1 115 |
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| 127 | #define CLKID_VPU 116 |
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| 128 | #define CLKID_VAPB_0_SEL 117 |
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| 129 | #define CLKID_VAPB_0_DIV 118 |
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| 130 | #define CLKID_VAPB_0 119 |
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| 131 | #define CLKID_VAPB_1_SEL 120 |
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| 132 | #define CLKID_VAPB_1_DIV 121 |
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| 133 | #define CLKID_VAPB_1 122 |
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| 134 | #define CLKID_VAPB_SEL 123 |
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| 135 | #define CLKID_VAPB 124 |
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| 136 | #define CLKID_HDMI_PLL_DCO 125 |
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| 137 | #define CLKID_HDMI_PLL_OD 126 |
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| 138 | #define CLKID_HDMI_PLL_OD2 127 |
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| 139 | #define CLKID_HDMI_PLL 128 |
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| 140 | #define CLKID_VID_PLL 129 |
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| 141 | #define CLKID_VID_PLL_SEL 130 |
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| 142 | #define CLKID_VID_PLL_DIV 131 |
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| 143 | #define CLKID_VCLK_SEL 132 |
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| 144 | #define CLKID_VCLK2_SEL 133 |
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| 145 | #define CLKID_VCLK_INPUT 134 |
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| 146 | #define CLKID_VCLK2_INPUT 135 |
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| 147 | #define CLKID_VCLK_DIV 136 |
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| 148 | #define CLKID_VCLK2_DIV 137 |
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| 149 | #define CLKID_VCLK 138 |
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| 150 | #define CLKID_VCLK2 139 |
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| 151 | #define CLKID_VCLK_DIV2_EN 140 |
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| 152 | #define CLKID_VCLK_DIV4_EN 141 |
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| 153 | #define CLKID_VCLK_DIV6_EN 142 |
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| 154 | #define CLKID_VCLK_DIV12_EN 143 |
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| 155 | #define CLKID_VCLK2_DIV2_EN 144 |
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| 156 | #define CLKID_VCLK2_DIV4_EN 145 |
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| 157 | #define CLKID_VCLK2_DIV6_EN 146 |
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| 158 | #define CLKID_VCLK2_DIV12_EN 147 |
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| 159 | #define CLKID_VCLK_DIV1 148 |
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| 160 | #define CLKID_VCLK_DIV2 149 |
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| 161 | #define CLKID_VCLK_DIV4 150 |
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| 162 | #define CLKID_VCLK_DIV6 151 |
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| 163 | #define CLKID_VCLK_DIV12 152 |
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| 164 | #define CLKID_VCLK2_DIV1 153 |
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| 165 | #define CLKID_VCLK2_DIV2 154 |
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| 166 | #define CLKID_VCLK2_DIV4 155 |
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| 167 | #define CLKID_VCLK2_DIV6 156 |
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| 168 | #define CLKID_VCLK2_DIV12 157 |
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| 169 | #define CLKID_CTS_ENCI_SEL 158 |
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| 170 | #define CLKID_CTS_ENCP_SEL 159 |
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| 171 | #define CLKID_CTS_VDAC_SEL 160 |
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| 172 | #define CLKID_HDMI_TX_SEL 161 |
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| 173 | #define CLKID_CTS_ENCI 162 |
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| 174 | #define CLKID_CTS_ENCP 163 |
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| 175 | #define CLKID_CTS_VDAC 164 |
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| 176 | #define CLKID_HDMI_TX 165 |
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| 177 | #define CLKID_HDMI_SEL 166 |
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| 178 | #define CLKID_HDMI_DIV 167 |
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| 179 | #define CLKID_HDMI 168 |
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| 180 | #define CLKID_MALI_0_SEL 169 |
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| 181 | #define CLKID_MALI_0_DIV 170 |
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| 182 | #define CLKID_MALI_0 171 |
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| 183 | #define CLKID_MALI_1_SEL 172 |
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| 184 | #define CLKID_MALI_1_DIV 173 |
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| 185 | #define CLKID_MALI_1 174 |
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| 186 | #define CLKID_MALI 175 |
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| 187 | #define CLKID_MPLL_50M_DIV 176 |
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| 188 | #define CLKID_MPLL_50M 177 |
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| 189 | #define CLKID_SYS_PLL_DIV16_EN 178 |
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| 190 | #define CLKID_SYS_PLL_DIV16 179 |
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| 191 | #define CLKID_CPU_CLK_DYN0_SEL 180 |
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| 192 | #define CLKID_CPU_CLK_DYN0_DIV 181 |
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| 193 | #define CLKID_CPU_CLK_DYN0 182 |
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| 194 | #define CLKID_CPU_CLK_DYN1_SEL 183 |
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| 195 | #define CLKID_CPU_CLK_DYN1_DIV 184 |
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| 196 | #define CLKID_CPU_CLK_DYN1 185 |
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| 197 | #define CLKID_CPU_CLK_DYN 186 |
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| 198 | #define CLKID_CPU_CLK 187 |
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| 199 | #define CLKID_CPU_CLK_DIV16_EN 188 |
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| 200 | #define CLKID_CPU_CLK_DIV16 189 |
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| 201 | #define CLKID_CPU_CLK_APB_DIV 190 |
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| 202 | #define CLKID_CPU_CLK_APB 191 |
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| 203 | #define CLKID_CPU_CLK_ATB_DIV 192 |
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| 204 | #define CLKID_CPU_CLK_ATB 193 |
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| 205 | #define CLKID_CPU_CLK_AXI_DIV 194 |
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| 206 | #define CLKID_CPU_CLK_AXI 195 |
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| 207 | #define CLKID_CPU_CLK_TRACE_DIV 196 |
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| 208 | #define CLKID_CPU_CLK_TRACE 197 |
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| 209 | #define CLKID_PCIE_PLL_DCO 198 |
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| 210 | #define CLKID_PCIE_PLL_DCO_DIV2 199 |
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| 211 | #define CLKID_PCIE_PLL_OD 200 |
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| 212 | #define CLKID_PCIE_PLL 201 |
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| 213 | #define CLKID_VDEC_1_SEL 202 |
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| 214 | #define CLKID_VDEC_1_DIV 203 |
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| 215 | #define CLKID_VDEC_1 204 |
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| 216 | #define CLKID_VDEC_HEVC_SEL 205 |
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| 217 | #define CLKID_VDEC_HEVC_DIV 206 |
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| 218 | #define CLKID_VDEC_HEVC 207 |
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| 219 | #define CLKID_VDEC_HEVCF_SEL 208 |
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| 220 | #define CLKID_VDEC_HEVCF_DIV 209 |
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| 221 | #define CLKID_VDEC_HEVCF 210 |
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| 222 | #define CLKID_TS_DIV 211 |
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| 223 | #define CLKID_TS 212 |
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| 224 | #define CLKID_SYS1_PLL_DCO 213 |
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| 225 | #define CLKID_SYS1_PLL 214 |
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| 226 | #define CLKID_SYS1_PLL_DIV16_EN 215 |
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| 227 | #define CLKID_SYS1_PLL_DIV16 216 |
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| 228 | #define CLKID_CPUB_CLK_DYN0_SEL 217 |
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| 229 | #define CLKID_CPUB_CLK_DYN0_DIV 218 |
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| 230 | #define CLKID_CPUB_CLK_DYN0 219 |
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| 231 | #define CLKID_CPUB_CLK_DYN1_SEL 220 |
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| 232 | #define CLKID_CPUB_CLK_DYN1_DIV 221 |
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| 233 | #define CLKID_CPUB_CLK_DYN1 222 |
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| 234 | #define CLKID_CPUB_CLK_DYN 223 |
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| 235 | #define CLKID_CPUB_CLK 224 |
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| 236 | #define CLKID_CPUB_CLK_DIV16_EN 225 |
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| 237 | #define CLKID_CPUB_CLK_DIV16 226 |
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| 238 | #define CLKID_CPUB_CLK_DIV2 227 |
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| 239 | #define CLKID_CPUB_CLK_DIV3 228 |
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| 240 | #define CLKID_CPUB_CLK_DIV4 229 |
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| 241 | #define CLKID_CPUB_CLK_DIV5 230 |
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| 242 | #define CLKID_CPUB_CLK_DIV6 231 |
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| 243 | #define CLKID_CPUB_CLK_DIV7 232 |
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| 244 | #define CLKID_CPUB_CLK_DIV8 233 |
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| 245 | #define CLKID_CPUB_CLK_APB_SEL 234 |
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| 246 | #define CLKID_CPUB_CLK_APB 235 |
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| 247 | #define CLKID_CPUB_CLK_ATB_SEL 236 |
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| 248 | #define CLKID_CPUB_CLK_ATB 237 |
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| 249 | #define CLKID_CPUB_CLK_AXI_SEL 238 |
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| 250 | #define CLKID_CPUB_CLK_AXI 239 |
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| 251 | #define CLKID_CPUB_CLK_TRACE_SEL 240 |
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| 252 | #define CLKID_CPUB_CLK_TRACE 241 |
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| 253 | #define CLKID_GP1_PLL_DCO 242 |
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| 254 | #define CLKID_GP1_PLL 243 |
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| 255 | #define CLKID_DSU_CLK_DYN0_SEL 244 |
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| 256 | #define CLKID_DSU_CLK_DYN0_DIV 245 |
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| 257 | #define CLKID_DSU_CLK_DYN0 246 |
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| 258 | #define CLKID_DSU_CLK_DYN1_SEL 247 |
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| 259 | #define CLKID_DSU_CLK_DYN1_DIV 248 |
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| 260 | #define CLKID_DSU_CLK_DYN1 249 |
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| 261 | #define CLKID_DSU_CLK_DYN 250 |
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| 262 | #define CLKID_DSU_CLK_FINAL 251 |
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| 263 | #define CLKID_DSU_CLK 252 |
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| 264 | #define CLKID_CPU1_CLK 253 |
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| 265 | #define CLKID_CPU2_CLK 254 |
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| 266 | #define CLKID_CPU3_CLK 255 |
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| 267 | #define CLKID_SPICC0_SCLK_SEL 256 |
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| 268 | #define CLKID_SPICC0_SCLK_DIV 257 |
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| 269 | #define CLKID_SPICC0_SCLK 258 |
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| 270 | #define CLKID_SPICC1_SCLK_SEL 259 |
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| 271 | #define CLKID_SPICC1_SCLK_DIV 260 |
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| 272 | #define CLKID_SPICC1_SCLK 261 |
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| 273 | #define CLKID_NNA_AXI_CLK_SEL 262 |
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| 274 | #define CLKID_NNA_AXI_CLK_DIV 263 |
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| 275 | #define CLKID_NNA_AXI_CLK 264 |
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| 276 | #define CLKID_NNA_CORE_CLK_SEL 265 |
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| 277 | #define CLKID_NNA_CORE_CLK_DIV 266 |
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| 278 | #define CLKID_NNA_CORE_CLK 267 |
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| 279 | #define CLKID_MIPI_DSI_PXCLK_DIV 268 |
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| 280 | #define CLKID_MIPI_DSI_PXCLK_SEL 269 |
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| 281 | #define CLKID_MIPI_DSI_PXCLK 270 |
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| 282 | #define CLKID_CTS_ENCL 271 |
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| 283 | #define CLKID_CTS_ENCL_SEL 272 |
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| 284 | #define CLKID_MIPI_ISP_DIV 273 |
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| 285 | #define CLKID_MIPI_ISP_SEL 274 |
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| 286 | #define CLKID_MIPI_ISP 275 |
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| 287 | #define CLKID_MIPI_ISP_GATE 276 |
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| 288 | #define CLKID_MIPI_ISP_CSI_PHY0 277 |
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| 289 | #define CLKID_MIPI_ISP_CSI_PHY1 278 |
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| 290 | |
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| 291 | #endif /* __G12A_CLKC_H */ |
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| 292 | |
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