1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. |
4 | */ |
5 | |
6 | #ifndef __DTS_HI3516CV300_CLOCK_H |
7 | #define __DTS_HI3516CV300_CLOCK_H |
8 | |
9 | /* hi3516CV300 core CRG */ |
10 | #define HI3516CV300_APB_CLK 0 |
11 | #define HI3516CV300_UART0_CLK 1 |
12 | #define HI3516CV300_UART1_CLK 2 |
13 | #define HI3516CV300_UART2_CLK 3 |
14 | #define HI3516CV300_SPI0_CLK 4 |
15 | #define HI3516CV300_SPI1_CLK 5 |
16 | #define HI3516CV300_FMC_CLK 6 |
17 | #define HI3516CV300_MMC0_CLK 7 |
18 | #define HI3516CV300_MMC1_CLK 8 |
19 | #define HI3516CV300_MMC2_CLK 9 |
20 | #define HI3516CV300_MMC3_CLK 10 |
21 | #define HI3516CV300_ETH_CLK 11 |
22 | #define HI3516CV300_ETH_MACIF_CLK 12 |
23 | #define HI3516CV300_DMAC_CLK 13 |
24 | #define HI3516CV300_PWM_CLK 14 |
25 | #define HI3516CV300_USB2_BUS_CLK 15 |
26 | #define HI3516CV300_USB2_OHCI48M_CLK 16 |
27 | #define HI3516CV300_USB2_OHCI12M_CLK 17 |
28 | #define HI3516CV300_USB2_OTG_UTMI_CLK 18 |
29 | #define HI3516CV300_USB2_HST_PHY_CLK 19 |
30 | #define HI3516CV300_USB2_UTMI0_CLK 20 |
31 | #define HI3516CV300_USB2_PHY_CLK 21 |
32 | |
33 | /* hi3516CV300 sysctrl CRG */ |
34 | #define HI3516CV300_WDT_CLK 1 |
35 | |
36 | #endif /* __DTS_HI3516CV300_CLOCK_H */ |
37 | |