| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright 2017-2018 NXP |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __DT_BINDINGS_CLOCK_IMX8MM_H |
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| 7 | #define __DT_BINDINGS_CLOCK_IMX8MM_H |
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| 8 | |
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| 9 | #define IMX8MM_CLK_DUMMY 0 |
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| 10 | #define IMX8MM_CLK_32K 1 |
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| 11 | #define IMX8MM_CLK_24M 2 |
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| 12 | #define IMX8MM_OSC_HDMI_CLK 3 |
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| 13 | #define IMX8MM_CLK_EXT1 4 |
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| 14 | #define IMX8MM_CLK_EXT2 5 |
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| 15 | #define IMX8MM_CLK_EXT3 6 |
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| 16 | #define IMX8MM_CLK_EXT4 7 |
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| 17 | #define IMX8MM_AUDIO_PLL1_REF_SEL 8 |
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| 18 | #define IMX8MM_AUDIO_PLL2_REF_SEL 9 |
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| 19 | #define IMX8MM_VIDEO_PLL1_REF_SEL 10 |
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| 20 | #define IMX8MM_DRAM_PLL_REF_SEL 11 |
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| 21 | #define IMX8MM_GPU_PLL_REF_SEL 12 |
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| 22 | #define IMX8MM_VPU_PLL_REF_SEL 13 |
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| 23 | #define IMX8MM_ARM_PLL_REF_SEL 14 |
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| 24 | #define IMX8MM_SYS_PLL1_REF_SEL 15 |
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| 25 | #define IMX8MM_SYS_PLL2_REF_SEL 16 |
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| 26 | #define IMX8MM_SYS_PLL3_REF_SEL 17 |
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| 27 | #define IMX8MM_AUDIO_PLL1 18 |
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| 28 | #define IMX8MM_AUDIO_PLL2 19 |
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| 29 | #define IMX8MM_VIDEO_PLL1 20 |
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| 30 | #define IMX8MM_DRAM_PLL 21 |
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| 31 | #define IMX8MM_GPU_PLL 22 |
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| 32 | #define IMX8MM_VPU_PLL 23 |
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| 33 | #define IMX8MM_ARM_PLL 24 |
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| 34 | #define IMX8MM_SYS_PLL1 25 |
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| 35 | #define IMX8MM_SYS_PLL2 26 |
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| 36 | #define IMX8MM_SYS_PLL3 27 |
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| 37 | #define IMX8MM_AUDIO_PLL1_BYPASS 28 |
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| 38 | #define IMX8MM_AUDIO_PLL2_BYPASS 29 |
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| 39 | #define IMX8MM_VIDEO_PLL1_BYPASS 30 |
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| 40 | #define IMX8MM_DRAM_PLL_BYPASS 31 |
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| 41 | #define IMX8MM_GPU_PLL_BYPASS 32 |
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| 42 | #define IMX8MM_VPU_PLL_BYPASS 33 |
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| 43 | #define IMX8MM_ARM_PLL_BYPASS 34 |
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| 44 | #define IMX8MM_SYS_PLL1_BYPASS 35 |
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| 45 | #define IMX8MM_SYS_PLL2_BYPASS 36 |
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| 46 | #define IMX8MM_SYS_PLL3_BYPASS 37 |
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| 47 | #define IMX8MM_AUDIO_PLL1_OUT 38 |
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| 48 | #define IMX8MM_AUDIO_PLL2_OUT 39 |
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| 49 | #define IMX8MM_VIDEO_PLL1_OUT 40 |
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| 50 | #define IMX8MM_DRAM_PLL_OUT 41 |
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| 51 | #define IMX8MM_GPU_PLL_OUT 42 |
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| 52 | #define IMX8MM_VPU_PLL_OUT 43 |
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| 53 | #define IMX8MM_ARM_PLL_OUT 44 |
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| 54 | #define IMX8MM_SYS_PLL1_OUT 45 |
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| 55 | #define IMX8MM_SYS_PLL2_OUT 46 |
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| 56 | #define IMX8MM_SYS_PLL3_OUT 47 |
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| 57 | #define IMX8MM_SYS_PLL1_40M 48 |
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| 58 | #define IMX8MM_SYS_PLL1_80M 49 |
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| 59 | #define IMX8MM_SYS_PLL1_100M 50 |
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| 60 | #define IMX8MM_SYS_PLL1_133M 51 |
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| 61 | #define IMX8MM_SYS_PLL1_160M 52 |
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| 62 | #define IMX8MM_SYS_PLL1_200M 53 |
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| 63 | #define IMX8MM_SYS_PLL1_266M 54 |
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| 64 | #define IMX8MM_SYS_PLL1_400M 55 |
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| 65 | #define IMX8MM_SYS_PLL1_800M 56 |
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| 66 | #define IMX8MM_SYS_PLL2_50M 57 |
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| 67 | #define IMX8MM_SYS_PLL2_100M 58 |
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| 68 | #define IMX8MM_SYS_PLL2_125M 59 |
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| 69 | #define IMX8MM_SYS_PLL2_166M 60 |
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| 70 | #define IMX8MM_SYS_PLL2_200M 61 |
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| 71 | #define IMX8MM_SYS_PLL2_250M 62 |
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| 72 | #define IMX8MM_SYS_PLL2_333M 63 |
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| 73 | #define IMX8MM_SYS_PLL2_500M 64 |
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| 74 | #define IMX8MM_SYS_PLL2_1000M 65 |
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| 75 | |
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| 76 | /* core */ |
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| 77 | #define IMX8MM_CLK_A53_SRC 66 |
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| 78 | #define IMX8MM_CLK_M4_SRC 67 |
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| 79 | #define IMX8MM_CLK_VPU_SRC 68 |
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| 80 | #define IMX8MM_CLK_GPU3D_SRC 69 |
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| 81 | #define IMX8MM_CLK_GPU2D_SRC 70 |
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| 82 | #define IMX8MM_CLK_A53_CG 71 |
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| 83 | #define IMX8MM_CLK_M4_CG 72 |
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| 84 | #define IMX8MM_CLK_VPU_CG 73 |
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| 85 | #define IMX8MM_CLK_GPU3D_CG 74 |
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| 86 | #define IMX8MM_CLK_GPU2D_CG 75 |
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| 87 | #define IMX8MM_CLK_A53_DIV 76 |
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| 88 | #define IMX8MM_CLK_M4_DIV 77 |
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| 89 | #define IMX8MM_CLK_VPU_DIV 78 |
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| 90 | #define IMX8MM_CLK_GPU3D_DIV 79 |
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| 91 | #define IMX8MM_CLK_GPU2D_DIV 80 |
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| 92 | |
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| 93 | /* bus */ |
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| 94 | #define IMX8MM_CLK_MAIN_AXI 81 |
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| 95 | #define IMX8MM_CLK_ENET_AXI 82 |
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| 96 | #define IMX8MM_CLK_NAND_USDHC_BUS 83 |
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| 97 | #define IMX8MM_CLK_VPU_BUS 84 |
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| 98 | #define IMX8MM_CLK_DISP_AXI 85 |
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| 99 | #define IMX8MM_CLK_DISP_APB 86 |
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| 100 | #define IMX8MM_CLK_DISP_RTRM 87 |
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| 101 | #define IMX8MM_CLK_USB_BUS 88 |
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| 102 | #define IMX8MM_CLK_GPU_AXI 89 |
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| 103 | #define IMX8MM_CLK_GPU_AHB 90 |
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| 104 | #define IMX8MM_CLK_NOC 91 |
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| 105 | #define IMX8MM_CLK_NOC_APB 92 |
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| 106 | |
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| 107 | #define IMX8MM_CLK_AHB 93 |
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| 108 | #define IMX8MM_CLK_AUDIO_AHB 94 |
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| 109 | #define IMX8MM_CLK_IPG_ROOT 95 |
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| 110 | #define IMX8MM_CLK_IPG_AUDIO_ROOT 96 |
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| 111 | |
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| 112 | #define IMX8MM_CLK_DRAM_ALT 97 |
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| 113 | #define IMX8MM_CLK_DRAM_APB 98 |
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| 114 | #define IMX8MM_CLK_VPU_G1 99 |
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| 115 | #define IMX8MM_CLK_VPU_G2 100 |
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| 116 | #define IMX8MM_CLK_DISP_DTRC 101 |
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| 117 | #define IMX8MM_CLK_DISP_DC8000 102 |
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| 118 | #define IMX8MM_CLK_PCIE1_CTRL 103 |
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| 119 | #define IMX8MM_CLK_PCIE1_PHY 104 |
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| 120 | #define IMX8MM_CLK_PCIE1_AUX 105 |
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| 121 | #define IMX8MM_CLK_DC_PIXEL 106 |
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| 122 | #define IMX8MM_CLK_LCDIF_PIXEL 107 |
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| 123 | #define IMX8MM_CLK_SAI1 108 |
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| 124 | #define IMX8MM_CLK_SAI2 109 |
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| 125 | #define IMX8MM_CLK_SAI3 110 |
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| 126 | #define IMX8MM_CLK_SAI4 111 |
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| 127 | #define IMX8MM_CLK_SAI5 112 |
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| 128 | #define IMX8MM_CLK_SAI6 113 |
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| 129 | #define IMX8MM_CLK_SPDIF1 114 |
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| 130 | #define IMX8MM_CLK_SPDIF2 115 |
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| 131 | #define IMX8MM_CLK_ENET_REF 116 |
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| 132 | #define IMX8MM_CLK_ENET_TIMER 117 |
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| 133 | #define IMX8MM_CLK_ENET_PHY_REF 118 |
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| 134 | #define IMX8MM_CLK_NAND 119 |
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| 135 | #define IMX8MM_CLK_QSPI 120 |
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| 136 | #define IMX8MM_CLK_USDHC1 121 |
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| 137 | #define IMX8MM_CLK_USDHC2 122 |
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| 138 | #define IMX8MM_CLK_I2C1 123 |
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| 139 | #define IMX8MM_CLK_I2C2 124 |
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| 140 | #define IMX8MM_CLK_I2C3 125 |
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| 141 | #define IMX8MM_CLK_I2C4 126 |
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| 142 | #define IMX8MM_CLK_UART1 127 |
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| 143 | #define IMX8MM_CLK_UART2 128 |
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| 144 | #define IMX8MM_CLK_UART3 129 |
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| 145 | #define IMX8MM_CLK_UART4 130 |
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| 146 | #define IMX8MM_CLK_USB_CORE_REF 131 |
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| 147 | #define IMX8MM_CLK_USB_PHY_REF 132 |
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| 148 | #define IMX8MM_CLK_ECSPI1 133 |
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| 149 | #define IMX8MM_CLK_ECSPI2 134 |
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| 150 | #define IMX8MM_CLK_PWM1 135 |
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| 151 | #define IMX8MM_CLK_PWM2 136 |
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| 152 | #define IMX8MM_CLK_PWM3 137 |
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| 153 | #define IMX8MM_CLK_PWM4 138 |
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| 154 | #define IMX8MM_CLK_GPT1 139 |
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| 155 | #define IMX8MM_CLK_WDOG 140 |
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| 156 | #define IMX8MM_CLK_WRCLK 141 |
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| 157 | #define IMX8MM_CLK_DSI_CORE 142 |
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| 158 | #define IMX8MM_CLK_DSI_PHY_REF 143 |
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| 159 | #define IMX8MM_CLK_DSI_DBI 144 |
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| 160 | #define IMX8MM_CLK_USDHC3 145 |
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| 161 | #define IMX8MM_CLK_CSI1_CORE 146 |
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| 162 | #define IMX8MM_CLK_CSI1_PHY_REF 147 |
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| 163 | #define IMX8MM_CLK_CSI1_ESC 148 |
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| 164 | #define IMX8MM_CLK_CSI2_CORE 149 |
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| 165 | #define IMX8MM_CLK_CSI2_PHY_REF 150 |
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| 166 | #define IMX8MM_CLK_CSI2_ESC 151 |
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| 167 | #define IMX8MM_CLK_PCIE2_CTRL 152 |
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| 168 | #define IMX8MM_CLK_PCIE2_PHY 153 |
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| 169 | #define IMX8MM_CLK_PCIE2_AUX 154 |
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| 170 | #define IMX8MM_CLK_ECSPI3 155 |
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| 171 | #define IMX8MM_CLK_PDM 156 |
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| 172 | #define IMX8MM_CLK_VPU_H1 157 |
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| 173 | #define IMX8MM_CLK_CLKO1 158 |
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| 174 | |
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| 175 | #define IMX8MM_CLK_ECSPI1_ROOT 159 |
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| 176 | #define IMX8MM_CLK_ECSPI2_ROOT 160 |
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| 177 | #define IMX8MM_CLK_ECSPI3_ROOT 161 |
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| 178 | #define IMX8MM_CLK_ENET1_ROOT 162 |
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| 179 | #define IMX8MM_CLK_GPT1_ROOT 163 |
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| 180 | #define IMX8MM_CLK_I2C1_ROOT 164 |
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| 181 | #define IMX8MM_CLK_I2C2_ROOT 165 |
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| 182 | #define IMX8MM_CLK_I2C3_ROOT 166 |
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| 183 | #define IMX8MM_CLK_I2C4_ROOT 167 |
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| 184 | #define IMX8MM_CLK_OCOTP_ROOT 168 |
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| 185 | #define IMX8MM_CLK_PCIE1_ROOT 169 |
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| 186 | #define IMX8MM_CLK_PWM1_ROOT 170 |
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| 187 | #define IMX8MM_CLK_PWM2_ROOT 171 |
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| 188 | #define IMX8MM_CLK_PWM3_ROOT 172 |
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| 189 | #define IMX8MM_CLK_PWM4_ROOT 173 |
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| 190 | #define IMX8MM_CLK_QSPI_ROOT 174 |
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| 191 | #define IMX8MM_CLK_NAND_ROOT 175 |
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| 192 | #define IMX8MM_CLK_SAI1_ROOT 176 |
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| 193 | #define IMX8MM_CLK_SAI1_IPG 177 |
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| 194 | #define IMX8MM_CLK_SAI2_ROOT 178 |
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| 195 | #define IMX8MM_CLK_SAI2_IPG 179 |
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| 196 | #define IMX8MM_CLK_SAI3_ROOT 180 |
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| 197 | #define IMX8MM_CLK_SAI3_IPG 181 |
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| 198 | #define IMX8MM_CLK_SAI4_ROOT 182 |
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| 199 | #define IMX8MM_CLK_SAI4_IPG 183 |
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| 200 | #define IMX8MM_CLK_SAI5_ROOT 184 |
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| 201 | #define IMX8MM_CLK_SAI5_IPG 185 |
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| 202 | #define IMX8MM_CLK_SAI6_ROOT 186 |
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| 203 | #define IMX8MM_CLK_SAI6_IPG 187 |
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| 204 | #define IMX8MM_CLK_UART1_ROOT 188 |
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| 205 | #define IMX8MM_CLK_UART2_ROOT 189 |
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| 206 | #define IMX8MM_CLK_UART3_ROOT 190 |
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| 207 | #define IMX8MM_CLK_UART4_ROOT 191 |
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| 208 | #define IMX8MM_CLK_USB1_CTRL_ROOT 192 |
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| 209 | #define IMX8MM_CLK_GPU3D_ROOT 193 |
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| 210 | #define IMX8MM_CLK_USDHC1_ROOT 194 |
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| 211 | #define IMX8MM_CLK_USDHC2_ROOT 195 |
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| 212 | #define IMX8MM_CLK_WDOG1_ROOT 196 |
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| 213 | #define IMX8MM_CLK_WDOG2_ROOT 197 |
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| 214 | #define IMX8MM_CLK_WDOG3_ROOT 198 |
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| 215 | #define IMX8MM_CLK_VPU_G1_ROOT 199 |
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| 216 | #define IMX8MM_CLK_GPU_BUS_ROOT 200 |
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| 217 | #define IMX8MM_CLK_VPU_H1_ROOT 201 |
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| 218 | #define IMX8MM_CLK_VPU_G2_ROOT 202 |
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| 219 | #define IMX8MM_CLK_PDM_ROOT 203 |
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| 220 | #define IMX8MM_CLK_DISP_ROOT 204 |
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| 221 | #define IMX8MM_CLK_DISP_AXI_ROOT 205 |
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| 222 | #define IMX8MM_CLK_DISP_APB_ROOT 206 |
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| 223 | #define IMX8MM_CLK_DISP_RTRM_ROOT 207 |
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| 224 | #define IMX8MM_CLK_USDHC3_ROOT 208 |
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| 225 | #define IMX8MM_CLK_TMU_ROOT 209 |
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| 226 | #define IMX8MM_CLK_VPU_DEC_ROOT 210 |
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| 227 | #define IMX8MM_CLK_SDMA1_ROOT 211 |
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| 228 | #define IMX8MM_CLK_SDMA2_ROOT 212 |
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| 229 | #define IMX8MM_CLK_SDMA3_ROOT 213 |
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| 230 | #define IMX8MM_CLK_GPT_3M 214 |
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| 231 | #define IMX8MM_CLK_ARM 215 |
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| 232 | #define IMX8MM_CLK_PDM_IPG 216 |
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| 233 | #define IMX8MM_CLK_GPU2D_ROOT 217 |
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| 234 | #define IMX8MM_CLK_MU_ROOT 218 |
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| 235 | #define IMX8MM_CLK_CSI1_ROOT 219 |
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| 236 | |
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| 237 | #define IMX8MM_CLK_DRAM_CORE 220 |
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| 238 | #define IMX8MM_CLK_DRAM_ALT_ROOT 221 |
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| 239 | |
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| 240 | #define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222 |
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| 241 | |
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| 242 | #define IMX8MM_CLK_GPIO1_ROOT 223 |
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| 243 | #define IMX8MM_CLK_GPIO2_ROOT 224 |
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| 244 | #define IMX8MM_CLK_GPIO3_ROOT 225 |
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| 245 | #define IMX8MM_CLK_GPIO4_ROOT 226 |
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| 246 | #define IMX8MM_CLK_GPIO5_ROOT 227 |
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| 247 | |
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| 248 | #define IMX8MM_CLK_SNVS_ROOT 228 |
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| 249 | #define IMX8MM_CLK_GIC 229 |
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| 250 | |
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| 251 | #define IMX8MM_SYS_PLL1_40M_CG 230 |
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| 252 | #define IMX8MM_SYS_PLL1_80M_CG 231 |
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| 253 | #define IMX8MM_SYS_PLL1_100M_CG 232 |
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| 254 | #define IMX8MM_SYS_PLL1_133M_CG 233 |
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| 255 | #define IMX8MM_SYS_PLL1_160M_CG 234 |
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| 256 | #define IMX8MM_SYS_PLL1_200M_CG 235 |
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| 257 | #define IMX8MM_SYS_PLL1_266M_CG 236 |
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| 258 | #define IMX8MM_SYS_PLL1_400M_CG 237 |
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| 259 | #define IMX8MM_SYS_PLL2_50M_CG 238 |
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| 260 | #define IMX8MM_SYS_PLL2_100M_CG 239 |
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| 261 | #define IMX8MM_SYS_PLL2_125M_CG 240 |
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| 262 | #define IMX8MM_SYS_PLL2_166M_CG 241 |
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| 263 | #define IMX8MM_SYS_PLL2_200M_CG 242 |
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| 264 | #define IMX8MM_SYS_PLL2_250M_CG 243 |
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| 265 | #define IMX8MM_SYS_PLL2_333M_CG 244 |
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| 266 | #define IMX8MM_SYS_PLL2_500M_CG 245 |
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| 267 | |
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| 268 | #define IMX8MM_CLK_M4_CORE 246 |
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| 269 | #define IMX8MM_CLK_VPU_CORE 247 |
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| 270 | #define IMX8MM_CLK_GPU3D_CORE 248 |
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| 271 | #define IMX8MM_CLK_GPU2D_CORE 249 |
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| 272 | |
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| 273 | #define IMX8MM_CLK_CLKO2 250 |
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| 274 | |
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| 275 | #define IMX8MM_CLK_A53_CORE 251 |
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| 276 | |
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| 277 | #define IMX8MM_CLK_CLKOUT1_SEL 252 |
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| 278 | #define IMX8MM_CLK_CLKOUT1_DIV 253 |
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| 279 | #define IMX8MM_CLK_CLKOUT1 254 |
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| 280 | #define IMX8MM_CLK_CLKOUT2_SEL 255 |
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| 281 | #define IMX8MM_CLK_CLKOUT2_DIV 256 |
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| 282 | #define IMX8MM_CLK_CLKOUT2 257 |
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| 283 | |
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| 284 | #define IMX8MM_CLK_END 258 |
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| 285 | |
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| 286 | #endif |
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| 287 | |
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