| 1 | /* SPDX-License-Identifier: GPL-2.0+ OR MIT */ |
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| 2 | /* |
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| 3 | * Copyright 2021 NXP |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H |
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| 7 | #define __DT_BINDINGS_CLOCK_IMX8ULP_H |
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| 8 | |
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| 9 | #define IMX8ULP_CLK_DUMMY 0 |
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| 10 | |
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| 11 | /* CGC1 */ |
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| 12 | #define IMX8ULP_CLK_SPLL2 5 |
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| 13 | #define IMX8ULP_CLK_SPLL3 6 |
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| 14 | #define IMX8ULP_CLK_A35_SEL 7 |
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| 15 | #define IMX8ULP_CLK_A35_DIV 8 |
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| 16 | #define IMX8ULP_CLK_SPLL2_PRE_SEL 9 |
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| 17 | #define IMX8ULP_CLK_SPLL3_PRE_SEL 10 |
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| 18 | #define IMX8ULP_CLK_SPLL3_PFD0 11 |
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| 19 | #define IMX8ULP_CLK_SPLL3_PFD1 12 |
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| 20 | #define IMX8ULP_CLK_SPLL3_PFD2 13 |
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| 21 | #define IMX8ULP_CLK_SPLL3_PFD3 14 |
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| 22 | #define IMX8ULP_CLK_SPLL3_PFD0_DIV1 15 |
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| 23 | #define IMX8ULP_CLK_SPLL3_PFD0_DIV2 16 |
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| 24 | #define IMX8ULP_CLK_SPLL3_PFD1_DIV1 17 |
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| 25 | #define IMX8ULP_CLK_SPLL3_PFD1_DIV2 18 |
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| 26 | #define IMX8ULP_CLK_SPLL3_PFD2_DIV1 19 |
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| 27 | #define IMX8ULP_CLK_SPLL3_PFD2_DIV2 20 |
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| 28 | #define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21 |
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| 29 | #define IMX8ULP_CLK_SPLL3_PFD3_DIV2 22 |
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| 30 | #define IMX8ULP_CLK_NIC_SEL 23 |
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| 31 | #define IMX8ULP_CLK_NIC_AD_DIVPLAT 24 |
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| 32 | #define IMX8ULP_CLK_NIC_PER_DIVPLAT 25 |
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| 33 | #define IMX8ULP_CLK_XBAR_SEL 26 |
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| 34 | #define IMX8ULP_CLK_XBAR_AD_DIVPLAT 27 |
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| 35 | #define IMX8ULP_CLK_XBAR_DIVBUS 28 |
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| 36 | #define IMX8ULP_CLK_XBAR_AD_SLOW 29 |
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| 37 | #define IMX8ULP_CLK_SOSC_DIV1 30 |
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| 38 | #define IMX8ULP_CLK_SOSC_DIV2 31 |
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| 39 | #define IMX8ULP_CLK_SOSC_DIV3 32 |
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| 40 | #define IMX8ULP_CLK_FROSC_DIV1 33 |
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| 41 | #define IMX8ULP_CLK_FROSC_DIV2 34 |
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| 42 | #define IMX8ULP_CLK_FROSC_DIV3 35 |
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| 43 | #define IMX8ULP_CLK_SPLL3_VCODIV 36 |
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| 44 | #define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE 37 |
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| 45 | #define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE 38 |
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| 46 | #define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE 39 |
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| 47 | #define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE 40 |
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| 48 | #define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE 41 |
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| 49 | #define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE 42 |
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| 50 | #define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE 43 |
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| 51 | #define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE 44 |
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| 52 | #define IMX8ULP_CLK_SOSC_DIV1_GATE 45 |
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| 53 | #define IMX8ULP_CLK_SOSC_DIV2_GATE 46 |
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| 54 | #define IMX8ULP_CLK_SOSC_DIV3_GATE 47 |
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| 55 | #define IMX8ULP_CLK_FROSC_DIV1_GATE 48 |
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| 56 | #define IMX8ULP_CLK_FROSC_DIV2_GATE 49 |
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| 57 | #define IMX8ULP_CLK_FROSC_DIV3_GATE 50 |
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| 58 | #define IMX8ULP_CLK_SAI4_SEL 51 |
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| 59 | #define IMX8ULP_CLK_SAI5_SEL 52 |
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| 60 | #define IMX8ULP_CLK_AUD_CLK1 53 |
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| 61 | #define IMX8ULP_CLK_ARM 54 |
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| 62 | #define IMX8ULP_CLK_ENET_TS_SEL 55 |
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| 63 | |
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| 64 | #define IMX8ULP_CLK_CGC1_END 56 |
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| 65 | |
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| 66 | /* CGC2 */ |
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| 67 | #define IMX8ULP_CLK_PLL4_PRE_SEL 0 |
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| 68 | #define IMX8ULP_CLK_PLL4 1 |
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| 69 | #define IMX8ULP_CLK_PLL4_VCODIV 2 |
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| 70 | #define IMX8ULP_CLK_DDR_SEL 3 |
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| 71 | #define IMX8ULP_CLK_DDR_DIV 4 |
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| 72 | #define IMX8ULP_CLK_LPAV_AXI_SEL 5 |
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| 73 | #define IMX8ULP_CLK_LPAV_AXI_DIV 6 |
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| 74 | #define IMX8ULP_CLK_LPAV_AHB_DIV 7 |
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| 75 | #define IMX8ULP_CLK_LPAV_BUS_DIV 8 |
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| 76 | #define IMX8ULP_CLK_PLL4_PFD0 9 |
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| 77 | #define IMX8ULP_CLK_PLL4_PFD1 10 |
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| 78 | #define IMX8ULP_CLK_PLL4_PFD2 11 |
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| 79 | #define IMX8ULP_CLK_PLL4_PFD3 12 |
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| 80 | #define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE 13 |
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| 81 | #define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE 14 |
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| 82 | #define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE 15 |
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| 83 | #define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE 16 |
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| 84 | #define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE 17 |
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| 85 | #define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE 18 |
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| 86 | #define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE 19 |
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| 87 | #define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE 20 |
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| 88 | #define IMX8ULP_CLK_PLL4_PFD0_DIV1 21 |
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| 89 | #define IMX8ULP_CLK_PLL4_PFD0_DIV2 22 |
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| 90 | #define IMX8ULP_CLK_PLL4_PFD1_DIV1 23 |
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| 91 | #define IMX8ULP_CLK_PLL4_PFD1_DIV2 24 |
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| 92 | #define IMX8ULP_CLK_PLL4_PFD2_DIV1 25 |
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| 93 | #define IMX8ULP_CLK_PLL4_PFD2_DIV2 26 |
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| 94 | #define IMX8ULP_CLK_PLL4_PFD3_DIV1 27 |
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| 95 | #define IMX8ULP_CLK_PLL4_PFD3_DIV2 28 |
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| 96 | #define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE 29 |
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| 97 | #define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE 30 |
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| 98 | #define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE 31 |
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| 99 | #define IMX8ULP_CLK_CGC2_SOSC_DIV1 32 |
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| 100 | #define IMX8ULP_CLK_CGC2_SOSC_DIV2 33 |
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| 101 | #define IMX8ULP_CLK_CGC2_SOSC_DIV3 34 |
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| 102 | #define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE 35 |
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| 103 | #define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE 36 |
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| 104 | #define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE 37 |
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| 105 | #define IMX8ULP_CLK_CGC2_FROSC_DIV1 38 |
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| 106 | #define IMX8ULP_CLK_CGC2_FROSC_DIV2 39 |
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| 107 | #define IMX8ULP_CLK_CGC2_FROSC_DIV3 40 |
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| 108 | #define IMX8ULP_CLK_AUD_CLK2 41 |
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| 109 | #define IMX8ULP_CLK_SAI6_SEL 42 |
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| 110 | #define IMX8ULP_CLK_SAI7_SEL 43 |
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| 111 | #define IMX8ULP_CLK_SPDIF_SEL 44 |
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| 112 | #define IMX8ULP_CLK_HIFI_SEL 45 |
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| 113 | #define IMX8ULP_CLK_HIFI_DIVCORE 46 |
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| 114 | #define IMX8ULP_CLK_HIFI_DIVPLAT 47 |
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| 115 | #define IMX8ULP_CLK_DSI_PHY_REF 48 |
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| 116 | |
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| 117 | #define IMX8ULP_CLK_CGC2_END 49 |
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| 118 | |
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| 119 | /* PCC3 */ |
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| 120 | #define IMX8ULP_CLK_WDOG3 0 |
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| 121 | #define IMX8ULP_CLK_WDOG4 1 |
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| 122 | #define IMX8ULP_CLK_LPIT1 2 |
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| 123 | #define IMX8ULP_CLK_TPM4 3 |
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| 124 | #define IMX8ULP_CLK_TPM5 4 |
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| 125 | #define IMX8ULP_CLK_FLEXIO1 5 |
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| 126 | #define IMX8ULP_CLK_I3C2 6 |
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| 127 | #define IMX8ULP_CLK_LPI2C4 7 |
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| 128 | #define IMX8ULP_CLK_LPI2C5 8 |
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| 129 | #define IMX8ULP_CLK_LPUART4 9 |
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| 130 | #define IMX8ULP_CLK_LPUART5 10 |
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| 131 | #define IMX8ULP_CLK_LPSPI4 11 |
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| 132 | #define IMX8ULP_CLK_LPSPI5 12 |
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| 133 | #define IMX8ULP_CLK_DMA1_MP 13 |
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| 134 | #define IMX8ULP_CLK_DMA1_CH0 14 |
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| 135 | #define IMX8ULP_CLK_DMA1_CH1 15 |
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| 136 | #define IMX8ULP_CLK_DMA1_CH2 16 |
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| 137 | #define IMX8ULP_CLK_DMA1_CH3 17 |
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| 138 | #define IMX8ULP_CLK_DMA1_CH4 18 |
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| 139 | #define IMX8ULP_CLK_DMA1_CH5 19 |
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| 140 | #define IMX8ULP_CLK_DMA1_CH6 20 |
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| 141 | #define IMX8ULP_CLK_DMA1_CH7 21 |
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| 142 | #define IMX8ULP_CLK_DMA1_CH8 22 |
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| 143 | #define IMX8ULP_CLK_DMA1_CH9 23 |
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| 144 | #define IMX8ULP_CLK_DMA1_CH10 24 |
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| 145 | #define IMX8ULP_CLK_DMA1_CH11 25 |
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| 146 | #define IMX8ULP_CLK_DMA1_CH12 26 |
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| 147 | #define IMX8ULP_CLK_DMA1_CH13 27 |
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| 148 | #define IMX8ULP_CLK_DMA1_CH14 28 |
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| 149 | #define IMX8ULP_CLK_DMA1_CH15 29 |
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| 150 | #define IMX8ULP_CLK_DMA1_CH16 30 |
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| 151 | #define IMX8ULP_CLK_DMA1_CH17 31 |
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| 152 | #define IMX8ULP_CLK_DMA1_CH18 32 |
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| 153 | #define IMX8ULP_CLK_DMA1_CH19 33 |
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| 154 | #define IMX8ULP_CLK_DMA1_CH20 34 |
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| 155 | #define IMX8ULP_CLK_DMA1_CH21 35 |
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| 156 | #define IMX8ULP_CLK_DMA1_CH22 36 |
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| 157 | #define IMX8ULP_CLK_DMA1_CH23 37 |
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| 158 | #define IMX8ULP_CLK_DMA1_CH24 38 |
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| 159 | #define IMX8ULP_CLK_DMA1_CH25 39 |
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| 160 | #define IMX8ULP_CLK_DMA1_CH26 40 |
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| 161 | #define IMX8ULP_CLK_DMA1_CH27 41 |
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| 162 | #define IMX8ULP_CLK_DMA1_CH28 42 |
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| 163 | #define IMX8ULP_CLK_DMA1_CH29 43 |
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| 164 | #define IMX8ULP_CLK_DMA1_CH30 44 |
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| 165 | #define IMX8ULP_CLK_DMA1_CH31 45 |
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| 166 | #define IMX8ULP_CLK_MU3_A 46 |
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| 167 | #define IMX8ULP_CLK_MU0_B 47 |
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| 168 | |
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| 169 | #define IMX8ULP_CLK_PCC3_END 48 |
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| 170 | |
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| 171 | /* PCC4 */ |
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| 172 | #define IMX8ULP_CLK_FLEXSPI2 0 |
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| 173 | #define IMX8ULP_CLK_TPM6 1 |
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| 174 | #define IMX8ULP_CLK_TPM7 2 |
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| 175 | #define IMX8ULP_CLK_LPI2C6 3 |
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| 176 | #define IMX8ULP_CLK_LPI2C7 4 |
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| 177 | #define IMX8ULP_CLK_LPUART6 5 |
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| 178 | #define IMX8ULP_CLK_LPUART7 6 |
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| 179 | #define IMX8ULP_CLK_SAI4 7 |
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| 180 | #define IMX8ULP_CLK_SAI5 8 |
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| 181 | #define IMX8ULP_CLK_PCTLE 9 |
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| 182 | #define IMX8ULP_CLK_PCTLF 10 |
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| 183 | #define IMX8ULP_CLK_USDHC0 11 |
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| 184 | #define IMX8ULP_CLK_USDHC1 12 |
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| 185 | #define IMX8ULP_CLK_USDHC2 13 |
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| 186 | #define IMX8ULP_CLK_USB0 14 |
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| 187 | #define IMX8ULP_CLK_USB0_PHY 15 |
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| 188 | #define IMX8ULP_CLK_USB1 16 |
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| 189 | #define IMX8ULP_CLK_USB1_PHY 17 |
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| 190 | #define IMX8ULP_CLK_USB_XBAR 18 |
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| 191 | #define IMX8ULP_CLK_ENET 19 |
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| 192 | #define IMX8ULP_CLK_SFA1 20 |
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| 193 | #define IMX8ULP_CLK_RGPIOE 21 |
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| 194 | #define IMX8ULP_CLK_RGPIOF 22 |
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| 195 | |
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| 196 | #define IMX8ULP_CLK_PCC4_END 23 |
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| 197 | |
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| 198 | /* PCC5 */ |
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| 199 | #define IMX8ULP_CLK_TPM8 0 |
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| 200 | #define IMX8ULP_CLK_SAI6 1 |
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| 201 | #define IMX8ULP_CLK_SAI7 2 |
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| 202 | #define IMX8ULP_CLK_SPDIF 3 |
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| 203 | #define IMX8ULP_CLK_ISI 4 |
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| 204 | #define IMX8ULP_CLK_CSI_REGS 5 |
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| 205 | #define IMX8ULP_CLK_PCTLD 6 |
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| 206 | #define IMX8ULP_CLK_CSI 7 |
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| 207 | #define IMX8ULP_CLK_DSI 8 |
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| 208 | #define IMX8ULP_CLK_WDOG5 9 |
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| 209 | #define IMX8ULP_CLK_EPDC 10 |
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| 210 | #define IMX8ULP_CLK_PXP 11 |
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| 211 | #define IMX8ULP_CLK_SFA2 12 |
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| 212 | #define IMX8ULP_CLK_GPU2D 13 |
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| 213 | #define IMX8ULP_CLK_GPU3D 14 |
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| 214 | #define IMX8ULP_CLK_DC_NANO 15 |
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| 215 | #define IMX8ULP_CLK_CSI_CLK_UI 16 |
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| 216 | #define IMX8ULP_CLK_CSI_CLK_ESC 17 |
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| 217 | #define IMX8ULP_CLK_RGPIOD 18 |
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| 218 | #define IMX8ULP_CLK_DMA2_MP 19 |
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| 219 | #define IMX8ULP_CLK_DMA2_CH0 20 |
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| 220 | #define IMX8ULP_CLK_DMA2_CH1 21 |
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| 221 | #define IMX8ULP_CLK_DMA2_CH2 22 |
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| 222 | #define IMX8ULP_CLK_DMA2_CH3 23 |
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| 223 | #define IMX8ULP_CLK_DMA2_CH4 24 |
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| 224 | #define IMX8ULP_CLK_DMA2_CH5 25 |
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| 225 | #define IMX8ULP_CLK_DMA2_CH6 26 |
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| 226 | #define IMX8ULP_CLK_DMA2_CH7 27 |
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| 227 | #define IMX8ULP_CLK_DMA2_CH8 28 |
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| 228 | #define IMX8ULP_CLK_DMA2_CH9 29 |
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| 229 | #define IMX8ULP_CLK_DMA2_CH10 30 |
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| 230 | #define IMX8ULP_CLK_DMA2_CH11 31 |
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| 231 | #define IMX8ULP_CLK_DMA2_CH12 32 |
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| 232 | #define IMX8ULP_CLK_DMA2_CH13 33 |
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| 233 | #define IMX8ULP_CLK_DMA2_CH14 34 |
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| 234 | #define IMX8ULP_CLK_DMA2_CH15 35 |
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| 235 | #define IMX8ULP_CLK_DMA2_CH16 36 |
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| 236 | #define IMX8ULP_CLK_DMA2_CH17 37 |
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| 237 | #define IMX8ULP_CLK_DMA2_CH18 38 |
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| 238 | #define IMX8ULP_CLK_DMA2_CH19 39 |
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| 239 | #define IMX8ULP_CLK_DMA2_CH20 40 |
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| 240 | #define IMX8ULP_CLK_DMA2_CH21 41 |
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| 241 | #define IMX8ULP_CLK_DMA2_CH22 42 |
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| 242 | #define IMX8ULP_CLK_DMA2_CH23 43 |
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| 243 | #define IMX8ULP_CLK_DMA2_CH24 44 |
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| 244 | #define IMX8ULP_CLK_DMA2_CH25 45 |
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| 245 | #define IMX8ULP_CLK_DMA2_CH26 46 |
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| 246 | #define IMX8ULP_CLK_DMA2_CH27 47 |
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| 247 | #define IMX8ULP_CLK_DMA2_CH28 48 |
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| 248 | #define IMX8ULP_CLK_DMA2_CH29 49 |
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| 249 | #define IMX8ULP_CLK_DMA2_CH30 50 |
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| 250 | #define IMX8ULP_CLK_DMA2_CH31 51 |
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| 251 | #define IMX8ULP_CLK_MU2_B 52 |
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| 252 | #define IMX8ULP_CLK_MU3_B 53 |
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| 253 | #define IMX8ULP_CLK_AVD_SIM 54 |
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| 254 | #define IMX8ULP_CLK_DSI_TX_ESC 55 |
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| 255 | |
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| 256 | #define IMX8ULP_CLK_PCC5_END 56 |
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| 257 | |
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| 258 | #endif |
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| 259 | |
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