| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * This header provides clock numbers for the ingenic,jz4740-cgu DT binding. |
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| 4 | * |
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| 5 | * They are roughly ordered as: |
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| 6 | * - external clocks |
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| 7 | * - PLLs |
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| 8 | * - muxes/dividers in the order they appear in the jz4740 programmers manual |
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| 9 | * - gates in order of their bit in the CLKGR* registers |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ |
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| 13 | #define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ |
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| 14 | |
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| 15 | #define JZ4740_CLK_EXT 0 |
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| 16 | #define JZ4740_CLK_RTC 1 |
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| 17 | #define JZ4740_CLK_PLL 2 |
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| 18 | #define JZ4740_CLK_PLL_HALF 3 |
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| 19 | #define JZ4740_CLK_CCLK 4 |
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| 20 | #define JZ4740_CLK_HCLK 5 |
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| 21 | #define JZ4740_CLK_PCLK 6 |
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| 22 | #define JZ4740_CLK_MCLK 7 |
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| 23 | #define JZ4740_CLK_LCD 8 |
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| 24 | #define JZ4740_CLK_LCD_PCLK 9 |
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| 25 | #define JZ4740_CLK_I2S 10 |
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| 26 | #define JZ4740_CLK_SPI 11 |
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| 27 | #define JZ4740_CLK_MMC 12 |
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| 28 | #define JZ4740_CLK_UHC 13 |
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| 29 | #define JZ4740_CLK_UDC 14 |
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| 30 | #define JZ4740_CLK_UART0 15 |
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| 31 | #define JZ4740_CLK_UART1 16 |
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| 32 | #define JZ4740_CLK_DMA 17 |
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| 33 | #define JZ4740_CLK_IPU 18 |
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| 34 | #define JZ4740_CLK_ADC 19 |
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| 35 | #define JZ4740_CLK_I2C 20 |
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| 36 | #define JZ4740_CLK_AIC 21 |
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| 37 | #define JZ4740_CLK_TCU 22 |
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| 38 | |
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| 39 | #endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */ |
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| 40 | |
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