1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * This header provides clock numbers for the ingenic,jz4760-cgu DT binding. |
4 | */ |
5 | |
6 | #ifndef __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ |
7 | #define __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ |
8 | |
9 | #define JZ4760_CLK_EXT 0 |
10 | #define JZ4760_CLK_OSC32K 1 |
11 | #define JZ4760_CLK_PLL0 2 |
12 | #define JZ4760_CLK_PLL0_HALF 3 |
13 | #define JZ4760_CLK_PLL1 4 |
14 | #define JZ4760_CLK_CCLK 5 |
15 | #define JZ4760_CLK_HCLK 6 |
16 | #define JZ4760_CLK_SCLK 7 |
17 | #define JZ4760_CLK_H2CLK 8 |
18 | #define JZ4760_CLK_MCLK 9 |
19 | #define JZ4760_CLK_PCLK 10 |
20 | #define JZ4760_CLK_MMC_MUX 11 |
21 | #define JZ4760_CLK_MMC0 12 |
22 | #define JZ4760_CLK_MMC1 13 |
23 | #define JZ4760_CLK_MMC2 14 |
24 | #define JZ4760_CLK_CIM 15 |
25 | #define JZ4760_CLK_UHC 16 |
26 | #define JZ4760_CLK_GPU 17 |
27 | #define JZ4760_CLK_GPS 18 |
28 | #define JZ4760_CLK_SSI_MUX 19 |
29 | #define JZ4760_CLK_PCM 20 |
30 | #define JZ4760_CLK_I2S 21 |
31 | #define JZ4760_CLK_OTG 22 |
32 | #define JZ4760_CLK_SSI0 23 |
33 | #define JZ4760_CLK_SSI1 24 |
34 | #define JZ4760_CLK_SSI2 25 |
35 | #define JZ4760_CLK_DMA 26 |
36 | #define JZ4760_CLK_I2C0 27 |
37 | #define JZ4760_CLK_I2C1 28 |
38 | #define JZ4760_CLK_UART0 29 |
39 | #define JZ4760_CLK_UART1 30 |
40 | #define JZ4760_CLK_UART2 31 |
41 | #define JZ4760_CLK_UART3 32 |
42 | #define JZ4760_CLK_IPU 33 |
43 | #define JZ4760_CLK_ADC 34 |
44 | #define JZ4760_CLK_AIC 35 |
45 | #define JZ4760_CLK_VPU 36 |
46 | #define JZ4760_CLK_UHC_PHY 37 |
47 | #define JZ4760_CLK_OTG_PHY 38 |
48 | #define JZ4760_CLK_EXT512 39 |
49 | #define JZ4760_CLK_RTC 40 |
50 | #define JZ4760_CLK_LPCLK_DIV 41 |
51 | #define JZ4760_CLK_TVE 42 |
52 | #define JZ4760_CLK_LPCLK 43 |
53 | #define JZ4760_CLK_MDMA 44 |
54 | #define JZ4760_CLK_BDMA 45 |
55 | |
56 | #endif /* __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ */ |
57 | |