| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. |
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| 4 | * |
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| 5 | * They are roughly ordered as: |
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| 6 | * - external clocks |
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| 7 | * - PLLs |
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| 8 | * - muxes/dividers in the order they appear in the jz4780 programmers manual |
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| 9 | * - gates in order of their bit in the CLKGR* registers |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ |
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| 13 | #define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ |
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| 14 | |
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| 15 | #define JZ4780_CLK_EXCLK 0 |
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| 16 | #define JZ4780_CLK_RTCLK 1 |
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| 17 | #define JZ4780_CLK_APLL 2 |
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| 18 | #define JZ4780_CLK_MPLL 3 |
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| 19 | #define JZ4780_CLK_EPLL 4 |
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| 20 | #define JZ4780_CLK_VPLL 5 |
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| 21 | #define JZ4780_CLK_OTGPHY 6 |
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| 22 | #define JZ4780_CLK_SCLKA 7 |
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| 23 | #define JZ4780_CLK_CPUMUX 8 |
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| 24 | #define JZ4780_CLK_CPU 9 |
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| 25 | #define JZ4780_CLK_L2CACHE 10 |
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| 26 | #define JZ4780_CLK_AHB0 11 |
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| 27 | #define JZ4780_CLK_AHB2PMUX 12 |
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| 28 | #define JZ4780_CLK_AHB2 13 |
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| 29 | #define JZ4780_CLK_PCLK 14 |
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| 30 | #define JZ4780_CLK_DDR 15 |
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| 31 | #define JZ4780_CLK_VPU 16 |
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| 32 | #define JZ4780_CLK_I2SPLL 17 |
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| 33 | #define JZ4780_CLK_I2S 18 |
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| 34 | #define JZ4780_CLK_LCD0PIXCLK 19 |
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| 35 | #define JZ4780_CLK_LCD1PIXCLK 20 |
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| 36 | #define JZ4780_CLK_MSCMUX 21 |
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| 37 | #define JZ4780_CLK_MSC0 22 |
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| 38 | #define JZ4780_CLK_MSC1 23 |
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| 39 | #define JZ4780_CLK_MSC2 24 |
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| 40 | #define JZ4780_CLK_UHC 25 |
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| 41 | #define JZ4780_CLK_SSIPLL 26 |
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| 42 | #define JZ4780_CLK_SSI 27 |
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| 43 | #define JZ4780_CLK_CIMMCLK 28 |
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| 44 | #define JZ4780_CLK_PCMPLL 29 |
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| 45 | #define JZ4780_CLK_PCM 30 |
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| 46 | #define JZ4780_CLK_GPU 31 |
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| 47 | #define JZ4780_CLK_HDMI 32 |
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| 48 | #define JZ4780_CLK_BCH 33 |
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| 49 | #define JZ4780_CLK_NEMC 34 |
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| 50 | #define JZ4780_CLK_OTG0 35 |
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| 51 | #define JZ4780_CLK_SSI0 36 |
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| 52 | #define JZ4780_CLK_SMB0 37 |
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| 53 | #define JZ4780_CLK_SMB1 38 |
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| 54 | #define JZ4780_CLK_SCC 39 |
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| 55 | #define JZ4780_CLK_AIC 40 |
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| 56 | #define JZ4780_CLK_TSSI0 41 |
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| 57 | #define JZ4780_CLK_OWI 42 |
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| 58 | #define JZ4780_CLK_KBC 43 |
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| 59 | #define JZ4780_CLK_SADC 44 |
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| 60 | #define JZ4780_CLK_UART0 45 |
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| 61 | #define JZ4780_CLK_UART1 46 |
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| 62 | #define JZ4780_CLK_UART2 47 |
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| 63 | #define JZ4780_CLK_UART3 48 |
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| 64 | #define JZ4780_CLK_SSI1 49 |
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| 65 | #define JZ4780_CLK_SSI2 50 |
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| 66 | #define JZ4780_CLK_PDMA 51 |
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| 67 | #define JZ4780_CLK_GPS 52 |
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| 68 | #define JZ4780_CLK_MAC 53 |
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| 69 | #define JZ4780_CLK_SMB2 54 |
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| 70 | #define JZ4780_CLK_CIM 55 |
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| 71 | #define JZ4780_CLK_LCD 56 |
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| 72 | #define JZ4780_CLK_TVE 57 |
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| 73 | #define JZ4780_CLK_IPU 58 |
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| 74 | #define JZ4780_CLK_DDR0 59 |
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| 75 | #define JZ4780_CLK_DDR1 60 |
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| 76 | #define JZ4780_CLK_SMB3 61 |
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| 77 | #define JZ4780_CLK_TSSI1 62 |
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| 78 | #define JZ4780_CLK_COMPRESS 63 |
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| 79 | #define JZ4780_CLK_AIC1 64 |
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| 80 | #define JZ4780_CLK_GPVLC 65 |
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| 81 | #define JZ4780_CLK_OTG1 66 |
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| 82 | #define JZ4780_CLK_UART4 67 |
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| 83 | #define JZ4780_CLK_AHBMON 68 |
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| 84 | #define JZ4780_CLK_SMB4 69 |
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| 85 | #define JZ4780_CLK_DES 70 |
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| 86 | #define JZ4780_CLK_X2D 71 |
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| 87 | #define JZ4780_CLK_CORE1 72 |
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| 88 | #define JZ4780_CLK_EXCLK_DIV512 73 |
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| 89 | #define JZ4780_CLK_RTC 74 |
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| 90 | |
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| 91 | #endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ |
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| 92 | |
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