| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * This header provides clock numbers for the ingenic,x1830-cgu DT binding. |
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| 4 | * |
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| 5 | * They are roughly ordered as: |
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| 6 | * - external clocks |
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| 7 | * - PLLs |
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| 8 | * - muxes/dividers in the order they appear in the x1830 programmers manual |
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| 9 | * - gates in order of their bit in the CLKGR* registers |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__ |
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| 13 | #define __DT_BINDINGS_CLOCK_X1830_CGU_H__ |
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| 14 | |
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| 15 | #define X1830_CLK_EXCLK 0 |
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| 16 | #define X1830_CLK_RTCLK 1 |
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| 17 | #define X1830_CLK_APLL 2 |
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| 18 | #define X1830_CLK_MPLL 3 |
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| 19 | #define X1830_CLK_EPLL 4 |
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| 20 | #define X1830_CLK_VPLL 5 |
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| 21 | #define X1830_CLK_OTGPHY 6 |
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| 22 | #define X1830_CLK_SCLKA 7 |
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| 23 | #define X1830_CLK_CPUMUX 8 |
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| 24 | #define X1830_CLK_CPU 9 |
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| 25 | #define X1830_CLK_L2CACHE 10 |
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| 26 | #define X1830_CLK_AHB0 11 |
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| 27 | #define X1830_CLK_AHB2PMUX 12 |
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| 28 | #define X1830_CLK_AHB2 13 |
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| 29 | #define X1830_CLK_PCLK 14 |
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| 30 | #define X1830_CLK_DDR 15 |
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| 31 | #define X1830_CLK_MAC 16 |
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| 32 | #define X1830_CLK_LCD 17 |
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| 33 | #define X1830_CLK_MSCMUX 18 |
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| 34 | #define X1830_CLK_MSC0 19 |
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| 35 | #define X1830_CLK_MSC1 20 |
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| 36 | #define X1830_CLK_SSIPLL 21 |
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| 37 | #define X1830_CLK_SSIPLL_DIV2 22 |
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| 38 | #define X1830_CLK_SSIMUX 23 |
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| 39 | #define X1830_CLK_EMC 24 |
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| 40 | #define X1830_CLK_EFUSE 25 |
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| 41 | #define X1830_CLK_OTG 26 |
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| 42 | #define X1830_CLK_SSI0 27 |
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| 43 | #define X1830_CLK_SMB0 28 |
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| 44 | #define X1830_CLK_SMB1 29 |
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| 45 | #define X1830_CLK_SMB2 30 |
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| 46 | #define X1830_CLK_UART0 31 |
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| 47 | #define X1830_CLK_UART1 32 |
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| 48 | #define X1830_CLK_SSI1 33 |
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| 49 | #define X1830_CLK_SFC 34 |
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| 50 | #define X1830_CLK_PDMA 35 |
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| 51 | #define X1830_CLK_TCU 36 |
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| 52 | #define X1830_CLK_DTRNG 37 |
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| 53 | #define X1830_CLK_OST 38 |
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| 54 | #define X1830_CLK_EXCLK_DIV512 39 |
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| 55 | #define X1830_CLK_RTC 40 |
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| 56 | |
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| 57 | #endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */ |
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| 58 | |
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