| 1 | /* |
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| 2 | * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com> |
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| 3 | * |
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| 4 | * This code is released using a dual license strategy: BSD/GPL |
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| 5 | * You can choose the licence that better fits your requirements. |
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| 6 | * |
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| 7 | * Released under the terms of 3-clause BSD License |
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| 8 | * Released under the terms of GNU General Public License Version 2.0 |
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| 9 | * |
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| 10 | */ |
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| 11 | |
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| 12 | /* LPC18xx/43xx base clock ids */ |
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| 13 | #define BASE_SAFE_CLK 0 |
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| 14 | #define BASE_USB0_CLK 1 |
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| 15 | #define BASE_PERIPH_CLK 2 |
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| 16 | #define BASE_USB1_CLK 3 |
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| 17 | #define BASE_CPU_CLK 4 |
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| 18 | #define BASE_SPIFI_CLK 5 |
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| 19 | #define BASE_SPI_CLK 6 |
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| 20 | #define BASE_PHY_RX_CLK 7 |
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| 21 | #define BASE_PHY_TX_CLK 8 |
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| 22 | #define BASE_APB1_CLK 9 |
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| 23 | #define BASE_APB3_CLK 10 |
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| 24 | #define BASE_LCD_CLK 11 |
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| 25 | #define BASE_ADCHS_CLK 12 |
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| 26 | #define BASE_SDIO_CLK 13 |
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| 27 | #define BASE_SSP0_CLK 14 |
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| 28 | #define BASE_SSP1_CLK 15 |
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| 29 | #define BASE_UART0_CLK 16 |
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| 30 | #define BASE_UART1_CLK 17 |
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| 31 | #define BASE_UART2_CLK 18 |
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| 32 | #define BASE_UART3_CLK 19 |
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| 33 | #define BASE_OUT_CLK 20 |
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| 34 | #define BASE_RES1_CLK 21 |
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| 35 | #define BASE_RES2_CLK 22 |
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| 36 | #define BASE_RES3_CLK 23 |
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| 37 | #define BASE_RES4_CLK 24 |
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| 38 | #define BASE_AUDIO_CLK 25 |
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| 39 | #define BASE_CGU_OUT0_CLK 26 |
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| 40 | #define BASE_CGU_OUT1_CLK 27 |
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| 41 | #define BASE_CLK_MAX (BASE_CGU_OUT1_CLK + 1) |
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| 42 | |
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