| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef __DTS_MARVELL_PXA1928_CLOCK_H |
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| 3 | #define __DTS_MARVELL_PXA1928_CLOCK_H |
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| 4 | |
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| 5 | /* |
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| 6 | * Clock ID values here correspond to the control register offset/4. |
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| 7 | */ |
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| 8 | |
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| 9 | /* apb peripherals */ |
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| 10 | #define PXA1928_CLK_RTC 0x00 |
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| 11 | #define PXA1928_CLK_TWSI0 0x01 |
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| 12 | #define PXA1928_CLK_TWSI1 0x02 |
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| 13 | #define PXA1928_CLK_TWSI2 0x03 |
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| 14 | #define PXA1928_CLK_TWSI3 0x04 |
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| 15 | #define PXA1928_CLK_OWIRE 0x05 |
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| 16 | #define PXA1928_CLK_KPC 0x06 |
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| 17 | #define PXA1928_CLK_TB_ROTARY 0x07 |
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| 18 | #define PXA1928_CLK_SW_JTAG 0x08 |
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| 19 | #define PXA1928_CLK_TIMER1 0x09 |
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| 20 | #define PXA1928_CLK_UART0 0x0b |
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| 21 | #define PXA1928_CLK_UART1 0x0c |
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| 22 | #define PXA1928_CLK_UART2 0x0d |
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| 23 | #define PXA1928_CLK_GPIO 0x0e |
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| 24 | #define PXA1928_CLK_PWM0 0x0f |
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| 25 | #define PXA1928_CLK_PWM1 0x10 |
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| 26 | #define PXA1928_CLK_PWM2 0x11 |
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| 27 | #define PXA1928_CLK_PWM3 0x12 |
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| 28 | #define PXA1928_CLK_SSP0 0x13 |
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| 29 | #define PXA1928_CLK_SSP1 0x14 |
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| 30 | #define PXA1928_CLK_SSP2 0x15 |
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| 31 | |
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| 32 | #define PXA1928_CLK_TWSI4 0x1f |
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| 33 | #define PXA1928_CLK_TWSI5 0x20 |
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| 34 | #define PXA1928_CLK_UART3 0x22 |
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| 35 | #define PXA1928_CLK_THSENS_GLOB 0x24 |
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| 36 | #define PXA1928_CLK_THSENS_CPU 0x26 |
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| 37 | #define PXA1928_CLK_THSENS_VPU 0x27 |
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| 38 | #define PXA1928_CLK_THSENS_GC 0x28 |
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| 39 | |
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| 40 | |
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| 41 | /* axi peripherals */ |
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| 42 | #define PXA1928_CLK_SDH0 0x15 |
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| 43 | #define PXA1928_CLK_SDH1 0x16 |
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| 44 | #define PXA1928_CLK_USB 0x17 |
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| 45 | #define PXA1928_CLK_NAND 0x18 |
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| 46 | #define PXA1928_CLK_DMA 0x19 |
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| 47 | |
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| 48 | #define PXA1928_CLK_SDH2 0x3a |
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| 49 | #define PXA1928_CLK_SDH3 0x3b |
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| 50 | #define PXA1928_CLK_HSIC 0x3e |
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| 51 | #define PXA1928_CLK_SDH4 0x57 |
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| 52 | #define PXA1928_CLK_GC3D 0x5d |
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| 53 | #define PXA1928_CLK_GC2D 0x5f |
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| 54 | |
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| 55 | #endif |
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| 56 | |
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