| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2017 MediaTek Inc. |
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| 4 | * Author: Weiyi Lu <weiyi.lu@mediatek.com> |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef _DT_BINDINGS_CLK_MT2712_H |
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| 8 | #define _DT_BINDINGS_CLK_MT2712_H |
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| 9 | |
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| 10 | /* APMIXEDSYS */ |
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| 11 | |
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| 12 | #define CLK_APMIXED_MAINPLL 0 |
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| 13 | #define CLK_APMIXED_UNIVPLL 1 |
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| 14 | #define CLK_APMIXED_VCODECPLL 2 |
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| 15 | #define CLK_APMIXED_VENCPLL 3 |
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| 16 | #define CLK_APMIXED_APLL1 4 |
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| 17 | #define CLK_APMIXED_APLL2 5 |
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| 18 | #define CLK_APMIXED_LVDSPLL 6 |
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| 19 | #define CLK_APMIXED_LVDSPLL2 7 |
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| 20 | #define CLK_APMIXED_MSDCPLL 8 |
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| 21 | #define CLK_APMIXED_MSDCPLL2 9 |
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| 22 | #define CLK_APMIXED_TVDPLL 10 |
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| 23 | #define CLK_APMIXED_MMPLL 11 |
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| 24 | #define CLK_APMIXED_ARMCA35PLL 12 |
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| 25 | #define CLK_APMIXED_ARMCA72PLL 13 |
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| 26 | #define CLK_APMIXED_ETHERPLL 14 |
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| 27 | #define CLK_APMIXED_NR_CLK 15 |
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| 28 | |
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| 29 | /* TOPCKGEN */ |
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| 30 | |
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| 31 | #define CLK_TOP_ARMCA35PLL 0 |
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| 32 | #define CLK_TOP_ARMCA35PLL_600M 1 |
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| 33 | #define CLK_TOP_ARMCA35PLL_400M 2 |
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| 34 | #define CLK_TOP_ARMCA72PLL 3 |
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| 35 | #define CLK_TOP_SYSPLL 4 |
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| 36 | #define CLK_TOP_SYSPLL_D2 5 |
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| 37 | #define CLK_TOP_SYSPLL1_D2 6 |
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| 38 | #define CLK_TOP_SYSPLL1_D4 7 |
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| 39 | #define CLK_TOP_SYSPLL1_D8 8 |
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| 40 | #define CLK_TOP_SYSPLL1_D16 9 |
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| 41 | #define CLK_TOP_SYSPLL_D3 10 |
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| 42 | #define CLK_TOP_SYSPLL2_D2 11 |
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| 43 | #define CLK_TOP_SYSPLL2_D4 12 |
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| 44 | #define CLK_TOP_SYSPLL_D5 13 |
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| 45 | #define CLK_TOP_SYSPLL3_D2 14 |
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| 46 | #define CLK_TOP_SYSPLL3_D4 15 |
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| 47 | #define CLK_TOP_SYSPLL_D7 16 |
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| 48 | #define CLK_TOP_SYSPLL4_D2 17 |
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| 49 | #define CLK_TOP_SYSPLL4_D4 18 |
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| 50 | #define CLK_TOP_UNIVPLL 19 |
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| 51 | #define CLK_TOP_UNIVPLL_D7 20 |
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| 52 | #define CLK_TOP_UNIVPLL_D26 21 |
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| 53 | #define CLK_TOP_UNIVPLL_D52 22 |
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| 54 | #define CLK_TOP_UNIVPLL_D104 23 |
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| 55 | #define CLK_TOP_UNIVPLL_D208 24 |
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| 56 | #define CLK_TOP_UNIVPLL_D2 25 |
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| 57 | #define CLK_TOP_UNIVPLL1_D2 26 |
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| 58 | #define CLK_TOP_UNIVPLL1_D4 27 |
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| 59 | #define CLK_TOP_UNIVPLL1_D8 28 |
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| 60 | #define CLK_TOP_UNIVPLL_D3 29 |
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| 61 | #define CLK_TOP_UNIVPLL2_D2 30 |
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| 62 | #define CLK_TOP_UNIVPLL2_D4 31 |
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| 63 | #define CLK_TOP_UNIVPLL2_D8 32 |
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| 64 | #define CLK_TOP_UNIVPLL_D5 33 |
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| 65 | #define CLK_TOP_UNIVPLL3_D2 34 |
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| 66 | #define CLK_TOP_UNIVPLL3_D4 35 |
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| 67 | #define CLK_TOP_UNIVPLL3_D8 36 |
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| 68 | #define CLK_TOP_F_MP0_PLL1 37 |
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| 69 | #define CLK_TOP_F_MP0_PLL2 38 |
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| 70 | #define CLK_TOP_F_BIG_PLL1 39 |
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| 71 | #define CLK_TOP_F_BIG_PLL2 40 |
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| 72 | #define CLK_TOP_F_BUS_PLL1 41 |
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| 73 | #define CLK_TOP_F_BUS_PLL2 42 |
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| 74 | #define CLK_TOP_APLL1 43 |
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| 75 | #define CLK_TOP_APLL1_D2 44 |
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| 76 | #define CLK_TOP_APLL1_D4 45 |
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| 77 | #define CLK_TOP_APLL1_D8 46 |
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| 78 | #define CLK_TOP_APLL1_D16 47 |
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| 79 | #define CLK_TOP_APLL2 48 |
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| 80 | #define CLK_TOP_APLL2_D2 49 |
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| 81 | #define CLK_TOP_APLL2_D4 50 |
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| 82 | #define CLK_TOP_APLL2_D8 51 |
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| 83 | #define CLK_TOP_APLL2_D16 52 |
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| 84 | #define CLK_TOP_LVDSPLL 53 |
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| 85 | #define CLK_TOP_LVDSPLL_D2 54 |
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| 86 | #define CLK_TOP_LVDSPLL_D4 55 |
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| 87 | #define CLK_TOP_LVDSPLL_D8 56 |
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| 88 | #define CLK_TOP_LVDSPLL2 57 |
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| 89 | #define CLK_TOP_LVDSPLL2_D2 58 |
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| 90 | #define CLK_TOP_LVDSPLL2_D4 59 |
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| 91 | #define CLK_TOP_LVDSPLL2_D8 60 |
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| 92 | #define CLK_TOP_ETHERPLL_125M 61 |
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| 93 | #define CLK_TOP_ETHERPLL_50M 62 |
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| 94 | #define CLK_TOP_CVBS 63 |
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| 95 | #define CLK_TOP_CVBS_D2 64 |
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| 96 | #define CLK_TOP_SYS_26M 65 |
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| 97 | #define CLK_TOP_MMPLL 66 |
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| 98 | #define CLK_TOP_MMPLL_D2 67 |
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| 99 | #define CLK_TOP_VENCPLL 68 |
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| 100 | #define CLK_TOP_VENCPLL_D2 69 |
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| 101 | #define CLK_TOP_VCODECPLL 70 |
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| 102 | #define CLK_TOP_VCODECPLL_D2 71 |
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| 103 | #define CLK_TOP_TVDPLL 72 |
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| 104 | #define CLK_TOP_TVDPLL_D2 73 |
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| 105 | #define CLK_TOP_TVDPLL_D4 74 |
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| 106 | #define CLK_TOP_TVDPLL_D8 75 |
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| 107 | #define CLK_TOP_TVDPLL_429M 76 |
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| 108 | #define CLK_TOP_TVDPLL_429M_D2 77 |
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| 109 | #define CLK_TOP_TVDPLL_429M_D4 78 |
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| 110 | #define CLK_TOP_MSDCPLL 79 |
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| 111 | #define CLK_TOP_MSDCPLL_D2 80 |
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| 112 | #define CLK_TOP_MSDCPLL_D4 81 |
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| 113 | #define CLK_TOP_MSDCPLL2 82 |
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| 114 | #define CLK_TOP_MSDCPLL2_D2 83 |
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| 115 | #define CLK_TOP_MSDCPLL2_D4 84 |
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| 116 | #define CLK_TOP_CLK26M_D2 85 |
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| 117 | #define CLK_TOP_D2A_ULCLK_6P5M 86 |
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| 118 | #define CLK_TOP_VPLL3_DPIX 87 |
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| 119 | #define CLK_TOP_VPLL_DPIX 88 |
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| 120 | #define CLK_TOP_LTEPLL_FS26M 89 |
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| 121 | #define CLK_TOP_DMPLL 90 |
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| 122 | #define CLK_TOP_DSI0_LNTC 91 |
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| 123 | #define CLK_TOP_DSI1_LNTC 92 |
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| 124 | #define CLK_TOP_LVDSTX3_CLKDIG_CTS 93 |
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| 125 | #define CLK_TOP_LVDSTX_CLKDIG_CTS 94 |
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| 126 | #define CLK_TOP_CLKRTC_EXT 95 |
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| 127 | #define CLK_TOP_CLKRTC_INT 96 |
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| 128 | #define CLK_TOP_CSI0 97 |
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| 129 | #define CLK_TOP_CVBSPLL 98 |
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| 130 | #define CLK_TOP_AXI_SEL 99 |
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| 131 | #define CLK_TOP_MEM_SEL 100 |
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| 132 | #define CLK_TOP_MM_SEL 101 |
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| 133 | #define CLK_TOP_PWM_SEL 102 |
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| 134 | #define CLK_TOP_VDEC_SEL 103 |
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| 135 | #define CLK_TOP_VENC_SEL 104 |
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| 136 | #define CLK_TOP_MFG_SEL 105 |
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| 137 | #define CLK_TOP_CAMTG_SEL 106 |
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| 138 | #define CLK_TOP_UART_SEL 107 |
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| 139 | #define CLK_TOP_SPI_SEL 108 |
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| 140 | #define CLK_TOP_USB20_SEL 109 |
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| 141 | #define CLK_TOP_USB30_SEL 110 |
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| 142 | #define CLK_TOP_MSDC50_0_HCLK_SEL 111 |
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| 143 | #define CLK_TOP_MSDC50_0_SEL 112 |
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| 144 | #define CLK_TOP_MSDC30_1_SEL 113 |
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| 145 | #define CLK_TOP_MSDC30_2_SEL 114 |
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| 146 | #define CLK_TOP_MSDC30_3_SEL 115 |
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| 147 | #define CLK_TOP_AUDIO_SEL 116 |
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| 148 | #define CLK_TOP_AUD_INTBUS_SEL 117 |
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| 149 | #define CLK_TOP_PMICSPI_SEL 118 |
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| 150 | #define CLK_TOP_DPILVDS1_SEL 119 |
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| 151 | #define CLK_TOP_ATB_SEL 120 |
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| 152 | #define CLK_TOP_NR_SEL 121 |
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| 153 | #define CLK_TOP_NFI2X_SEL 122 |
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| 154 | #define CLK_TOP_IRDA_SEL 123 |
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| 155 | #define CLK_TOP_CCI400_SEL 124 |
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| 156 | #define CLK_TOP_AUD_1_SEL 125 |
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| 157 | #define CLK_TOP_AUD_2_SEL 126 |
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| 158 | #define CLK_TOP_MEM_MFG_IN_AS_SEL 127 |
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| 159 | #define CLK_TOP_AXI_MFG_IN_AS_SEL 128 |
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| 160 | #define CLK_TOP_SCAM_SEL 129 |
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| 161 | #define CLK_TOP_NFIECC_SEL 130 |
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| 162 | #define CLK_TOP_PE2_MAC_P0_SEL 131 |
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| 163 | #define CLK_TOP_PE2_MAC_P1_SEL 132 |
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| 164 | #define CLK_TOP_DPILVDS_SEL 133 |
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| 165 | #define CLK_TOP_MSDC50_3_HCLK_SEL 134 |
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| 166 | #define CLK_TOP_HDCP_SEL 135 |
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| 167 | #define CLK_TOP_HDCP_24M_SEL 136 |
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| 168 | #define CLK_TOP_RTC_SEL 137 |
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| 169 | #define CLK_TOP_SPINOR_SEL 138 |
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| 170 | #define CLK_TOP_APLL_SEL 139 |
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| 171 | #define CLK_TOP_APLL2_SEL 140 |
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| 172 | #define CLK_TOP_A1SYS_HP_SEL 141 |
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| 173 | #define CLK_TOP_A2SYS_HP_SEL 142 |
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| 174 | #define CLK_TOP_ASM_L_SEL 143 |
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| 175 | #define CLK_TOP_ASM_M_SEL 144 |
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| 176 | #define CLK_TOP_ASM_H_SEL 145 |
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| 177 | #define CLK_TOP_I2SO1_SEL 146 |
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| 178 | #define CLK_TOP_I2SO2_SEL 147 |
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| 179 | #define CLK_TOP_I2SO3_SEL 148 |
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| 180 | #define CLK_TOP_TDMO0_SEL 149 |
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| 181 | #define CLK_TOP_TDMO1_SEL 150 |
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| 182 | #define CLK_TOP_I2SI1_SEL 151 |
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| 183 | #define CLK_TOP_I2SI2_SEL 152 |
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| 184 | #define CLK_TOP_I2SI3_SEL 153 |
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| 185 | #define CLK_TOP_ETHER_125M_SEL 154 |
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| 186 | #define CLK_TOP_ETHER_50M_SEL 155 |
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| 187 | #define CLK_TOP_JPGDEC_SEL 156 |
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| 188 | #define CLK_TOP_SPISLV_SEL 157 |
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| 189 | #define CLK_TOP_ETHER_50M_RMII_SEL 158 |
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| 190 | #define CLK_TOP_CAM2TG_SEL 159 |
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| 191 | #define CLK_TOP_DI_SEL 160 |
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| 192 | #define CLK_TOP_TVD_SEL 161 |
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| 193 | #define CLK_TOP_I2C_SEL 162 |
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| 194 | #define CLK_TOP_PWM_INFRA_SEL 163 |
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| 195 | #define CLK_TOP_MSDC0P_AES_SEL 164 |
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| 196 | #define CLK_TOP_CMSYS_SEL 165 |
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| 197 | #define CLK_TOP_GCPU_SEL 166 |
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| 198 | #define CLK_TOP_AUD_APLL1_SEL 167 |
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| 199 | #define CLK_TOP_AUD_APLL2_SEL 168 |
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| 200 | #define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169 |
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| 201 | #define CLK_TOP_APLL_DIV0 170 |
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| 202 | #define CLK_TOP_APLL_DIV1 171 |
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| 203 | #define CLK_TOP_APLL_DIV2 172 |
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| 204 | #define CLK_TOP_APLL_DIV3 173 |
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| 205 | #define CLK_TOP_APLL_DIV4 174 |
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| 206 | #define CLK_TOP_APLL_DIV5 175 |
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| 207 | #define CLK_TOP_APLL_DIV6 176 |
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| 208 | #define CLK_TOP_APLL_DIV7 177 |
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| 209 | #define CLK_TOP_APLL_DIV_PDN0 178 |
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| 210 | #define CLK_TOP_APLL_DIV_PDN1 179 |
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| 211 | #define CLK_TOP_APLL_DIV_PDN2 180 |
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| 212 | #define CLK_TOP_APLL_DIV_PDN3 181 |
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| 213 | #define CLK_TOP_APLL_DIV_PDN4 182 |
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| 214 | #define CLK_TOP_APLL_DIV_PDN5 183 |
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| 215 | #define CLK_TOP_APLL_DIV_PDN6 184 |
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| 216 | #define CLK_TOP_APLL_DIV_PDN7 185 |
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| 217 | #define CLK_TOP_APLL1_D3 186 |
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| 218 | #define CLK_TOP_APLL1_REF_SEL 187 |
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| 219 | #define CLK_TOP_APLL2_REF_SEL 188 |
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| 220 | #define CLK_TOP_NFI2X_EN 189 |
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| 221 | #define CLK_TOP_NFIECC_EN 190 |
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| 222 | #define CLK_TOP_NFI1X_CK_EN 191 |
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| 223 | #define CLK_TOP_APLL2_D3 192 |
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| 224 | #define CLK_TOP_NR_CLK 193 |
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| 225 | |
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| 226 | /* INFRACFG */ |
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| 227 | |
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| 228 | #define CLK_INFRA_DBGCLK 0 |
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| 229 | #define CLK_INFRA_GCE 1 |
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| 230 | #define CLK_INFRA_M4U 2 |
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| 231 | #define CLK_INFRA_KP 3 |
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| 232 | #define CLK_INFRA_AO_SPI0 4 |
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| 233 | #define CLK_INFRA_AO_SPI1 5 |
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| 234 | #define CLK_INFRA_AO_UART5 6 |
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| 235 | #define CLK_INFRA_NR_CLK 7 |
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| 236 | |
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| 237 | /* PERICFG */ |
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| 238 | |
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| 239 | #define CLK_PERI_NFI 0 |
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| 240 | #define CLK_PERI_THERM 1 |
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| 241 | #define CLK_PERI_PWM0 2 |
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| 242 | #define CLK_PERI_PWM1 3 |
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| 243 | #define CLK_PERI_PWM2 4 |
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| 244 | #define CLK_PERI_PWM3 5 |
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| 245 | #define CLK_PERI_PWM4 6 |
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| 246 | #define CLK_PERI_PWM5 7 |
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| 247 | #define CLK_PERI_PWM6 8 |
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| 248 | #define CLK_PERI_PWM7 9 |
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| 249 | #define CLK_PERI_PWM 10 |
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| 250 | #define CLK_PERI_AP_DMA 11 |
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| 251 | #define CLK_PERI_MSDC30_0 12 |
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| 252 | #define CLK_PERI_MSDC30_1 13 |
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| 253 | #define CLK_PERI_MSDC30_2 14 |
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| 254 | #define CLK_PERI_MSDC30_3 15 |
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| 255 | #define CLK_PERI_UART0 16 |
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| 256 | #define CLK_PERI_UART1 17 |
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| 257 | #define CLK_PERI_UART2 18 |
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| 258 | #define CLK_PERI_UART3 19 |
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| 259 | #define CLK_PERI_I2C0 20 |
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| 260 | #define CLK_PERI_I2C1 21 |
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| 261 | #define CLK_PERI_I2C2 22 |
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| 262 | #define CLK_PERI_I2C3 23 |
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| 263 | #define CLK_PERI_I2C4 24 |
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| 264 | #define CLK_PERI_AUXADC 25 |
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| 265 | #define CLK_PERI_SPI0 26 |
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| 266 | #define CLK_PERI_SPI 27 |
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| 267 | #define CLK_PERI_I2C5 28 |
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| 268 | #define CLK_PERI_SPI2 29 |
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| 269 | #define CLK_PERI_SPI3 30 |
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| 270 | #define CLK_PERI_SPI5 31 |
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| 271 | #define CLK_PERI_UART4 32 |
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| 272 | #define CLK_PERI_SFLASH 33 |
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| 273 | #define CLK_PERI_GMAC 34 |
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| 274 | #define CLK_PERI_PCIE0 35 |
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| 275 | #define CLK_PERI_PCIE1 36 |
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| 276 | #define CLK_PERI_GMAC_PCLK 37 |
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| 277 | #define CLK_PERI_MSDC50_0_EN 38 |
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| 278 | #define CLK_PERI_MSDC30_1_EN 39 |
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| 279 | #define CLK_PERI_MSDC30_2_EN 40 |
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| 280 | #define CLK_PERI_MSDC30_3_EN 41 |
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| 281 | #define CLK_PERI_MSDC50_0_HCLK_EN 42 |
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| 282 | #define CLK_PERI_MSDC50_3_HCLK_EN 43 |
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| 283 | #define CLK_PERI_MSDC30_0_QTR_EN 44 |
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| 284 | #define CLK_PERI_MSDC30_3_QTR_EN 45 |
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| 285 | #define CLK_PERI_NR_CLK 46 |
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| 286 | |
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| 287 | /* MCUCFG */ |
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| 288 | |
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| 289 | #define CLK_MCU_MP0_SEL 0 |
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| 290 | #define CLK_MCU_MP2_SEL 1 |
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| 291 | #define CLK_MCU_BUS_SEL 2 |
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| 292 | #define CLK_MCU_NR_CLK 3 |
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| 293 | |
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| 294 | /* MFGCFG */ |
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| 295 | |
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| 296 | #define CLK_MFG_BG3D 0 |
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| 297 | #define CLK_MFG_NR_CLK 1 |
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| 298 | |
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| 299 | /* MMSYS */ |
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| 300 | |
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| 301 | #define CLK_MM_SMI_COMMON 0 |
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| 302 | #define CLK_MM_SMI_LARB0 1 |
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| 303 | #define CLK_MM_CAM_MDP 2 |
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| 304 | #define CLK_MM_MDP_RDMA0 3 |
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| 305 | #define CLK_MM_MDP_RDMA1 4 |
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| 306 | #define CLK_MM_MDP_RSZ0 5 |
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| 307 | #define CLK_MM_MDP_RSZ1 6 |
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| 308 | #define CLK_MM_MDP_RSZ2 7 |
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| 309 | #define CLK_MM_MDP_TDSHP0 8 |
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| 310 | #define CLK_MM_MDP_TDSHP1 9 |
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| 311 | #define CLK_MM_MDP_CROP 10 |
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| 312 | #define CLK_MM_MDP_WDMA 11 |
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| 313 | #define CLK_MM_MDP_WROT0 12 |
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| 314 | #define CLK_MM_MDP_WROT1 13 |
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| 315 | #define CLK_MM_FAKE_ENG 14 |
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| 316 | #define CLK_MM_MUTEX_32K 15 |
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| 317 | #define CLK_MM_DISP_OVL0 16 |
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| 318 | #define CLK_MM_DISP_OVL1 17 |
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| 319 | #define CLK_MM_DISP_RDMA0 18 |
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| 320 | #define CLK_MM_DISP_RDMA1 19 |
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| 321 | #define CLK_MM_DISP_RDMA2 20 |
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| 322 | #define CLK_MM_DISP_WDMA0 21 |
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| 323 | #define CLK_MM_DISP_WDMA1 22 |
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| 324 | #define CLK_MM_DISP_COLOR0 23 |
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| 325 | #define CLK_MM_DISP_COLOR1 24 |
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| 326 | #define CLK_MM_DISP_AAL 25 |
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| 327 | #define CLK_MM_DISP_GAMMA 26 |
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| 328 | #define CLK_MM_DISP_UFOE 27 |
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| 329 | #define CLK_MM_DISP_SPLIT0 28 |
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| 330 | #define CLK_MM_DISP_OD 29 |
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| 331 | #define CLK_MM_DISP_PWM0_MM 30 |
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| 332 | #define CLK_MM_DISP_PWM0_26M 31 |
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| 333 | #define CLK_MM_DISP_PWM1_MM 32 |
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| 334 | #define CLK_MM_DISP_PWM1_26M 33 |
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| 335 | #define CLK_MM_DSI0_ENGINE 34 |
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| 336 | #define CLK_MM_DSI0_DIGITAL 35 |
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| 337 | #define CLK_MM_DSI1_ENGINE 36 |
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| 338 | #define CLK_MM_DSI1_DIGITAL 37 |
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| 339 | #define CLK_MM_DPI_PIXEL 38 |
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| 340 | #define CLK_MM_DPI_ENGINE 39 |
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| 341 | #define CLK_MM_DPI1_PIXEL 40 |
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| 342 | #define CLK_MM_DPI1_ENGINE 41 |
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| 343 | #define CLK_MM_LVDS_PIXEL 42 |
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| 344 | #define CLK_MM_LVDS_CTS 43 |
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| 345 | #define CLK_MM_SMI_LARB4 44 |
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| 346 | #define CLK_MM_SMI_COMMON1 45 |
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| 347 | #define CLK_MM_SMI_LARB5 46 |
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| 348 | #define CLK_MM_MDP_RDMA2 47 |
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| 349 | #define CLK_MM_MDP_TDSHP2 48 |
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| 350 | #define CLK_MM_DISP_OVL2 49 |
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| 351 | #define CLK_MM_DISP_WDMA2 50 |
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| 352 | #define CLK_MM_DISP_COLOR2 51 |
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| 353 | #define CLK_MM_DISP_AAL1 52 |
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| 354 | #define CLK_MM_DISP_OD1 53 |
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| 355 | #define CLK_MM_LVDS1_PIXEL 54 |
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| 356 | #define CLK_MM_LVDS1_CTS 55 |
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| 357 | #define CLK_MM_SMI_LARB7 56 |
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| 358 | #define CLK_MM_MDP_RDMA3 57 |
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| 359 | #define CLK_MM_MDP_WROT2 58 |
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| 360 | #define CLK_MM_DSI2 59 |
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| 361 | #define CLK_MM_DSI2_DIGITAL 60 |
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| 362 | #define CLK_MM_DSI3 61 |
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| 363 | #define CLK_MM_DSI3_DIGITAL 62 |
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| 364 | #define CLK_MM_NR_CLK 63 |
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| 365 | |
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| 366 | /* IMGSYS */ |
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| 367 | |
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| 368 | #define CLK_IMG_SMI_LARB2 0 |
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| 369 | #define CLK_IMG_SENINF_SCAM_EN 1 |
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| 370 | #define CLK_IMG_SENINF_CAM_EN 2 |
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| 371 | #define CLK_IMG_CAM_SV_EN 3 |
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| 372 | #define CLK_IMG_CAM_SV1_EN 4 |
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| 373 | #define CLK_IMG_CAM_SV2_EN 5 |
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| 374 | #define CLK_IMG_NR_CLK 6 |
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| 375 | |
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| 376 | /* BDPSYS */ |
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| 377 | |
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| 378 | #define CLK_BDP_BRIDGE_B 0 |
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| 379 | #define CLK_BDP_BRIDGE_DRAM 1 |
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| 380 | #define CLK_BDP_LARB_DRAM 2 |
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| 381 | #define CLK_BDP_WR_CHANNEL_VDI_PXL 3 |
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| 382 | #define CLK_BDP_WR_CHANNEL_VDI_DRAM 4 |
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| 383 | #define CLK_BDP_WR_CHANNEL_VDI_B 5 |
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| 384 | #define CLK_BDP_MT_B 6 |
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| 385 | #define CLK_BDP_DISPFMT_27M 7 |
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| 386 | #define CLK_BDP_DISPFMT_27M_VDOUT 8 |
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| 387 | #define CLK_BDP_DISPFMT_27_74_74 9 |
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| 388 | #define CLK_BDP_DISPFMT_2FS 10 |
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| 389 | #define CLK_BDP_DISPFMT_2FS_2FS74_148 11 |
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| 390 | #define CLK_BDP_DISPFMT_B 12 |
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| 391 | #define CLK_BDP_VDO_DRAM 13 |
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| 392 | #define CLK_BDP_VDO_2FS 14 |
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| 393 | #define CLK_BDP_VDO_B 15 |
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| 394 | #define CLK_BDP_WR_CHANNEL_DI_PXL 16 |
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| 395 | #define CLK_BDP_WR_CHANNEL_DI_DRAM 17 |
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| 396 | #define CLK_BDP_WR_CHANNEL_DI_B 18 |
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| 397 | #define CLK_BDP_NR_AGENT 19 |
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| 398 | #define CLK_BDP_NR_DRAM 20 |
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| 399 | #define CLK_BDP_NR_B 21 |
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| 400 | #define CLK_BDP_BRIDGE_RT_B 22 |
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| 401 | #define CLK_BDP_BRIDGE_RT_DRAM 23 |
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| 402 | #define CLK_BDP_LARB_RT_DRAM 24 |
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| 403 | #define CLK_BDP_TVD_TDC 25 |
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| 404 | #define CLK_BDP_TVD_54 26 |
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| 405 | #define CLK_BDP_TVD_CBUS 27 |
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| 406 | #define CLK_BDP_NR_CLK 28 |
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| 407 | |
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| 408 | /* VDECSYS */ |
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| 409 | |
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| 410 | #define CLK_VDEC_CKEN 0 |
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| 411 | #define CLK_VDEC_LARB1_CKEN 1 |
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| 412 | #define CLK_VDEC_IMGRZ_CKEN 2 |
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| 413 | #define CLK_VDEC_NR_CLK 3 |
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| 414 | |
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| 415 | /* VENCSYS */ |
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| 416 | |
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| 417 | #define CLK_VENC_SMI_COMMON_CON 0 |
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| 418 | #define CLK_VENC_VENC 1 |
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| 419 | #define CLK_VENC_SMI_LARB6 2 |
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| 420 | #define CLK_VENC_NR_CLK 3 |
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| 421 | |
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| 422 | /* JPGDECSYS */ |
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| 423 | |
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| 424 | #define CLK_JPGDEC_JPGDEC1 0 |
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| 425 | #define CLK_JPGDEC_JPGDEC 1 |
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| 426 | #define CLK_JPGDEC_NR_CLK 2 |
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| 427 | |
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| 428 | #endif /* _DT_BINDINGS_CLK_MT2712_H */ |
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| 429 | |
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