| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2017 MediaTek Inc. |
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| 4 | * Author: Kevin Chen <kevin-cw.chen@mediatek.com> |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef _DT_BINDINGS_CLK_MT6797_H |
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| 8 | #define _DT_BINDINGS_CLK_MT6797_H |
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| 9 | |
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| 10 | /* TOPCKGEN */ |
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| 11 | #define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE 1 |
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| 12 | #define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX 2 |
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| 13 | #define CLK_TOP_MUX_AXI 3 |
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| 14 | #define CLK_TOP_MUX_MEM 4 |
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| 15 | #define CLK_TOP_MUX_DDRPHYCFG 5 |
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| 16 | #define CLK_TOP_MUX_MM 6 |
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| 17 | #define CLK_TOP_MUX_PWM 7 |
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| 18 | #define CLK_TOP_MUX_VDEC 8 |
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| 19 | #define CLK_TOP_MUX_VENC 9 |
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| 20 | #define CLK_TOP_MUX_MFG 10 |
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| 21 | #define CLK_TOP_MUX_CAMTG 11 |
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| 22 | #define CLK_TOP_MUX_UART 12 |
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| 23 | #define CLK_TOP_MUX_SPI 13 |
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| 24 | #define CLK_TOP_MUX_ULPOSC_SPI_CK_MUX 14 |
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| 25 | #define CLK_TOP_MUX_USB20 15 |
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| 26 | #define CLK_TOP_MUX_MSDC50_0_HCLK 16 |
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| 27 | #define CLK_TOP_MUX_MSDC50_0 17 |
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| 28 | #define CLK_TOP_MUX_MSDC30_1 18 |
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| 29 | #define CLK_TOP_MUX_MSDC30_2 19 |
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| 30 | #define CLK_TOP_MUX_AUDIO 20 |
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| 31 | #define CLK_TOP_MUX_AUD_INTBUS 21 |
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| 32 | #define CLK_TOP_MUX_PMICSPI 22 |
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| 33 | #define CLK_TOP_MUX_SCP 23 |
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| 34 | #define CLK_TOP_MUX_ATB 24 |
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| 35 | #define CLK_TOP_MUX_MJC 25 |
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| 36 | #define CLK_TOP_MUX_DPI0 26 |
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| 37 | #define CLK_TOP_MUX_AUD_1 27 |
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| 38 | #define CLK_TOP_MUX_AUD_2 28 |
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| 39 | #define CLK_TOP_MUX_SSUSB_TOP_SYS 29 |
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| 40 | #define CLK_TOP_MUX_SPM 30 |
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| 41 | #define CLK_TOP_MUX_BSI_SPI 31 |
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| 42 | #define CLK_TOP_MUX_AUDIO_H 32 |
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| 43 | #define CLK_TOP_MUX_ANC_MD32 33 |
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| 44 | #define CLK_TOP_MUX_MFG_52M 34 |
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| 45 | #define CLK_TOP_SYSPLL_CK 35 |
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| 46 | #define CLK_TOP_SYSPLL_D2 36 |
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| 47 | #define CLK_TOP_SYSPLL1_D2 37 |
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| 48 | #define CLK_TOP_SYSPLL1_D4 38 |
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| 49 | #define CLK_TOP_SYSPLL1_D8 39 |
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| 50 | #define CLK_TOP_SYSPLL1_D16 40 |
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| 51 | #define CLK_TOP_SYSPLL_D3 41 |
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| 52 | #define CLK_TOP_SYSPLL_D3_D3 42 |
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| 53 | #define CLK_TOP_SYSPLL2_D2 43 |
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| 54 | #define CLK_TOP_SYSPLL2_D4 44 |
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| 55 | #define CLK_TOP_SYSPLL2_D8 45 |
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| 56 | #define CLK_TOP_SYSPLL_D5 46 |
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| 57 | #define CLK_TOP_SYSPLL3_D2 47 |
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| 58 | #define CLK_TOP_SYSPLL3_D4 48 |
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| 59 | #define CLK_TOP_SYSPLL_D7 49 |
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| 60 | #define CLK_TOP_SYSPLL4_D2 50 |
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| 61 | #define CLK_TOP_SYSPLL4_D4 51 |
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| 62 | #define CLK_TOP_UNIVPLL_CK 52 |
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| 63 | #define CLK_TOP_UNIVPLL_D7 53 |
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| 64 | #define CLK_TOP_UNIVPLL_D26 54 |
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| 65 | #define CLK_TOP_SSUSB_PHY_48M_CK 55 |
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| 66 | #define CLK_TOP_USB_PHY48M_CK 56 |
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| 67 | #define CLK_TOP_UNIVPLL_D2 57 |
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| 68 | #define CLK_TOP_UNIVPLL1_D2 58 |
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| 69 | #define CLK_TOP_UNIVPLL1_D4 59 |
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| 70 | #define CLK_TOP_UNIVPLL1_D8 60 |
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| 71 | #define CLK_TOP_UNIVPLL_D3 61 |
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| 72 | #define CLK_TOP_UNIVPLL2_D2 62 |
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| 73 | #define CLK_TOP_UNIVPLL2_D4 63 |
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| 74 | #define CLK_TOP_UNIVPLL2_D8 64 |
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| 75 | #define CLK_TOP_UNIVPLL_D5 65 |
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| 76 | #define CLK_TOP_UNIVPLL3_D2 66 |
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| 77 | #define CLK_TOP_UNIVPLL3_D4 67 |
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| 78 | #define CLK_TOP_UNIVPLL3_D8 68 |
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| 79 | #define CLK_TOP_ULPOSC_CK_ORG 69 |
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| 80 | #define CLK_TOP_ULPOSC_CK 70 |
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| 81 | #define CLK_TOP_ULPOSC_D2 71 |
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| 82 | #define CLK_TOP_ULPOSC_D3 72 |
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| 83 | #define CLK_TOP_ULPOSC_D4 73 |
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| 84 | #define CLK_TOP_ULPOSC_D8 74 |
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| 85 | #define CLK_TOP_ULPOSC_D10 75 |
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| 86 | #define CLK_TOP_APLL1_CK 76 |
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| 87 | #define CLK_TOP_APLL2_CK 77 |
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| 88 | #define CLK_TOP_MFGPLL_CK 78 |
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| 89 | #define CLK_TOP_MFGPLL_D2 79 |
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| 90 | #define CLK_TOP_IMGPLL_CK 80 |
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| 91 | #define CLK_TOP_IMGPLL_D2 81 |
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| 92 | #define CLK_TOP_IMGPLL_D4 82 |
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| 93 | #define CLK_TOP_CODECPLL_CK 83 |
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| 94 | #define CLK_TOP_CODECPLL_D2 84 |
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| 95 | #define CLK_TOP_VDECPLL_CK 85 |
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| 96 | #define CLK_TOP_TVDPLL_CK 86 |
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| 97 | #define CLK_TOP_TVDPLL_D2 87 |
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| 98 | #define CLK_TOP_TVDPLL_D4 88 |
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| 99 | #define CLK_TOP_TVDPLL_D8 89 |
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| 100 | #define CLK_TOP_TVDPLL_D16 90 |
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| 101 | #define CLK_TOP_MSDCPLL_CK 91 |
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| 102 | #define CLK_TOP_MSDCPLL_D2 92 |
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| 103 | #define CLK_TOP_MSDCPLL_D4 93 |
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| 104 | #define CLK_TOP_MSDCPLL_D8 94 |
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| 105 | #define CLK_TOP_NR 95 |
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| 106 | |
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| 107 | /* APMIXED_SYS */ |
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| 108 | #define CLK_APMIXED_MAINPLL 1 |
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| 109 | #define CLK_APMIXED_UNIVPLL 2 |
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| 110 | #define CLK_APMIXED_MFGPLL 3 |
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| 111 | #define CLK_APMIXED_MSDCPLL 4 |
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| 112 | #define CLK_APMIXED_IMGPLL 5 |
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| 113 | #define CLK_APMIXED_TVDPLL 6 |
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| 114 | #define CLK_APMIXED_CODECPLL 7 |
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| 115 | #define CLK_APMIXED_VDECPLL 8 |
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| 116 | #define CLK_APMIXED_APLL1 9 |
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| 117 | #define CLK_APMIXED_APLL2 10 |
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| 118 | #define CLK_APMIXED_NR 11 |
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| 119 | |
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| 120 | /* INFRA_SYS */ |
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| 121 | #define CLK_INFRA_PMIC_TMR 1 |
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| 122 | #define CLK_INFRA_PMIC_AP 2 |
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| 123 | #define CLK_INFRA_PMIC_MD 3 |
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| 124 | #define CLK_INFRA_PMIC_CONN 4 |
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| 125 | #define CLK_INFRA_SCP 5 |
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| 126 | #define CLK_INFRA_SEJ 6 |
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| 127 | #define CLK_INFRA_APXGPT 7 |
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| 128 | #define CLK_INFRA_SEJ_13M 8 |
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| 129 | #define CLK_INFRA_ICUSB 9 |
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| 130 | #define CLK_INFRA_GCE 10 |
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| 131 | #define CLK_INFRA_THERM 11 |
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| 132 | #define CLK_INFRA_I2C0 12 |
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| 133 | #define CLK_INFRA_I2C1 13 |
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| 134 | #define CLK_INFRA_I2C2 14 |
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| 135 | #define CLK_INFRA_I2C3 15 |
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| 136 | #define CLK_INFRA_PWM_HCLK 16 |
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| 137 | #define CLK_INFRA_PWM1 17 |
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| 138 | #define CLK_INFRA_PWM2 18 |
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| 139 | #define CLK_INFRA_PWM3 19 |
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| 140 | #define CLK_INFRA_PWM4 20 |
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| 141 | #define CLK_INFRA_PWM 21 |
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| 142 | #define CLK_INFRA_UART0 22 |
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| 143 | #define CLK_INFRA_UART1 23 |
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| 144 | #define CLK_INFRA_UART2 24 |
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| 145 | #define CLK_INFRA_UART3 25 |
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| 146 | #define CLK_INFRA_MD2MD_CCIF_0 26 |
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| 147 | #define CLK_INFRA_MD2MD_CCIF_1 27 |
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| 148 | #define CLK_INFRA_MD2MD_CCIF_2 28 |
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| 149 | #define CLK_INFRA_FHCTL 29 |
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| 150 | #define CLK_INFRA_BTIF 30 |
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| 151 | #define CLK_INFRA_MD2MD_CCIF_3 31 |
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| 152 | #define CLK_INFRA_SPI 32 |
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| 153 | #define CLK_INFRA_MSDC0 33 |
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| 154 | #define CLK_INFRA_MD2MD_CCIF_4 34 |
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| 155 | #define CLK_INFRA_MSDC1 35 |
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| 156 | #define CLK_INFRA_MSDC2 36 |
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| 157 | #define CLK_INFRA_MD2MD_CCIF_5 37 |
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| 158 | #define CLK_INFRA_GCPU 38 |
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| 159 | #define CLK_INFRA_TRNG 39 |
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| 160 | #define CLK_INFRA_AUXADC 40 |
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| 161 | #define CLK_INFRA_CPUM 41 |
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| 162 | #define CLK_INFRA_AP_C2K_CCIF_0 42 |
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| 163 | #define CLK_INFRA_AP_C2K_CCIF_1 43 |
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| 164 | #define CLK_INFRA_CLDMA 44 |
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| 165 | #define CLK_INFRA_DISP_PWM 45 |
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| 166 | #define CLK_INFRA_AP_DMA 46 |
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| 167 | #define CLK_INFRA_DEVICE_APC 47 |
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| 168 | #define CLK_INFRA_L2C_SRAM 48 |
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| 169 | #define CLK_INFRA_CCIF_AP 49 |
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| 170 | #define CLK_INFRA_AUDIO 50 |
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| 171 | #define CLK_INFRA_CCIF_MD 51 |
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| 172 | #define CLK_INFRA_DRAMC_F26M 52 |
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| 173 | #define CLK_INFRA_I2C4 53 |
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| 174 | #define CLK_INFRA_I2C_APPM 54 |
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| 175 | #define CLK_INFRA_I2C_GPUPM 55 |
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| 176 | #define CLK_INFRA_I2C2_IMM 56 |
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| 177 | #define CLK_INFRA_I2C2_ARB 57 |
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| 178 | #define CLK_INFRA_I2C3_IMM 58 |
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| 179 | #define CLK_INFRA_I2C3_ARB 59 |
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| 180 | #define CLK_INFRA_I2C5 60 |
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| 181 | #define CLK_INFRA_SYS_CIRQ 61 |
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| 182 | #define CLK_INFRA_SPI1 62 |
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| 183 | #define CLK_INFRA_DRAMC_B_F26M 63 |
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| 184 | #define CLK_INFRA_ANC_MD32 64 |
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| 185 | #define CLK_INFRA_ANC_MD32_32K 65 |
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| 186 | #define CLK_INFRA_DVFS_SPM1 66 |
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| 187 | #define CLK_INFRA_AES_TOP0 67 |
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| 188 | #define CLK_INFRA_AES_TOP1 68 |
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| 189 | #define CLK_INFRA_SSUSB_BUS 69 |
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| 190 | #define CLK_INFRA_SPI2 70 |
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| 191 | #define CLK_INFRA_SPI3 71 |
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| 192 | #define CLK_INFRA_SPI4 72 |
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| 193 | #define CLK_INFRA_SPI5 73 |
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| 194 | #define CLK_INFRA_IRTX 74 |
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| 195 | #define CLK_INFRA_SSUSB_SYS 75 |
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| 196 | #define CLK_INFRA_SSUSB_REF 76 |
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| 197 | #define CLK_INFRA_AUDIO_26M 77 |
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| 198 | #define CLK_INFRA_AUDIO_26M_PAD_TOP 78 |
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| 199 | #define CLK_INFRA_MODEM_TEMP_SHARE 79 |
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| 200 | #define CLK_INFRA_VAD_WRAP_SOC 80 |
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| 201 | #define CLK_INFRA_DRAMC_CONF 81 |
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| 202 | #define CLK_INFRA_DRAMC_B_CONF 82 |
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| 203 | #define CLK_INFRA_MFG_VCG 83 |
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| 204 | #define CLK_INFRA_13M 84 |
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| 205 | #define CLK_INFRA_NR 85 |
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| 206 | |
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| 207 | /* IMG_SYS */ |
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| 208 | #define CLK_IMG_FDVT 1 |
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| 209 | #define CLK_IMG_DPE 2 |
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| 210 | #define CLK_IMG_DIP 3 |
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| 211 | #define CLK_IMG_LARB6 4 |
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| 212 | #define CLK_IMG_NR 5 |
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| 213 | |
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| 214 | /* MM_SYS */ |
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| 215 | #define CLK_MM_SMI_COMMON 1 |
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| 216 | #define CLK_MM_SMI_LARB0 2 |
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| 217 | #define CLK_MM_SMI_LARB5 3 |
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| 218 | #define CLK_MM_CAM_MDP 4 |
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| 219 | #define CLK_MM_MDP_RDMA0 5 |
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| 220 | #define CLK_MM_MDP_RDMA1 6 |
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| 221 | #define CLK_MM_MDP_RSZ0 7 |
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| 222 | #define CLK_MM_MDP_RSZ1 8 |
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| 223 | #define CLK_MM_MDP_RSZ2 9 |
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| 224 | #define CLK_MM_MDP_TDSHP 10 |
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| 225 | #define CLK_MM_MDP_COLOR 11 |
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| 226 | #define CLK_MM_MDP_WDMA 12 |
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| 227 | #define CLK_MM_MDP_WROT0 13 |
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| 228 | #define CLK_MM_MDP_WROT1 14 |
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| 229 | #define CLK_MM_FAKE_ENG 15 |
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| 230 | #define CLK_MM_DISP_OVL0 16 |
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| 231 | #define CLK_MM_DISP_OVL1 17 |
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| 232 | #define CLK_MM_DISP_OVL0_2L 18 |
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| 233 | #define CLK_MM_DISP_OVL1_2L 19 |
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| 234 | #define CLK_MM_DISP_RDMA0 20 |
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| 235 | #define CLK_MM_DISP_RDMA1 21 |
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| 236 | #define CLK_MM_DISP_WDMA0 22 |
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| 237 | #define CLK_MM_DISP_WDMA1 23 |
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| 238 | #define CLK_MM_DISP_COLOR 24 |
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| 239 | #define CLK_MM_DISP_CCORR 25 |
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| 240 | #define CLK_MM_DISP_AAL 26 |
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| 241 | #define CLK_MM_DISP_GAMMA 27 |
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| 242 | #define CLK_MM_DISP_OD 28 |
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| 243 | #define CLK_MM_DISP_DITHER 29 |
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| 244 | #define CLK_MM_DISP_UFOE 30 |
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| 245 | #define CLK_MM_DISP_DSC 31 |
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| 246 | #define CLK_MM_DISP_SPLIT 32 |
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| 247 | #define CLK_MM_DSI0_MM_CLOCK 33 |
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| 248 | #define CLK_MM_DSI1_MM_CLOCK 34 |
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| 249 | #define CLK_MM_DPI_MM_CLOCK 35 |
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| 250 | #define CLK_MM_DPI_INTERFACE_CLOCK 36 |
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| 251 | #define CLK_MM_LARB4_AXI_ASIF_MM_CLOCK 37 |
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| 252 | #define CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK 38 |
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| 253 | #define CLK_MM_DISP_OVL0_MOUT_CLOCK 39 |
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| 254 | #define CLK_MM_FAKE_ENG2 40 |
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| 255 | #define CLK_MM_DSI0_INTERFACE_CLOCK 41 |
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| 256 | #define CLK_MM_DSI1_INTERFACE_CLOCK 42 |
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| 257 | #define CLK_MM_NR 43 |
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| 258 | |
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| 259 | /* VDEC_SYS */ |
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| 260 | #define CLK_VDEC_CKEN_ENG 1 |
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| 261 | #define CLK_VDEC_ACTIVE 2 |
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| 262 | #define CLK_VDEC_CKEN 3 |
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| 263 | #define CLK_VDEC_LARB1_CKEN 4 |
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| 264 | #define CLK_VDEC_NR 5 |
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| 265 | |
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| 266 | /* VENC_SYS */ |
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| 267 | #define CLK_VENC_0 1 |
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| 268 | #define CLK_VENC_1 2 |
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| 269 | #define CLK_VENC_2 3 |
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| 270 | #define CLK_VENC_3 4 |
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| 271 | #define CLK_VENC_NR 5 |
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| 272 | |
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| 273 | #endif /* _DT_BINDINGS_CLK_MT6797_H */ |
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| 274 | |
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