| 1 | /* SPDX-License-Identifier: GPL-2.0+ |
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| 2 | * |
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| 3 | * Copyright (C) 2020 Renesas Electronics Corp. |
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| 4 | */ |
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| 5 | #ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ |
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| 6 | #define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ |
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| 7 | |
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| 8 | #include <dt-bindings/clock/renesas-cpg-mssr.h> |
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| 9 | |
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| 10 | /* r8a7742 CPG Core Clocks */ |
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| 11 | #define R8A7742_CLK_Z 0 |
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| 12 | #define R8A7742_CLK_Z2 1 |
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| 13 | #define R8A7742_CLK_ZG 2 |
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| 14 | #define R8A7742_CLK_ZTR 3 |
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| 15 | #define R8A7742_CLK_ZTRD2 4 |
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| 16 | #define R8A7742_CLK_ZT 5 |
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| 17 | #define R8A7742_CLK_ZX 6 |
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| 18 | #define R8A7742_CLK_ZS 7 |
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| 19 | #define R8A7742_CLK_HP 8 |
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| 20 | #define R8A7742_CLK_B 9 |
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| 21 | #define R8A7742_CLK_LB 10 |
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| 22 | #define R8A7742_CLK_P 11 |
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| 23 | #define R8A7742_CLK_CL 12 |
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| 24 | #define R8A7742_CLK_M2 13 |
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| 25 | #define R8A7742_CLK_ZB3 14 |
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| 26 | #define R8A7742_CLK_ZB3D2 15 |
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| 27 | #define R8A7742_CLK_DDR 16 |
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| 28 | #define R8A7742_CLK_SDH 17 |
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| 29 | #define R8A7742_CLK_SD0 18 |
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| 30 | #define R8A7742_CLK_SD1 19 |
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| 31 | #define R8A7742_CLK_SD2 20 |
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| 32 | #define R8A7742_CLK_SD3 21 |
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| 33 | #define R8A7742_CLK_MMC0 22 |
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| 34 | #define R8A7742_CLK_MMC1 23 |
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| 35 | #define R8A7742_CLK_MP 24 |
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| 36 | #define R8A7742_CLK_QSPI 25 |
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| 37 | #define R8A7742_CLK_CP 26 |
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| 38 | #define R8A7742_CLK_RCAN 27 |
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| 39 | #define R8A7742_CLK_R 28 |
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| 40 | #define R8A7742_CLK_OSC 29 |
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| 41 | |
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| 42 | #endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */ |
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| 43 | |
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