1/* SPDX-License-Identifier: GPL-2.0+
2 *
3 * Copyright (C) 2016 Renesas Electronics Corp.
4 */
5#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
6#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>
9
10/* r8a7796 CPG Core Clocks */
11#define R8A7796_CLK_Z 0
12#define R8A7796_CLK_Z2 1
13#define R8A7796_CLK_ZR 2
14#define R8A7796_CLK_ZG 3
15#define R8A7796_CLK_ZTR 4
16#define R8A7796_CLK_ZTRD2 5
17#define R8A7796_CLK_ZT 6
18#define R8A7796_CLK_ZX 7
19#define R8A7796_CLK_S0D1 8
20#define R8A7796_CLK_S0D2 9
21#define R8A7796_CLK_S0D3 10
22#define R8A7796_CLK_S0D4 11
23#define R8A7796_CLK_S0D6 12
24#define R8A7796_CLK_S0D8 13
25#define R8A7796_CLK_S0D12 14
26#define R8A7796_CLK_S1D1 15
27#define R8A7796_CLK_S1D2 16
28#define R8A7796_CLK_S1D4 17
29#define R8A7796_CLK_S2D1 18
30#define R8A7796_CLK_S2D2 19
31#define R8A7796_CLK_S2D4 20
32#define R8A7796_CLK_S3D1 21
33#define R8A7796_CLK_S3D2 22
34#define R8A7796_CLK_S3D4 23
35#define R8A7796_CLK_LB 24
36#define R8A7796_CLK_CL 25
37#define R8A7796_CLK_ZB3 26
38#define R8A7796_CLK_ZB3D2 27
39#define R8A7796_CLK_ZB3D4 28
40#define R8A7796_CLK_CR 29
41#define R8A7796_CLK_CRD2 30
42#define R8A7796_CLK_SD0H 31
43#define R8A7796_CLK_SD0 32
44#define R8A7796_CLK_SD1H 33
45#define R8A7796_CLK_SD1 34
46#define R8A7796_CLK_SD2H 35
47#define R8A7796_CLK_SD2 36
48#define R8A7796_CLK_SD3H 37
49#define R8A7796_CLK_SD3 38
50#define R8A7796_CLK_SSP2 39
51#define R8A7796_CLK_SSP1 40
52#define R8A7796_CLK_SSPRS 41
53#define R8A7796_CLK_RPC 42
54#define R8A7796_CLK_RPCD2 43
55#define R8A7796_CLK_MSO 44
56#define R8A7796_CLK_CANFD 45
57#define R8A7796_CLK_HDMI 46
58#define R8A7796_CLK_CSI0 47
59/* CLK_CSIREF was removed */
60#define R8A7796_CLK_CP 49
61#define R8A7796_CLK_CPEX 50
62#define R8A7796_CLK_R 51
63#define R8A7796_CLK_OSC 52
64
65#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */
66

source code of linux/include/dt-bindings/clock/r8a7796-cpg-mssr.h