| 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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| 2 | // |
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| 3 | // Spreadtrum SC9860 platform clocks |
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| 4 | // |
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| 5 | // Copyright (C) 2017, Spreadtrum Communications Inc. |
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| 6 | |
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| 7 | #ifndef _DT_BINDINGS_CLK_SC9860_H_ |
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| 8 | #define _DT_BINDINGS_CLK_SC9860_H_ |
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| 9 | |
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| 10 | #define CLK_FAC_4M 0 |
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| 11 | #define CLK_FAC_2M 1 |
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| 12 | #define CLK_FAC_1M 2 |
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| 13 | #define CLK_FAC_250K 3 |
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| 14 | #define CLK_FAC_RPLL0_26M 4 |
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| 15 | #define CLK_FAC_RPLL1_26M 5 |
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| 16 | #define CLK_FAC_RCO25M 6 |
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| 17 | #define CLK_FAC_RCO4M 7 |
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| 18 | #define CLK_FAC_RCO2M 8 |
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| 19 | #define CLK_FAC_3K2 9 |
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| 20 | #define CLK_FAC_1K 10 |
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| 21 | #define CLK_MPLL0_GATE 11 |
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| 22 | #define CLK_MPLL1_GATE 12 |
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| 23 | #define CLK_DPLL0_GATE 13 |
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| 24 | #define CLK_DPLL1_GATE 14 |
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| 25 | #define CLK_LTEPLL0_GATE 15 |
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| 26 | #define CLK_TWPLL_GATE 16 |
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| 27 | #define CLK_LTEPLL1_GATE 17 |
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| 28 | #define CLK_RPLL0_GATE 18 |
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| 29 | #define CLK_RPLL1_GATE 19 |
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| 30 | #define CLK_CPPLL_GATE 20 |
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| 31 | #define CLK_GPLL_GATE 21 |
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| 32 | #define CLK_PMU_GATE_NUM (CLK_GPLL_GATE + 1) |
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| 33 | |
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| 34 | #define CLK_MPLL0 0 |
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| 35 | #define CLK_MPLL1 1 |
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| 36 | #define CLK_DPLL0 2 |
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| 37 | #define CLK_DPLL1 3 |
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| 38 | #define CLK_RPLL0 4 |
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| 39 | #define CLK_RPLL1 5 |
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| 40 | #define CLK_TWPLL 6 |
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| 41 | #define CLK_LTEPLL0 7 |
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| 42 | #define CLK_LTEPLL1 8 |
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| 43 | #define CLK_GPLL 9 |
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| 44 | #define CLK_CPPLL 10 |
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| 45 | #define CLK_GPLL_42M5 11 |
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| 46 | #define CLK_TWPLL_768M 12 |
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| 47 | #define CLK_TWPLL_384M 13 |
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| 48 | #define CLK_TWPLL_192M 14 |
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| 49 | #define CLK_TWPLL_96M 15 |
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| 50 | #define CLK_TWPLL_48M 16 |
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| 51 | #define CLK_TWPLL_24M 17 |
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| 52 | #define CLK_TWPLL_12M 18 |
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| 53 | #define CLK_TWPLL_512M 19 |
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| 54 | #define CLK_TWPLL_256M 20 |
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| 55 | #define CLK_TWPLL_128M 21 |
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| 56 | #define CLK_TWPLL_64M 22 |
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| 57 | #define CLK_TWPLL_307M2 23 |
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| 58 | #define CLK_TWPLL_153M6 24 |
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| 59 | #define CLK_TWPLL_76M8 25 |
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| 60 | #define CLK_TWPLL_51M2 26 |
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| 61 | #define CLK_TWPLL_38M4 27 |
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| 62 | #define CLK_TWPLL_19M2 28 |
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| 63 | #define CLK_L0_614M4 29 |
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| 64 | #define CLK_L0_409M6 30 |
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| 65 | #define CLK_L0_38M 31 |
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| 66 | #define CLK_L1_38M 32 |
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| 67 | #define CLK_RPLL0_192M 33 |
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| 68 | #define CLK_RPLL0_96M 34 |
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| 69 | #define CLK_RPLL0_48M 35 |
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| 70 | #define CLK_RPLL1_468M 36 |
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| 71 | #define CLK_RPLL1_192M 37 |
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| 72 | #define CLK_RPLL1_96M 38 |
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| 73 | #define CLK_RPLL1_64M 39 |
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| 74 | #define CLK_RPLL1_48M 40 |
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| 75 | #define CLK_DPLL0_50M 41 |
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| 76 | #define CLK_DPLL1_50M 42 |
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| 77 | #define CLK_CPPLL_50M 43 |
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| 78 | #define CLK_M0_39M 44 |
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| 79 | #define CLK_M1_63M 45 |
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| 80 | #define CLK_PLL_NUM (CLK_M1_63M + 1) |
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| 81 | |
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| 82 | |
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| 83 | #define CLK_AP_APB 0 |
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| 84 | #define CLK_AP_USB3 1 |
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| 85 | #define CLK_UART0 2 |
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| 86 | #define CLK_UART1 3 |
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| 87 | #define CLK_UART2 4 |
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| 88 | #define CLK_UART3 5 |
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| 89 | #define CLK_UART4 6 |
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| 90 | #define CLK_I2C0 7 |
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| 91 | #define CLK_I2C1 8 |
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| 92 | #define CLK_I2C2 9 |
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| 93 | #define CLK_I2C3 10 |
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| 94 | #define CLK_I2C4 11 |
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| 95 | #define CLK_I2C5 12 |
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| 96 | #define CLK_SPI0 13 |
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| 97 | #define CLK_SPI1 14 |
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| 98 | #define CLK_SPI2 15 |
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| 99 | #define CLK_SPI3 16 |
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| 100 | #define CLK_IIS0 17 |
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| 101 | #define CLK_IIS1 18 |
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| 102 | #define CLK_IIS2 19 |
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| 103 | #define CLK_IIS3 20 |
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| 104 | #define CLK_AP_CLK_NUM (CLK_IIS3 + 1) |
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| 105 | |
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| 106 | #define CLK_AON_APB 0 |
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| 107 | #define CLK_AUX0 1 |
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| 108 | #define CLK_AUX1 2 |
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| 109 | #define CLK_AUX2 3 |
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| 110 | #define CLK_PROBE 4 |
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| 111 | #define CLK_SP_AHB 5 |
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| 112 | #define CLK_CCI 6 |
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| 113 | #define CLK_GIC 7 |
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| 114 | #define CLK_CSSYS 8 |
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| 115 | #define CLK_SDIO0_2X 9 |
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| 116 | #define CLK_SDIO1_2X 10 |
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| 117 | #define CLK_SDIO2_2X 11 |
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| 118 | #define CLK_EMMC_2X 12 |
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| 119 | #define CLK_SDIO0_1X 13 |
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| 120 | #define CLK_SDIO1_1X 14 |
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| 121 | #define CLK_SDIO2_1X 15 |
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| 122 | #define CLK_EMMC_1X 16 |
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| 123 | #define CLK_ADI 17 |
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| 124 | #define CLK_PWM0 18 |
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| 125 | #define CLK_PWM1 19 |
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| 126 | #define CLK_PWM2 20 |
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| 127 | #define CLK_PWM3 21 |
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| 128 | #define CLK_EFUSE 22 |
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| 129 | #define CLK_CM3_UART0 23 |
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| 130 | #define CLK_CM3_UART1 24 |
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| 131 | #define CLK_THM 25 |
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| 132 | #define CLK_CM3_I2C0 26 |
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| 133 | #define CLK_CM3_I2C1 27 |
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| 134 | #define CLK_CM4_SPI 28 |
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| 135 | #define CLK_AON_I2C 29 |
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| 136 | #define CLK_AVS 30 |
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| 137 | #define CLK_CA53_DAP 31 |
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| 138 | #define CLK_CA53_TS 32 |
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| 139 | #define CLK_DJTAG_TCK 33 |
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| 140 | #define CLK_PMU 34 |
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| 141 | #define CLK_PMU_26M 35 |
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| 142 | #define CLK_DEBOUNCE 36 |
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| 143 | #define CLK_OTG2_REF 37 |
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| 144 | #define CLK_USB3_REF 38 |
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| 145 | #define CLK_AP_AXI 39 |
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| 146 | #define CLK_AON_PREDIV_NUM (CLK_AP_AXI + 1) |
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| 147 | |
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| 148 | #define CLK_USB3_EB 0 |
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| 149 | #define CLK_USB3_SUSPEND_EB 1 |
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| 150 | #define CLK_USB3_REF_EB 2 |
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| 151 | #define CLK_DMA_EB 3 |
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| 152 | #define CLK_SDIO0_EB 4 |
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| 153 | #define CLK_SDIO1_EB 5 |
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| 154 | #define CLK_SDIO2_EB 6 |
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| 155 | #define CLK_EMMC_EB 7 |
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| 156 | #define CLK_ROM_EB 8 |
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| 157 | #define CLK_BUSMON_EB 9 |
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| 158 | #define CLK_CC63S_EB 10 |
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| 159 | #define CLK_CC63P_EB 11 |
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| 160 | #define CLK_CE0_EB 12 |
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| 161 | #define CLK_CE1_EB 13 |
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| 162 | #define CLK_APAHB_GATE_NUM (CLK_CE1_EB + 1) |
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| 163 | |
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| 164 | #define CLK_AVS_LIT_EB 0 |
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| 165 | #define CLK_AVS_BIG_EB 1 |
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| 166 | #define CLK_AP_INTC5_EB 2 |
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| 167 | #define CLK_GPIO_EB 3 |
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| 168 | #define CLK_PWM0_EB 4 |
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| 169 | #define CLK_PWM1_EB 5 |
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| 170 | #define CLK_PWM2_EB 6 |
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| 171 | #define CLK_PWM3_EB 7 |
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| 172 | #define CLK_KPD_EB 8 |
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| 173 | #define CLK_AON_SYS_EB 9 |
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| 174 | #define CLK_AP_SYS_EB 10 |
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| 175 | #define CLK_AON_TMR_EB 11 |
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| 176 | #define CLK_AP_TMR0_EB 12 |
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| 177 | #define CLK_EFUSE_EB 13 |
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| 178 | #define CLK_EIC_EB 14 |
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| 179 | #define CLK_PUB1_REG_EB 15 |
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| 180 | #define CLK_ADI_EB 16 |
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| 181 | #define CLK_AP_INTC0_EB 17 |
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| 182 | #define CLK_AP_INTC1_EB 18 |
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| 183 | #define CLK_AP_INTC2_EB 19 |
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| 184 | #define CLK_AP_INTC3_EB 20 |
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| 185 | #define CLK_AP_INTC4_EB 21 |
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| 186 | #define CLK_SPLK_EB 22 |
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| 187 | #define CLK_MSPI_EB 23 |
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| 188 | #define CLK_PUB0_REG_EB 24 |
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| 189 | #define CLK_PIN_EB 25 |
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| 190 | #define CLK_AON_CKG_EB 26 |
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| 191 | #define CLK_GPU_EB 27 |
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| 192 | #define CLK_APCPU_TS0_EB 28 |
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| 193 | #define CLK_APCPU_TS1_EB 29 |
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| 194 | #define CLK_DAP_EB 30 |
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| 195 | #define CLK_I2C_EB 31 |
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| 196 | #define CLK_PMU_EB 32 |
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| 197 | #define CLK_THM_EB 33 |
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| 198 | #define CLK_AUX0_EB 34 |
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| 199 | #define CLK_AUX1_EB 35 |
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| 200 | #define CLK_AUX2_EB 36 |
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| 201 | #define CLK_PROBE_EB 37 |
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| 202 | #define CLK_GPU0_AVS_EB 38 |
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| 203 | #define CLK_GPU1_AVS_EB 39 |
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| 204 | #define CLK_APCPU_WDG_EB 40 |
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| 205 | #define CLK_AP_TMR1_EB 41 |
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| 206 | #define CLK_AP_TMR2_EB 42 |
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| 207 | #define CLK_DISP_EMC_EB 43 |
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| 208 | #define CLK_ZIP_EMC_EB 44 |
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| 209 | #define CLK_GSP_EMC_EB 45 |
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| 210 | #define CLK_OSC_AON_EB 46 |
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| 211 | #define CLK_LVDS_TRX_EB 47 |
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| 212 | #define CLK_LVDS_TCXO_EB 48 |
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| 213 | #define CLK_MDAR_EB 49 |
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| 214 | #define CLK_RTC4M0_CAL_EB 50 |
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| 215 | #define CLK_RCT100M_CAL_EB 51 |
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| 216 | #define CLK_DJTAG_EB 52 |
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| 217 | #define CLK_MBOX_EB 53 |
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| 218 | #define CLK_AON_DMA_EB 54 |
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| 219 | #define CLK_DBG_EMC_EB 55 |
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| 220 | #define CLK_LVDS_PLL_DIV_EN 56 |
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| 221 | #define CLK_DEF_EB 57 |
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| 222 | #define CLK_AON_APB_RSV0 58 |
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| 223 | #define CLK_ORP_JTAG_EB 59 |
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| 224 | #define CLK_VSP_EB 60 |
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| 225 | #define CLK_CAM_EB 61 |
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| 226 | #define CLK_DISP_EB 62 |
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| 227 | #define CLK_DBG_AXI_IF_EB 63 |
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| 228 | #define CLK_SDIO0_2X_EN 64 |
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| 229 | #define CLK_SDIO1_2X_EN 65 |
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| 230 | #define CLK_SDIO2_2X_EN 66 |
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| 231 | #define CLK_EMMC_2X_EN 67 |
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| 232 | #define CLK_ARCH_RTC_EB 68 |
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| 233 | #define CLK_KPB_RTC_EB 69 |
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| 234 | #define CLK_AON_SYST_RTC_EB 70 |
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| 235 | #define CLK_AP_SYST_RTC_EB 71 |
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| 236 | #define CLK_AON_TMR_RTC_EB 72 |
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| 237 | #define CLK_AP_TMR0_RTC_EB 73 |
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| 238 | #define CLK_EIC_RTC_EB 74 |
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| 239 | #define CLK_EIC_RTCDV5_EB 75 |
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| 240 | #define CLK_AP_WDG_RTC_EB 76 |
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| 241 | #define CLK_AP_TMR1_RTC_EB 77 |
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| 242 | #define CLK_AP_TMR2_RTC_EB 78 |
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| 243 | #define CLK_DCXO_TMR_RTC_EB 79 |
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| 244 | #define CLK_BB_CAL_RTC_EB 80 |
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| 245 | #define CLK_AVS_BIG_RTC_EB 81 |
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| 246 | #define CLK_AVS_LIT_RTC_EB 82 |
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| 247 | #define CLK_AVS_GPU0_RTC_EB 83 |
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| 248 | #define CLK_AVS_GPU1_RTC_EB 84 |
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| 249 | #define CLK_GPU_TS_EB 85 |
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| 250 | #define CLK_RTCDV10_EB 86 |
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| 251 | #define CLK_AON_GATE_NUM (CLK_RTCDV10_EB + 1) |
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| 252 | |
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| 253 | #define CLK_LIT_MCU 0 |
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| 254 | #define CLK_BIG_MCU 1 |
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| 255 | #define CLK_AONSECURE_NUM (CLK_BIG_MCU + 1) |
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| 256 | |
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| 257 | #define CLK_AGCP_IIS0_EB 0 |
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| 258 | #define CLK_AGCP_IIS1_EB 1 |
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| 259 | #define CLK_AGCP_IIS2_EB 2 |
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| 260 | #define CLK_AGCP_IIS3_EB 3 |
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| 261 | #define CLK_AGCP_UART_EB 4 |
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| 262 | #define CLK_AGCP_DMACP_EB 5 |
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| 263 | #define CLK_AGCP_DMAAP_EB 6 |
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| 264 | #define CLK_AGCP_ARC48K_EB 7 |
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| 265 | #define CLK_AGCP_SRC44P1K_EB 8 |
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| 266 | #define CLK_AGCP_MCDT_EB 9 |
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| 267 | #define CLK_AGCP_VBCIFD_EB 10 |
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| 268 | #define CLK_AGCP_VBC_EB 11 |
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| 269 | #define CLK_AGCP_SPINLOCK_EB 12 |
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| 270 | #define CLK_AGCP_ICU_EB 13 |
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| 271 | #define CLK_AGCP_AP_ASHB_EB 14 |
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| 272 | #define CLK_AGCP_CP_ASHB_EB 15 |
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| 273 | #define CLK_AGCP_AUD_EB 16 |
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| 274 | #define CLK_AGCP_AUDIF_EB 17 |
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| 275 | #define CLK_AGCP_GATE_NUM (CLK_AGCP_AUDIF_EB + 1) |
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| 276 | |
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| 277 | #define CLK_GPU 0 |
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| 278 | #define CLK_GPU_NUM (CLK_GPU + 1) |
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| 279 | |
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| 280 | #define CLK_AHB_VSP 0 |
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| 281 | #define CLK_VSP 1 |
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| 282 | #define CLK_VSP_ENC 2 |
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| 283 | #define CLK_VPP 3 |
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| 284 | #define CLK_VSP_26M 4 |
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| 285 | #define CLK_VSP_NUM (CLK_VSP_26M + 1) |
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| 286 | |
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| 287 | #define CLK_VSP_DEC_EB 0 |
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| 288 | #define CLK_VSP_CKG_EB 1 |
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| 289 | #define CLK_VSP_MMU_EB 2 |
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| 290 | #define CLK_VSP_ENC_EB 3 |
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| 291 | #define CLK_VPP_EB 4 |
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| 292 | #define CLK_VSP_26M_EB 5 |
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| 293 | #define CLK_VSP_AXI_GATE 6 |
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| 294 | #define CLK_VSP_ENC_GATE 7 |
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| 295 | #define CLK_VPP_AXI_GATE 8 |
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| 296 | #define CLK_VSP_BM_GATE 9 |
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| 297 | #define CLK_VSP_ENC_BM_GATE 10 |
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| 298 | #define CLK_VPP_BM_GATE 11 |
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| 299 | #define CLK_VSP_GATE_NUM (CLK_VPP_BM_GATE + 1) |
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| 300 | |
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| 301 | #define CLK_AHB_CAM 0 |
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| 302 | #define CLK_SENSOR0 1 |
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| 303 | #define CLK_SENSOR1 2 |
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| 304 | #define CLK_SENSOR2 3 |
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| 305 | #define CLK_MIPI_CSI0_EB 4 |
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| 306 | #define CLK_MIPI_CSI1_EB 5 |
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| 307 | #define CLK_CAM_NUM (CLK_MIPI_CSI1_EB + 1) |
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| 308 | |
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| 309 | #define CLK_DCAM0_EB 0 |
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| 310 | #define CLK_DCAM1_EB 1 |
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| 311 | #define CLK_ISP0_EB 2 |
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| 312 | #define CLK_CSI0_EB 3 |
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| 313 | #define CLK_CSI1_EB 4 |
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| 314 | #define CLK_JPG0_EB 5 |
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| 315 | #define CLK_JPG1_EB 6 |
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| 316 | #define CLK_CAM_CKG_EB 7 |
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| 317 | #define CLK_CAM_MMU_EB 8 |
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| 318 | #define CLK_ISP1_EB 9 |
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| 319 | #define CLK_CPP_EB 10 |
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| 320 | #define CLK_MMU_PF_EB 11 |
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| 321 | #define CLK_ISP2_EB 12 |
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| 322 | #define CLK_DCAM2ISP_IF_EB 13 |
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| 323 | #define CLK_ISP2DCAM_IF_EB 14 |
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| 324 | #define CLK_ISP_LCLK_EB 15 |
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| 325 | #define CLK_ISP_ICLK_EB 16 |
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| 326 | #define CLK_ISP_MCLK_EB 17 |
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| 327 | #define CLK_ISP_PCLK_EB 18 |
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| 328 | #define CLK_ISP_ISP2DCAM_EB 19 |
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| 329 | #define CLK_DCAM0_IF_EB 20 |
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| 330 | #define CLK_CLK26M_IF_EB 21 |
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| 331 | #define CLK_CPHY0_GATE 22 |
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| 332 | #define CLK_MIPI_CSI0_GATE 23 |
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| 333 | #define CLK_CPHY1_GATE 24 |
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| 334 | #define CLK_MIPI_CSI1 25 |
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| 335 | #define CLK_DCAM0_AXI_GATE 26 |
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| 336 | #define CLK_DCAM1_AXI_GATE 27 |
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| 337 | #define CLK_SENSOR0_GATE 28 |
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| 338 | #define CLK_SENSOR1_GATE 29 |
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| 339 | #define CLK_JPG0_AXI_GATE 30 |
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| 340 | #define CLK_GPG1_AXI_GATE 31 |
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| 341 | #define CLK_ISP0_AXI_GATE 32 |
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| 342 | #define CLK_ISP1_AXI_GATE 33 |
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| 343 | #define CLK_ISP2_AXI_GATE 34 |
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| 344 | #define CLK_CPP_AXI_GATE 35 |
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| 345 | #define CLK_D0_IF_AXI_GATE 36 |
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| 346 | #define CLK_D2I_IF_AXI_GATE 37 |
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| 347 | #define CLK_I2D_IF_AXI_GATE 38 |
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| 348 | #define CLK_SPARE_AXI_GATE 39 |
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| 349 | #define CLK_SENSOR2_GATE 40 |
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| 350 | #define CLK_D0IF_IN_D_EN 41 |
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| 351 | #define CLK_D1IF_IN_D_EN 42 |
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| 352 | #define CLK_D0IF_IN_D2I_EN 43 |
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| 353 | #define CLK_D1IF_IN_D2I_EN 44 |
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| 354 | #define CLK_IA_IN_D2I_EN 45 |
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| 355 | #define CLK_IB_IN_D2I_EN 46 |
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| 356 | #define CLK_IC_IN_D2I_EN 47 |
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| 357 | #define CLK_IA_IN_I_EN 48 |
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| 358 | #define CLK_IB_IN_I_EN 49 |
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| 359 | #define CLK_IC_IN_I_EN 50 |
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| 360 | #define CLK_CAM_GATE_NUM (CLK_IC_IN_I_EN + 1) |
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| 361 | |
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| 362 | #define CLK_AHB_DISP 0 |
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| 363 | #define CLK_DISPC0_DPI 1 |
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| 364 | #define CLK_DISPC1_DPI 2 |
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| 365 | #define CLK_DISP_NUM (CLK_DISPC1_DPI + 1) |
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| 366 | |
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| 367 | #define CLK_DISPC0_EB 0 |
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| 368 | #define CLK_DISPC1_EB 1 |
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| 369 | #define CLK_DISPC_MMU_EB 2 |
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| 370 | #define CLK_GSP0_EB 3 |
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| 371 | #define CLK_GSP1_EB 4 |
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| 372 | #define CLK_GSP0_MMU_EB 5 |
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| 373 | #define CLK_GSP1_MMU_EB 6 |
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| 374 | #define CLK_DSI0_EB 7 |
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| 375 | #define CLK_DSI1_EB 8 |
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| 376 | #define CLK_DISP_CKG_EB 9 |
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| 377 | #define CLK_DISP_GPU_EB 10 |
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| 378 | #define CLK_GPU_MTX_EB 11 |
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| 379 | #define CLK_GSP_MTX_EB 12 |
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| 380 | #define CLK_TMC_MTX_EB 13 |
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| 381 | #define CLK_DISPC_MTX_EB 14 |
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| 382 | #define CLK_DPHY0_GATE 15 |
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| 383 | #define CLK_DPHY1_GATE 16 |
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| 384 | #define CLK_GSP0_A_GATE 17 |
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| 385 | #define CLK_GSP1_A_GATE 18 |
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| 386 | #define CLK_GSP0_F_GATE 19 |
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| 387 | #define CLK_GSP1_F_GATE 20 |
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| 388 | #define CLK_D_MTX_F_GATE 21 |
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| 389 | #define CLK_D_MTX_A_GATE 22 |
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| 390 | #define CLK_D_NOC_F_GATE 23 |
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| 391 | #define CLK_D_NOC_A_GATE 24 |
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| 392 | #define CLK_GSP_MTX_F_GATE 25 |
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| 393 | #define CLK_GSP_MTX_A_GATE 26 |
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| 394 | #define CLK_GSP_NOC_F_GATE 27 |
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| 395 | #define CLK_GSP_NOC_A_GATE 28 |
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| 396 | #define CLK_DISPM0IDLE_GATE 29 |
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| 397 | #define CLK_GSPM0IDLE_GATE 30 |
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| 398 | #define CLK_DISP_GATE_NUM (CLK_GSPM0IDLE_GATE + 1) |
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| 399 | |
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| 400 | #define CLK_SIM0_EB 0 |
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| 401 | #define CLK_IIS0_EB 1 |
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| 402 | #define CLK_IIS1_EB 2 |
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| 403 | #define CLK_IIS2_EB 3 |
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| 404 | #define CLK_IIS3_EB 4 |
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| 405 | #define CLK_SPI0_EB 5 |
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| 406 | #define CLK_SPI1_EB 6 |
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| 407 | #define CLK_SPI2_EB 7 |
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| 408 | #define CLK_I2C0_EB 8 |
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| 409 | #define CLK_I2C1_EB 9 |
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| 410 | #define CLK_I2C2_EB 10 |
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| 411 | #define CLK_I2C3_EB 11 |
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| 412 | #define CLK_I2C4_EB 12 |
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| 413 | #define CLK_I2C5_EB 13 |
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| 414 | #define CLK_UART0_EB 14 |
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| 415 | #define CLK_UART1_EB 15 |
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| 416 | #define CLK_UART2_EB 16 |
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| 417 | #define CLK_UART3_EB 17 |
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| 418 | #define CLK_UART4_EB 18 |
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| 419 | #define CLK_AP_CKG_EB 19 |
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| 420 | #define CLK_SPI3_EB 20 |
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| 421 | #define CLK_APAPB_GATE_NUM (CLK_SPI3_EB + 1) |
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| 422 | |
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| 423 | #endif /* _DT_BINDINGS_CLK_SC9860_H_ */ |
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| 424 | |
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