1 | /* |
2 | * Copyright (C) 2017 Priit Laes <plaes@plaes.org> |
3 | * |
4 | * This file is dual-licensed: you can use it either under the terms |
5 | * of the GPL or the X11 license, at your option. Note that this dual |
6 | * licensing only applies to this file, and not this project as a |
7 | * whole. |
8 | * |
9 | * a) This file is free software; you can redistribute it and/or |
10 | * modify it under the terms of the GNU General Public License as |
11 | * published by the Free Software Foundation; either version 2 of the |
12 | * License, or (at your option) any later version. |
13 | * |
14 | * This file is distributed in the hope that it will be useful, |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
17 | * GNU General Public License for more details. |
18 | * |
19 | * Or, alternatively, |
20 | * |
21 | * b) Permission is hereby granted, free of charge, to any person |
22 | * obtaining a copy of this software and associated documentation |
23 | * files (the "Software"), to deal in the Software without |
24 | * restriction, including without limitation the rights to use, |
25 | * copy, modify, merge, publish, distribute, sublicense, and/or |
26 | * sell copies of the Software, and to permit persons to whom the |
27 | * Software is furnished to do so, subject to the following |
28 | * conditions: |
29 | * |
30 | * The above copyright notice and this permission notice shall be |
31 | * included in all copies or substantial portions of the Software. |
32 | * |
33 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
34 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
35 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
36 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
37 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
38 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
39 | * OTHER DEALINGS IN THE SOFTWARE. |
40 | */ |
41 | |
42 | #ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_ |
43 | #define _DT_BINDINGS_CLK_SUN4I_A10_H_ |
44 | |
45 | #define CLK_HOSC 1 |
46 | #define CLK_PLL_VIDEO0_2X 9 |
47 | #define CLK_PLL_VIDEO1_2X 18 |
48 | #define CLK_CPU 20 |
49 | |
50 | /* AHB Gates */ |
51 | #define CLK_AHB_OTG 26 |
52 | #define CLK_AHB_EHCI0 27 |
53 | #define CLK_AHB_OHCI0 28 |
54 | #define CLK_AHB_EHCI1 29 |
55 | #define CLK_AHB_OHCI1 30 |
56 | #define CLK_AHB_SS 31 |
57 | #define CLK_AHB_DMA 32 |
58 | #define CLK_AHB_BIST 33 |
59 | #define CLK_AHB_MMC0 34 |
60 | #define CLK_AHB_MMC1 35 |
61 | #define CLK_AHB_MMC2 36 |
62 | #define CLK_AHB_MMC3 37 |
63 | #define CLK_AHB_MS 38 |
64 | #define CLK_AHB_NAND 39 |
65 | #define CLK_AHB_SDRAM 40 |
66 | #define CLK_AHB_ACE 41 |
67 | #define CLK_AHB_EMAC 42 |
68 | #define CLK_AHB_TS 43 |
69 | #define CLK_AHB_SPI0 44 |
70 | #define CLK_AHB_SPI1 45 |
71 | #define CLK_AHB_SPI2 46 |
72 | #define CLK_AHB_SPI3 47 |
73 | #define CLK_AHB_PATA 48 |
74 | #define CLK_AHB_SATA 49 |
75 | #define CLK_AHB_GPS 50 |
76 | #define CLK_AHB_HSTIMER 51 |
77 | #define CLK_AHB_VE 52 |
78 | #define CLK_AHB_TVD 53 |
79 | #define CLK_AHB_TVE0 54 |
80 | #define CLK_AHB_TVE1 55 |
81 | #define CLK_AHB_LCD0 56 |
82 | #define CLK_AHB_LCD1 57 |
83 | #define CLK_AHB_CSI0 58 |
84 | #define CLK_AHB_CSI1 59 |
85 | #define CLK_AHB_HDMI0 60 |
86 | #define CLK_AHB_HDMI1 61 |
87 | #define CLK_AHB_DE_BE0 62 |
88 | #define CLK_AHB_DE_BE1 63 |
89 | #define CLK_AHB_DE_FE0 64 |
90 | #define CLK_AHB_DE_FE1 65 |
91 | #define CLK_AHB_GMAC 66 |
92 | #define CLK_AHB_MP 67 |
93 | #define CLK_AHB_GPU 68 |
94 | |
95 | /* APB0 Gates */ |
96 | #define CLK_APB0_CODEC 69 |
97 | #define CLK_APB0_SPDIF 70 |
98 | #define CLK_APB0_I2S0 71 |
99 | #define CLK_APB0_AC97 72 |
100 | #define CLK_APB0_I2S1 73 |
101 | #define CLK_APB0_PIO 74 |
102 | #define CLK_APB0_IR0 75 |
103 | #define CLK_APB0_IR1 76 |
104 | #define CLK_APB0_I2S2 77 |
105 | #define CLK_APB0_KEYPAD 78 |
106 | |
107 | /* APB1 Gates */ |
108 | #define CLK_APB1_I2C0 79 |
109 | #define CLK_APB1_I2C1 80 |
110 | #define CLK_APB1_I2C2 81 |
111 | #define CLK_APB1_I2C3 82 |
112 | #define CLK_APB1_CAN 83 |
113 | #define CLK_APB1_SCR 84 |
114 | #define CLK_APB1_PS20 85 |
115 | #define CLK_APB1_PS21 86 |
116 | #define CLK_APB1_I2C4 87 |
117 | #define CLK_APB1_UART0 88 |
118 | #define CLK_APB1_UART1 89 |
119 | #define CLK_APB1_UART2 90 |
120 | #define CLK_APB1_UART3 91 |
121 | #define CLK_APB1_UART4 92 |
122 | #define CLK_APB1_UART5 93 |
123 | #define CLK_APB1_UART6 94 |
124 | #define CLK_APB1_UART7 95 |
125 | |
126 | /* IP clocks */ |
127 | #define CLK_NAND 96 |
128 | #define CLK_MS 97 |
129 | #define CLK_MMC0 98 |
130 | #define CLK_MMC0_OUTPUT 99 |
131 | #define CLK_MMC0_SAMPLE 100 |
132 | #define CLK_MMC1 101 |
133 | #define CLK_MMC1_OUTPUT 102 |
134 | #define CLK_MMC1_SAMPLE 103 |
135 | #define CLK_MMC2 104 |
136 | #define CLK_MMC2_OUTPUT 105 |
137 | #define CLK_MMC2_SAMPLE 106 |
138 | #define CLK_MMC3 107 |
139 | #define CLK_MMC3_OUTPUT 108 |
140 | #define CLK_MMC3_SAMPLE 109 |
141 | #define CLK_TS 110 |
142 | #define CLK_SS 111 |
143 | #define CLK_SPI0 112 |
144 | #define CLK_SPI1 113 |
145 | #define CLK_SPI2 114 |
146 | #define CLK_PATA 115 |
147 | #define CLK_IR0 116 |
148 | #define CLK_IR1 117 |
149 | #define CLK_I2S0 118 |
150 | #define CLK_AC97 119 |
151 | #define CLK_SPDIF 120 |
152 | #define CLK_KEYPAD 121 |
153 | #define CLK_SATA 122 |
154 | #define CLK_USB_OHCI0 123 |
155 | #define CLK_USB_OHCI1 124 |
156 | #define CLK_USB_PHY 125 |
157 | #define CLK_GPS 126 |
158 | #define CLK_SPI3 127 |
159 | #define CLK_I2S1 128 |
160 | #define CLK_I2S2 129 |
161 | |
162 | /* DRAM Gates */ |
163 | #define CLK_DRAM_VE 130 |
164 | #define CLK_DRAM_CSI0 131 |
165 | #define CLK_DRAM_CSI1 132 |
166 | #define CLK_DRAM_TS 133 |
167 | #define CLK_DRAM_TVD 134 |
168 | #define CLK_DRAM_TVE0 135 |
169 | #define CLK_DRAM_TVE1 136 |
170 | #define CLK_DRAM_OUT 137 |
171 | #define CLK_DRAM_DE_FE1 138 |
172 | #define CLK_DRAM_DE_FE0 139 |
173 | #define CLK_DRAM_DE_BE0 140 |
174 | #define CLK_DRAM_DE_BE1 141 |
175 | #define CLK_DRAM_MP 142 |
176 | #define CLK_DRAM_ACE 143 |
177 | |
178 | /* Display Engine Clocks */ |
179 | #define CLK_DE_BE0 144 |
180 | #define CLK_DE_BE1 145 |
181 | #define CLK_DE_FE0 146 |
182 | #define CLK_DE_FE1 147 |
183 | #define CLK_DE_MP 148 |
184 | #define CLK_TCON0_CH0 149 |
185 | #define CLK_TCON1_CH0 150 |
186 | #define CLK_CSI_SCLK 151 |
187 | #define CLK_TVD_SCLK2 152 |
188 | #define CLK_TVD 153 |
189 | #define CLK_TCON0_CH1_SCLK2 154 |
190 | #define CLK_TCON0_CH1 155 |
191 | #define CLK_TCON1_CH1_SCLK2 156 |
192 | #define CLK_TCON1_CH1 157 |
193 | #define CLK_CSI0 158 |
194 | #define CLK_CSI1 159 |
195 | #define CLK_CODEC 160 |
196 | #define CLK_VE 161 |
197 | #define CLK_AVS 162 |
198 | #define CLK_ACE 163 |
199 | #define CLK_HDMI 164 |
200 | #define CLK_GPU 165 |
201 | |
202 | #endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */ |
203 | |