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| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
|---|---|
| 2 | /* |
| 3 | * Copyright (c) 2019 MediaTek Inc. |
| 4 | * Author: Dennis-YC Hsieh <dennis-yc.hsieh@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef _DT_BINDINGS_GCE_MT6779_H |
| 8 | #define _DT_BINDINGS_GCE_MT6779_H |
| 9 | |
| 10 | #define CMDQ_NO_TIMEOUT 0xffffffff |
| 11 | |
| 12 | /* GCE HW thread priority */ |
| 13 | #define CMDQ_THR_PRIO_LOWEST 0 |
| 14 | #define CMDQ_THR_PRIO_1 1 |
| 15 | #define CMDQ_THR_PRIO_2 2 |
| 16 | #define CMDQ_THR_PRIO_3 3 |
| 17 | #define CMDQ_THR_PRIO_4 4 |
| 18 | #define CMDQ_THR_PRIO_5 5 |
| 19 | #define CMDQ_THR_PRIO_6 6 |
| 20 | #define CMDQ_THR_PRIO_HIGHEST 7 |
| 21 | |
| 22 | /* GCE subsys table */ |
| 23 | #define SUBSYS_1300XXXX 0 |
| 24 | #define SUBSYS_1400XXXX 1 |
| 25 | #define SUBSYS_1401XXXX 2 |
| 26 | #define SUBSYS_1402XXXX 3 |
| 27 | #define SUBSYS_1502XXXX 4 |
| 28 | #define SUBSYS_1880XXXX 5 |
| 29 | #define SUBSYS_1881XXXX 6 |
| 30 | #define SUBSYS_1882XXXX 7 |
| 31 | #define SUBSYS_1883XXXX 8 |
| 32 | #define SUBSYS_1884XXXX 9 |
| 33 | #define SUBSYS_1000XXXX 10 |
| 34 | #define SUBSYS_1001XXXX 11 |
| 35 | #define SUBSYS_1002XXXX 12 |
| 36 | #define SUBSYS_1003XXXX 13 |
| 37 | #define SUBSYS_1004XXXX 14 |
| 38 | #define SUBSYS_1005XXXX 15 |
| 39 | #define SUBSYS_1020XXXX 16 |
| 40 | #define SUBSYS_1028XXXX 17 |
| 41 | #define SUBSYS_1700XXXX 18 |
| 42 | #define SUBSYS_1701XXXX 19 |
| 43 | #define SUBSYS_1702XXXX 20 |
| 44 | #define SUBSYS_1703XXXX 21 |
| 45 | #define SUBSYS_1800XXXX 22 |
| 46 | #define SUBSYS_1801XXXX 23 |
| 47 | #define SUBSYS_1802XXXX 24 |
| 48 | #define SUBSYS_1804XXXX 25 |
| 49 | #define SUBSYS_1805XXXX 26 |
| 50 | #define SUBSYS_1808XXXX 27 |
| 51 | #define SUBSYS_180aXXXX 28 |
| 52 | #define SUBSYS_180bXXXX 29 |
| 53 | #define CMDQ_SUBSYS_OFF 32 |
| 54 | |
| 55 | /* GCE hardware events */ |
| 56 | #define CMDQ_EVENT_DISP_RDMA0_SOF 0 |
| 57 | #define CMDQ_EVENT_DISP_RDMA1_SOF 1 |
| 58 | #define CMDQ_EVENT_MDP_RDMA0_SOF 2 |
| 59 | #define CMDQ_EVENT_MDP_RDMA1_SOF 3 |
| 60 | #define CMDQ_EVENT_MDP_RSZ0_SOF 4 |
| 61 | #define CMDQ_EVENT_MDP_RSZ1_SOF 5 |
| 62 | #define CMDQ_EVENT_MDP_TDSHP_SOF 6 |
| 63 | #define CMDQ_EVENT_MDP_WROT0_SOF 7 |
| 64 | #define CMDQ_EVENT_MDP_WROT1_SOF 8 |
| 65 | #define CMDQ_EVENT_DISP_OVL0_SOF 9 |
| 66 | #define CMDQ_EVENT_DISP_2L_OVL0_SOF 10 |
| 67 | #define CMDQ_EVENT_DISP_2L_OVL1_SOF 11 |
| 68 | #define CMDQ_EVENT_DISP_WDMA0_SOF 12 |
| 69 | #define CMDQ_EVENT_DISP_COLOR0_SOF 13 |
| 70 | #define CMDQ_EVENT_DISP_CCORR0_SOF 14 |
| 71 | #define CMDQ_EVENT_DISP_AAL0_SOF 15 |
| 72 | #define CMDQ_EVENT_DISP_GAMMA0_SOF 16 |
| 73 | #define CMDQ_EVENT_DISP_DITHER0_SOF 17 |
| 74 | #define CMDQ_EVENT_DISP_PWM0_SOF 18 |
| 75 | #define CMDQ_EVENT_DISP_DSI0_SOF 19 |
| 76 | #define CMDQ_EVENT_DISP_DPI0_SOF 20 |
| 77 | #define CMDQ_EVENT_DISP_POSTMASK0_SOF 21 |
| 78 | #define CMDQ_EVENT_DISP_RSZ0_SOF 22 |
| 79 | #define CMDQ_EVENT_MDP_AAL_SOF 23 |
| 80 | #define CMDQ_EVENT_MDP_CCORR_SOF 24 |
| 81 | #define CMDQ_EVENT_DISP_DBI0_SOF 25 |
| 82 | #define CMDQ_EVENT_ISP_RELAY_SOF 26 |
| 83 | #define CMDQ_EVENT_IPU_RELAY_SOF 27 |
| 84 | #define CMDQ_EVENT_DISP_RDMA0_EOF 28 |
| 85 | #define CMDQ_EVENT_DISP_RDMA1_EOF 29 |
| 86 | #define CMDQ_EVENT_MDP_RDMA0_EOF 30 |
| 87 | #define CMDQ_EVENT_MDP_RDMA1_EOF 31 |
| 88 | #define CMDQ_EVENT_MDP_RSZ0_EOF 32 |
| 89 | #define CMDQ_EVENT_MDP_RSZ1_EOF 33 |
| 90 | #define CMDQ_EVENT_MDP_TDSHP_EOF 34 |
| 91 | #define CMDQ_EVENT_MDP_WROT0_W_EOF 35 |
| 92 | #define CMDQ_EVENT_MDP_WROT1_W_EOF 36 |
| 93 | #define CMDQ_EVENT_DISP_OVL0_EOF 37 |
| 94 | #define CMDQ_EVENT_DISP_2L_OVL0_EOF 38 |
| 95 | #define CMDQ_EVENT_DISP_2L_OVL1_EOF 39 |
| 96 | #define CMDQ_EVENT_DISP_WDMA0_EOF 40 |
| 97 | #define CMDQ_EVENT_DISP_COLOR0_EOF 41 |
| 98 | #define CMDQ_EVENT_DISP_CCORR0_EOF 42 |
| 99 | #define CMDQ_EVENT_DISP_AAL0_EOF 43 |
| 100 | #define CMDQ_EVENT_DISP_GAMMA0_EOF 44 |
| 101 | #define CMDQ_EVENT_DISP_DITHER0_EOF 45 |
| 102 | #define CMDQ_EVENT_DISP_DSI0_EOF 46 |
| 103 | #define CMDQ_EVENT_DISP_DPI0_EOF 47 |
| 104 | #define CMDQ_EVENT_DISP_RSZ0_EOF 49 |
| 105 | #define CMDQ_EVENT_MDP_AAL_FRAME_DONE 50 |
| 106 | #define CMDQ_EVENT_MDP_CCORR_FRAME_DONE 51 |
| 107 | #define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 52 |
| 108 | #define CMDQ_EVENT_MUTEX0_STREAM_EOF 130 |
| 109 | #define CMDQ_EVENT_MUTEX1_STREAM_EOF 131 |
| 110 | #define CMDQ_EVENT_MUTEX2_STREAM_EOF 132 |
| 111 | #define CMDQ_EVENT_MUTEX3_STREAM_EOF 133 |
| 112 | #define CMDQ_EVENT_MUTEX4_STREAM_EOF 134 |
| 113 | #define CMDQ_EVENT_MUTEX5_STREAM_EOF 135 |
| 114 | #define CMDQ_EVENT_MUTEX6_STREAM_EOF 136 |
| 115 | #define CMDQ_EVENT_MUTEX7_STREAM_EOF 137 |
| 116 | #define CMDQ_EVENT_MUTEX8_STREAM_EOF 138 |
| 117 | #define CMDQ_EVENT_MUTEX9_STREAM_EOF 139 |
| 118 | #define CMDQ_EVENT_MUTEX10_STREAM_EOF 140 |
| 119 | #define CMDQ_EVENT_MUTEX11_STREAM_EOF 141 |
| 120 | #define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 142 |
| 121 | #define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 143 |
| 122 | #define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 144 |
| 123 | #define CMDQ_EVENT_DISP_RDMA3_UNDERRUN 145 |
| 124 | #define CMDQ_EVENT_DSI0_TE 146 |
| 125 | #define CMDQ_EVENT_DSI0_IRQ_EVENT 147 |
| 126 | #define CMDQ_EVENT_DSI0_DONE_EVENT 148 |
| 127 | #define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE 150 |
| 128 | #define CMDQ_EVENT_DISP_WDMA0_RST_DONE 151 |
| 129 | #define CMDQ_EVENT_MDP_WROT0_RST_DONE 153 |
| 130 | #define CMDQ_EVENT_MDP_RDMA0_RST_DONE 154 |
| 131 | #define CMDQ_EVENT_DISP_OVL0_RST_DONE 155 |
| 132 | #define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE 156 |
| 133 | #define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE 157 |
| 134 | #define CMDQ_EVENT_DIP_CQ_THREAD0_EOF 257 |
| 135 | #define CMDQ_EVENT_DIP_CQ_THREAD1_EOF 258 |
| 136 | #define CMDQ_EVENT_DIP_CQ_THREAD2_EOF 259 |
| 137 | #define CMDQ_EVENT_DIP_CQ_THREAD3_EOF 260 |
| 138 | #define CMDQ_EVENT_DIP_CQ_THREAD4_EOF 261 |
| 139 | #define CMDQ_EVENT_DIP_CQ_THREAD5_EOF 262 |
| 140 | #define CMDQ_EVENT_DIP_CQ_THREAD6_EOF 263 |
| 141 | #define CMDQ_EVENT_DIP_CQ_THREAD7_EOF 264 |
| 142 | #define CMDQ_EVENT_DIP_CQ_THREAD8_EOF 265 |
| 143 | #define CMDQ_EVENT_DIP_CQ_THREAD9_EOF 266 |
| 144 | #define CMDQ_EVENT_DIP_CQ_THREAD10_EOF 267 |
| 145 | #define CMDQ_EVENT_DIP_CQ_THREAD11_EOF 268 |
| 146 | #define CMDQ_EVENT_DIP_CQ_THREAD12_EOF 269 |
| 147 | #define CMDQ_EVENT_DIP_CQ_THREAD13_EOF 270 |
| 148 | #define CMDQ_EVENT_DIP_CQ_THREAD14_EOF 271 |
| 149 | #define CMDQ_EVENT_DIP_CQ_THREAD15_EOF 272 |
| 150 | #define CMDQ_EVENT_DIP_CQ_THREAD16_EOF 273 |
| 151 | #define CMDQ_EVENT_DIP_CQ_THREAD17_EOF 274 |
| 152 | #define CMDQ_EVENT_DIP_CQ_THREAD18_EOF 275 |
| 153 | #define CMDQ_EVENT_DIP_DMA_ERR_EVENT 276 |
| 154 | #define CMDQ_EVENT_AMD_FRAME_DONE 277 |
| 155 | #define CMDQ_EVENT_MFB_DONE 278 |
| 156 | #define CMDQ_EVENT_WPE_A_EOF 279 |
| 157 | #define CMDQ_EVENT_VENC_EOF 289 |
| 158 | #define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 290 |
| 159 | #define CMDQ_EVENT_JPEG_ENC_EOF 291 |
| 160 | #define CMDQ_EVENT_VENC_MB_DONE 292 |
| 161 | #define CMDQ_EVENT_VENC_128BYTE_CNT_DONE 293 |
| 162 | #define CMDQ_EVENT_ISP_FRAME_DONE_A 321 |
| 163 | #define CMDQ_EVENT_ISP_FRAME_DONE_B 322 |
| 164 | #define CMDQ_EVENT_ISP_FRAME_DONE_C 323 |
| 165 | #define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE 324 |
| 166 | #define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE 325 |
| 167 | #define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE 326 |
| 168 | #define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE 327 |
| 169 | #define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE 328 |
| 170 | #define CMDQ_EVENT_ISP_TSF_DONE 329 |
| 171 | #define CMDQ_EVENT_SENINF_0_FIFO_FULL 330 |
| 172 | #define CMDQ_EVENT_SENINF_1_FIFO_FULL 331 |
| 173 | #define CMDQ_EVENT_SENINF_2_FIFO_FULL 332 |
| 174 | #define CMDQ_EVENT_SENINF_3_FIFO_FULL 333 |
| 175 | #define CMDQ_EVENT_SENINF_4_FIFO_FULL 334 |
| 176 | #define CMDQ_EVENT_SENINF_5_FIFO_FULL 335 |
| 177 | #define CMDQ_EVENT_SENINF_6_FIFO_FULL 336 |
| 178 | #define CMDQ_EVENT_SENINF_7_FIFO_FULL 337 |
| 179 | #define CMDQ_EVENT_TG_OVRUN_A_INT_DLY 338 |
| 180 | #define CMDQ_EVENT_TG_OVRUN_B_INT_DLY 339 |
| 181 | #define CMDQ_EVENT_TG_OVRUN_C_INT 340 |
| 182 | #define CMDQ_EVENT_TG_GRABERR_A_INT_DLY 341 |
| 183 | #define CMDQ_EVENT_TG_GRABERR_B_INT_DLY 342 |
| 184 | #define CMDQ_EVENT_TG_GRABERR_C_INT 343 |
| 185 | #define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY 344 |
| 186 | #define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY 345 |
| 187 | #define CMDQ_EVENT_CQ_VR_SNAP_C_INT 346 |
| 188 | #define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY 347 |
| 189 | #define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY 348 |
| 190 | #define CMDQ_EVENT_DMA_R1_ERROR_C_INT 349 |
| 191 | #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0 353 |
| 192 | #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1 354 |
| 193 | #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2 355 |
| 194 | #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3 356 |
| 195 | #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0 385 |
| 196 | #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1 386 |
| 197 | #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2 387 |
| 198 | #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3 388 |
| 199 | #define CMDQ_EVENT_VDEC_EVENT_0 416 |
| 200 | #define CMDQ_EVENT_VDEC_EVENT_1 417 |
| 201 | #define CMDQ_EVENT_VDEC_EVENT_2 418 |
| 202 | #define CMDQ_EVENT_VDEC_EVENT_3 419 |
| 203 | #define CMDQ_EVENT_VDEC_EVENT_4 420 |
| 204 | #define CMDQ_EVENT_VDEC_EVENT_5 421 |
| 205 | #define CMDQ_EVENT_VDEC_EVENT_6 422 |
| 206 | #define CMDQ_EVENT_VDEC_EVENT_7 423 |
| 207 | #define CMDQ_EVENT_VDEC_EVENT_8 424 |
| 208 | #define CMDQ_EVENT_VDEC_EVENT_9 425 |
| 209 | #define CMDQ_EVENT_VDEC_EVENT_10 426 |
| 210 | #define CMDQ_EVENT_VDEC_EVENT_11 427 |
| 211 | #define CMDQ_EVENT_VDEC_EVENT_12 428 |
| 212 | #define CMDQ_EVENT_VDEC_EVENT_13 429 |
| 213 | #define CMDQ_EVENT_VDEC_EVENT_14 430 |
| 214 | #define CMDQ_EVENT_VDEC_EVENT_15 431 |
| 215 | #define CMDQ_EVENT_FDVT_DONE 449 |
| 216 | #define CMDQ_EVENT_FE_DONE 450 |
| 217 | #define CMDQ_EVENT_RSC_EOF 451 |
| 218 | #define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 452 |
| 219 | #define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 453 |
| 220 | #define CMDQ_EVENT_DSI0_TE_INFRA 898 |
| 221 | |
| 222 | #endif |
| 223 |
Warning: This file is not a C or C++ file. It does not have highlighting.