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| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
|---|---|
| 2 | /* |
| 3 | * Copyright (c) 2019 MediaTek Inc. |
| 4 | * Author: Bibby Hsieh <bibby.hsieh@mediatek.com> |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef _DT_BINDINGS_GCE_MT8183_H |
| 9 | #define _DT_BINDINGS_GCE_MT8183_H |
| 10 | |
| 11 | #define CMDQ_NO_TIMEOUT 0xffffffff |
| 12 | |
| 13 | /* GCE HW thread priority */ |
| 14 | #define CMDQ_THR_PRIO_LOWEST 0 |
| 15 | #define CMDQ_THR_PRIO_HIGHEST 1 |
| 16 | |
| 17 | /* GCE SUBSYS */ |
| 18 | #define SUBSYS_1300XXXX 0 |
| 19 | #define SUBSYS_1400XXXX 1 |
| 20 | #define SUBSYS_1401XXXX 2 |
| 21 | #define SUBSYS_1402XXXX 3 |
| 22 | #define SUBSYS_1502XXXX 4 |
| 23 | #define SUBSYS_1880XXXX 5 |
| 24 | #define SUBSYS_1881XXXX 6 |
| 25 | #define SUBSYS_1882XXXX 7 |
| 26 | #define SUBSYS_1883XXXX 8 |
| 27 | #define SUBSYS_1884XXXX 9 |
| 28 | #define SUBSYS_1000XXXX 10 |
| 29 | #define SUBSYS_1001XXXX 11 |
| 30 | #define SUBSYS_1002XXXX 12 |
| 31 | #define SUBSYS_1003XXXX 13 |
| 32 | #define SUBSYS_1004XXXX 14 |
| 33 | #define SUBSYS_1005XXXX 15 |
| 34 | #define SUBSYS_1020XXXX 16 |
| 35 | #define SUBSYS_1028XXXX 17 |
| 36 | #define SUBSYS_1700XXXX 18 |
| 37 | #define SUBSYS_1701XXXX 19 |
| 38 | #define SUBSYS_1702XXXX 20 |
| 39 | #define SUBSYS_1703XXXX 21 |
| 40 | #define SUBSYS_1800XXXX 22 |
| 41 | #define SUBSYS_1801XXXX 23 |
| 42 | #define SUBSYS_1802XXXX 24 |
| 43 | #define SUBSYS_1804XXXX 25 |
| 44 | #define SUBSYS_1805XXXX 26 |
| 45 | #define SUBSYS_1808XXXX 27 |
| 46 | #define SUBSYS_180aXXXX 28 |
| 47 | #define SUBSYS_180bXXXX 29 |
| 48 | |
| 49 | #define CMDQ_EVENT_DISP_RDMA0_SOF 0 |
| 50 | #define CMDQ_EVENT_DISP_RDMA1_SOF 1 |
| 51 | #define CMDQ_EVENT_MDP_RDMA0_SOF 2 |
| 52 | #define CMDQ_EVENT_MDP_RSZ0_SOF 4 |
| 53 | #define CMDQ_EVENT_MDP_RSZ1_SOF 5 |
| 54 | #define CMDQ_EVENT_MDP_TDSHP_SOF 6 |
| 55 | #define CMDQ_EVENT_MDP_WROT0_SOF 7 |
| 56 | #define CMDQ_EVENT_MDP_WDMA0_SOF 8 |
| 57 | #define CMDQ_EVENT_DISP_OVL0_SOF 9 |
| 58 | #define CMDQ_EVENT_DISP_OVL0_2L_SOF 10 |
| 59 | #define CMDQ_EVENT_DISP_OVL1_2L_SOF 11 |
| 60 | #define CMDQ_EVENT_DISP_WDMA0_SOF 12 |
| 61 | #define CMDQ_EVENT_DISP_COLOR0_SOF 13 |
| 62 | #define CMDQ_EVENT_DISP_CCORR0_SOF 14 |
| 63 | #define CMDQ_EVENT_DISP_AAL0_SOF 15 |
| 64 | #define CMDQ_EVENT_DISP_GAMMA0_SOF 16 |
| 65 | #define CMDQ_EVENT_DISP_DITHER0_SOF 17 |
| 66 | #define CMDQ_EVENT_DISP_PWM0_SOF 18 |
| 67 | #define CMDQ_EVENT_DISP_DSI0_SOF 19 |
| 68 | #define CMDQ_EVENT_DISP_DPI0_SOF 20 |
| 69 | #define CMDQ_EVENT_DISP_RSZ_SOF 22 |
| 70 | #define CMDQ_EVENT_MDP_AAL_SOF 23 |
| 71 | #define CMDQ_EVENT_MDP_CCORR_SOF 24 |
| 72 | #define CMDQ_EVENT_DISP_DBI_SOF 25 |
| 73 | #define CMDQ_EVENT_DISP_RDMA0_EOF 26 |
| 74 | #define CMDQ_EVENT_DISP_RDMA1_EOF 27 |
| 75 | #define CMDQ_EVENT_MDP_RDMA0_EOF 28 |
| 76 | #define CMDQ_EVENT_MDP_RSZ0_EOF 30 |
| 77 | #define CMDQ_EVENT_MDP_RSZ1_EOF 31 |
| 78 | #define CMDQ_EVENT_MDP_TDSHP_EOF 32 |
| 79 | #define CMDQ_EVENT_MDP_WROT0_EOF 33 |
| 80 | #define CMDQ_EVENT_MDP_WDMA0_EOF 34 |
| 81 | #define CMDQ_EVENT_DISP_OVL0_EOF 35 |
| 82 | #define CMDQ_EVENT_DISP_OVL0_2L_EOF 36 |
| 83 | #define CMDQ_EVENT_DISP_OVL1_2L_EOF 37 |
| 84 | #define CMDQ_EVENT_DISP_WDMA0_EOF 38 |
| 85 | #define CMDQ_EVENT_DISP_COLOR0_EOF 39 |
| 86 | #define CMDQ_EVENT_DISP_CCORR0_EOF 40 |
| 87 | #define CMDQ_EVENT_DISP_AAL0_EOF 41 |
| 88 | #define CMDQ_EVENT_DISP_GAMMA0_EOF 42 |
| 89 | #define CMDQ_EVENT_DISP_DITHER0_EOF 43 |
| 90 | #define CMDQ_EVENT_DSI0_EOF 44 |
| 91 | #define CMDQ_EVENT_DPI0_EOF 45 |
| 92 | #define CMDQ_EVENT_DISP_RSZ_EOF 47 |
| 93 | #define CMDQ_EVENT_MDP_AAL_EOF 48 |
| 94 | #define CMDQ_EVENT_MDP_CCORR_EOF 49 |
| 95 | #define CMDQ_EVENT_DBI_EOF 50 |
| 96 | #define CMDQ_EVENT_MUTEX_STREAM_DONE0 130 |
| 97 | #define CMDQ_EVENT_MUTEX_STREAM_DONE1 131 |
| 98 | #define CMDQ_EVENT_MUTEX_STREAM_DONE2 132 |
| 99 | #define CMDQ_EVENT_MUTEX_STREAM_DONE3 133 |
| 100 | #define CMDQ_EVENT_MUTEX_STREAM_DONE4 134 |
| 101 | #define CMDQ_EVENT_MUTEX_STREAM_DONE5 135 |
| 102 | #define CMDQ_EVENT_MUTEX_STREAM_DONE6 136 |
| 103 | #define CMDQ_EVENT_MUTEX_STREAM_DONE7 137 |
| 104 | #define CMDQ_EVENT_MUTEX_STREAM_DONE8 138 |
| 105 | #define CMDQ_EVENT_MUTEX_STREAM_DONE9 139 |
| 106 | #define CMDQ_EVENT_MUTEX_STREAM_DONE10 140 |
| 107 | #define CMDQ_EVENT_MUTEX_STREAM_DONE11 141 |
| 108 | #define CMDQ_EVENT_DISP_RDMA0_BUF_UNDERRUN_EVEN 142 |
| 109 | #define CMDQ_EVENT_DISP_RDMA1_BUF_UNDERRUN_EVEN 143 |
| 110 | #define CMDQ_EVENT_DSI0_TE_EVENT 144 |
| 111 | #define CMDQ_EVENT_DSI0_IRQ_EVENT 145 |
| 112 | #define CMDQ_EVENT_DSI0_DONE_EVENT 146 |
| 113 | #define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE 150 |
| 114 | #define CMDQ_EVENT_MDP_WDMA_SW_RST_DONE 151 |
| 115 | #define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE 152 |
| 116 | #define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE 154 |
| 117 | #define CMDQ_EVENT_DISP_OVL0_FRAME_RST_DONE_PULE 155 |
| 118 | #define CMDQ_EVENT_DISP_OVL0_2L_FRAME_RST_DONE_ULSE 156 |
| 119 | #define CMDQ_EVENT_DISP_OVL1_2L_FRAME_RST_DONE_ULSE 157 |
| 120 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_0 257 |
| 121 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_1 258 |
| 122 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_2 259 |
| 123 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_3 260 |
| 124 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_4 261 |
| 125 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_5 262 |
| 126 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_6 263 |
| 127 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_7 264 |
| 128 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_8 265 |
| 129 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_9 266 |
| 130 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_10 267 |
| 131 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_11 268 |
| 132 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_12 269 |
| 133 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_13 270 |
| 134 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_14 271 |
| 135 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_15 272 |
| 136 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_16 273 |
| 137 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_17 274 |
| 138 | #define CMDQ_EVENT_ISP_FRAME_DONE_P2_18 275 |
| 139 | #define CMDQ_EVENT_AMD_FRAME_DONE 276 |
| 140 | #define CMDQ_EVENT_DVE_DONE 277 |
| 141 | #define CMDQ_EVENT_WMFE_DONE 278 |
| 142 | #define CMDQ_EVENT_RSC_DONE 279 |
| 143 | #define CMDQ_EVENT_MFB_DONE 280 |
| 144 | #define CMDQ_EVENT_WPE_A_DONE 281 |
| 145 | #define CMDQ_EVENT_SPE_B_DONE 282 |
| 146 | #define CMDQ_EVENT_OCC_DONE 283 |
| 147 | #define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 289 |
| 148 | #define CMDQ_EVENT_JPG_ENC_CMDQ_DONE 290 |
| 149 | #define CMDQ_EVENT_JPG_DEC_CMDQ_DONE 291 |
| 150 | #define CMDQ_EVENT_VENC_CMDQ_MB_DONE 292 |
| 151 | #define CMDQ_EVENT_VENC_CMDQ_128BYTE_DONE 293 |
| 152 | #define CMDQ_EVENT_ISP_FRAME_DONE_A 321 |
| 153 | #define CMDQ_EVENT_ISP_FRAME_DONE_B 322 |
| 154 | #define CMDQ_EVENT_CAMSV0_PASS1_DONE 323 |
| 155 | #define CMDQ_EVENT_CAMSV1_PASS1_DONE 324 |
| 156 | #define CMDQ_EVENT_CAMSV2_PASS1_DONE 325 |
| 157 | #define CMDQ_EVENT_TSF_DONE 326 |
| 158 | #define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 327 |
| 159 | #define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 328 |
| 160 | #define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 329 |
| 161 | #define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 330 |
| 162 | #define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 331 |
| 163 | #define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 332 |
| 164 | #define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 333 |
| 165 | #define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 334 |
| 166 | #define CMDQ_EVENT_IPU_CORE0_DONE0 353 |
| 167 | #define CMDQ_EVENT_IPU_CORE0_DONE1 354 |
| 168 | #define CMDQ_EVENT_IPU_CORE0_DONE2 355 |
| 169 | #define CMDQ_EVENT_IPU_CORE0_DONE3 356 |
| 170 | #define CMDQ_EVENT_IPU_CORE1_DONE0 385 |
| 171 | #define CMDQ_EVENT_IPU_CORE1_DONE1 386 |
| 172 | #define CMDQ_EVENT_IPU_CORE1_DONE2 387 |
| 173 | #define CMDQ_EVENT_IPU_CORE1_DONE3 388 |
| 174 | |
| 175 | #endif |
| 176 |
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