| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. */ |
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| 3 | |
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| 4 | /* |
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| 5 | * This header provides constants for the nvidia,tegra241-gpio DT binding. |
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| 6 | * |
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| 7 | * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below |
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| 8 | * provide names for this. |
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| 9 | * |
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| 10 | * The second cell contains standard flag values specified in gpio.h. |
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| 11 | */ |
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| 12 | |
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| 13 | #ifndef _DT_BINDINGS_GPIO_TEGRA241_GPIO_H |
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| 14 | #define _DT_BINDINGS_GPIO_TEGRA241_GPIO_H |
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| 15 | |
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| 16 | #include <dt-bindings/gpio/gpio.h> |
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| 17 | |
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| 18 | /* GPIOs implemented by main GPIO controller */ |
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| 19 | #define TEGRA241_MAIN_GPIO_PORT_A 0 |
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| 20 | #define TEGRA241_MAIN_GPIO_PORT_B 1 |
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| 21 | #define TEGRA241_MAIN_GPIO_PORT_C 2 |
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| 22 | #define TEGRA241_MAIN_GPIO_PORT_D 3 |
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| 23 | #define TEGRA241_MAIN_GPIO_PORT_E 4 |
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| 24 | #define TEGRA241_MAIN_GPIO_PORT_F 5 |
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| 25 | #define TEGRA241_MAIN_GPIO_PORT_G 6 |
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| 26 | #define TEGRA241_MAIN_GPIO_PORT_H 7 |
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| 27 | #define TEGRA241_MAIN_GPIO_PORT_I 8 |
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| 28 | #define TEGRA241_MAIN_GPIO_PORT_J 9 |
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| 29 | #define TEGRA241_MAIN_GPIO_PORT_K 10 |
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| 30 | #define TEGRA241_MAIN_GPIO_PORT_L 11 |
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| 31 | |
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| 32 | #define TEGRA241_MAIN_GPIO(port, offset) \ |
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| 33 | ((TEGRA241_MAIN_GPIO_PORT_##port * 8) + (offset)) |
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| 34 | |
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| 35 | /* GPIOs implemented by AON GPIO controller */ |
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| 36 | #define TEGRA241_AON_GPIO_PORT_AA 0 |
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| 37 | #define TEGRA241_AON_GPIO_PORT_BB 1 |
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| 38 | |
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| 39 | #define TEGRA241_AON_GPIO(port, offset) \ |
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| 40 | ((TEGRA241_AON_GPIO_PORT_##port * 8) + (offset)) |
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| 41 | |
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| 42 | #endif |
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| 43 | |
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