1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H |
3 | #define DT_BINDINGS_MEMORY_TEGRA124_MC_H |
4 | |
5 | #define TEGRA_SWGROUP_PTC 0 |
6 | #define TEGRA_SWGROUP_DC 1 |
7 | #define TEGRA_SWGROUP_DCB 2 |
8 | #define TEGRA_SWGROUP_AFI 3 |
9 | #define TEGRA_SWGROUP_AVPC 4 |
10 | #define TEGRA_SWGROUP_HDA 5 |
11 | #define TEGRA_SWGROUP_HC 6 |
12 | #define TEGRA_SWGROUP_MSENC 7 |
13 | #define TEGRA_SWGROUP_PPCS 8 |
14 | #define TEGRA_SWGROUP_SATA 9 |
15 | #define TEGRA_SWGROUP_VDE 10 |
16 | #define TEGRA_SWGROUP_MPCORELP 11 |
17 | #define TEGRA_SWGROUP_MPCORE 12 |
18 | #define TEGRA_SWGROUP_ISP2 13 |
19 | #define TEGRA_SWGROUP_XUSB_HOST 14 |
20 | #define TEGRA_SWGROUP_XUSB_DEV 15 |
21 | #define TEGRA_SWGROUP_ISP2B 16 |
22 | #define TEGRA_SWGROUP_TSEC 17 |
23 | #define TEGRA_SWGROUP_A9AVP 18 |
24 | #define TEGRA_SWGROUP_GPU 19 |
25 | #define TEGRA_SWGROUP_SDMMC1A 20 |
26 | #define TEGRA_SWGROUP_SDMMC2A 21 |
27 | #define TEGRA_SWGROUP_SDMMC3A 22 |
28 | #define TEGRA_SWGROUP_SDMMC4A 23 |
29 | #define TEGRA_SWGROUP_VIC 24 |
30 | #define TEGRA_SWGROUP_VI 25 |
31 | |
32 | #define TEGRA124_MC_RESET_AFI 0 |
33 | #define TEGRA124_MC_RESET_AVPC 1 |
34 | #define TEGRA124_MC_RESET_DC 2 |
35 | #define TEGRA124_MC_RESET_DCB 3 |
36 | #define TEGRA124_MC_RESET_HC 4 |
37 | #define TEGRA124_MC_RESET_HDA 5 |
38 | #define TEGRA124_MC_RESET_ISP2 6 |
39 | #define TEGRA124_MC_RESET_MPCORE 7 |
40 | #define TEGRA124_MC_RESET_MPCORELP 8 |
41 | #define TEGRA124_MC_RESET_MSENC 9 |
42 | #define TEGRA124_MC_RESET_PPCS 10 |
43 | #define TEGRA124_MC_RESET_SATA 11 |
44 | #define TEGRA124_MC_RESET_VDE 12 |
45 | #define TEGRA124_MC_RESET_VI 13 |
46 | #define TEGRA124_MC_RESET_VIC 14 |
47 | #define TEGRA124_MC_RESET_XUSB_HOST 15 |
48 | #define TEGRA124_MC_RESET_XUSB_DEV 16 |
49 | #define TEGRA124_MC_RESET_TSEC 17 |
50 | #define TEGRA124_MC_RESET_SDMMC1 18 |
51 | #define TEGRA124_MC_RESET_SDMMC2 19 |
52 | #define TEGRA124_MC_RESET_SDMMC3 20 |
53 | #define TEGRA124_MC_RESET_SDMMC4 21 |
54 | #define TEGRA124_MC_RESET_ISP2B 22 |
55 | #define TEGRA124_MC_RESET_GPU 23 |
56 | |
57 | #define TEGRA124_MC_PTCR 0 |
58 | #define TEGRA124_MC_DISPLAY0A 1 |
59 | #define TEGRA124_MC_DISPLAY0AB 2 |
60 | #define TEGRA124_MC_DISPLAY0B 3 |
61 | #define TEGRA124_MC_DISPLAY0BB 4 |
62 | #define TEGRA124_MC_DISPLAY0C 5 |
63 | #define TEGRA124_MC_DISPLAY0CB 6 |
64 | #define TEGRA124_MC_AFIR 14 |
65 | #define TEGRA124_MC_AVPCARM7R 15 |
66 | #define TEGRA124_MC_DISPLAYHC 16 |
67 | #define TEGRA124_MC_DISPLAYHCB 17 |
68 | #define TEGRA124_MC_HDAR 21 |
69 | #define TEGRA124_MC_HOST1XDMAR 22 |
70 | #define TEGRA124_MC_HOST1XR 23 |
71 | #define TEGRA124_MC_MSENCSRD 28 |
72 | #define TEGRA124_MC_PPCSAHBDMAR 29 |
73 | #define TEGRA124_MC_PPCSAHBSLVR 30 |
74 | #define TEGRA124_MC_SATAR 31 |
75 | #define TEGRA124_MC_VDEBSEVR 34 |
76 | #define TEGRA124_MC_VDEMBER 35 |
77 | #define TEGRA124_MC_VDEMCER 36 |
78 | #define TEGRA124_MC_VDETPER 37 |
79 | #define TEGRA124_MC_MPCORELPR 38 |
80 | #define TEGRA124_MC_MPCORER 39 |
81 | #define TEGRA124_MC_MSENCSWR 43 |
82 | #define TEGRA124_MC_AFIW 49 |
83 | #define TEGRA124_MC_AVPCARM7W 50 |
84 | #define TEGRA124_MC_HDAW 53 |
85 | #define TEGRA124_MC_HOST1XW 54 |
86 | #define TEGRA124_MC_MPCORELPW 56 |
87 | #define TEGRA124_MC_MPCOREW 57 |
88 | #define TEGRA124_MC_PPCSAHBDMAW 59 |
89 | #define TEGRA124_MC_PPCSAHBSLVW 60 |
90 | #define TEGRA124_MC_SATAW 61 |
91 | #define TEGRA124_MC_VDEBSEVW 62 |
92 | #define TEGRA124_MC_VDEDBGW 63 |
93 | #define TEGRA124_MC_VDEMBEW 64 |
94 | #define TEGRA124_MC_VDETPMW 65 |
95 | #define TEGRA124_MC_ISPRA 68 |
96 | #define TEGRA124_MC_ISPWA 70 |
97 | #define TEGRA124_MC_ISPWB 71 |
98 | #define TEGRA124_MC_XUSB_HOSTR 74 |
99 | #define TEGRA124_MC_XUSB_HOSTW 75 |
100 | #define TEGRA124_MC_XUSB_DEVR 76 |
101 | #define TEGRA124_MC_XUSB_DEVW 77 |
102 | #define TEGRA124_MC_ISPRAB 78 |
103 | #define TEGRA124_MC_ISPWAB 80 |
104 | #define TEGRA124_MC_ISPWBB 81 |
105 | #define TEGRA124_MC_TSECSRD 84 |
106 | #define TEGRA124_MC_TSECSWR 85 |
107 | #define TEGRA124_MC_A9AVPSCR 86 |
108 | #define TEGRA124_MC_A9AVPSCW 87 |
109 | #define TEGRA124_MC_GPUSRD 88 |
110 | #define TEGRA124_MC_GPUSWR 89 |
111 | #define TEGRA124_MC_DISPLAYT 90 |
112 | #define TEGRA124_MC_SDMMCRA 96 |
113 | #define TEGRA124_MC_SDMMCRAA 97 |
114 | #define TEGRA124_MC_SDMMCR 98 |
115 | #define TEGRA124_MC_SDMMCRAB 99 |
116 | #define TEGRA124_MC_SDMMCWA 100 |
117 | #define TEGRA124_MC_SDMMCWAA 101 |
118 | #define TEGRA124_MC_SDMMCW 102 |
119 | #define TEGRA124_MC_SDMMCWAB 103 |
120 | #define TEGRA124_MC_VICSRD 108 |
121 | #define TEGRA124_MC_VICSWR 109 |
122 | #define TEGRA124_MC_VIW 114 |
123 | #define TEGRA124_MC_DISPLAYD 115 |
124 | |
125 | #endif |
126 | |