1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H |
3 | #define DT_BINDINGS_MEMORY_TEGRA210_MC_H |
4 | |
5 | #define TEGRA_SWGROUP_PTC 0 |
6 | #define TEGRA_SWGROUP_DC 1 |
7 | #define TEGRA_SWGROUP_DCB 2 |
8 | #define TEGRA_SWGROUP_AFI 3 |
9 | #define TEGRA_SWGROUP_AVPC 4 |
10 | #define TEGRA_SWGROUP_HDA 5 |
11 | #define TEGRA_SWGROUP_HC 6 |
12 | #define TEGRA_SWGROUP_NVENC 7 |
13 | #define TEGRA_SWGROUP_PPCS 8 |
14 | #define TEGRA_SWGROUP_SATA 9 |
15 | #define TEGRA_SWGROUP_MPCORE 10 |
16 | #define TEGRA_SWGROUP_ISP2 11 |
17 | #define TEGRA_SWGROUP_XUSB_HOST 12 |
18 | #define TEGRA_SWGROUP_XUSB_DEV 13 |
19 | #define TEGRA_SWGROUP_ISP2B 14 |
20 | #define TEGRA_SWGROUP_TSEC 15 |
21 | #define TEGRA_SWGROUP_A9AVP 16 |
22 | #define TEGRA_SWGROUP_GPU 17 |
23 | #define TEGRA_SWGROUP_SDMMC1A 18 |
24 | #define TEGRA_SWGROUP_SDMMC2A 19 |
25 | #define TEGRA_SWGROUP_SDMMC3A 20 |
26 | #define TEGRA_SWGROUP_SDMMC4A 21 |
27 | #define TEGRA_SWGROUP_VIC 22 |
28 | #define TEGRA_SWGROUP_VI 23 |
29 | #define TEGRA_SWGROUP_NVDEC 24 |
30 | #define TEGRA_SWGROUP_APE 25 |
31 | #define TEGRA_SWGROUP_NVJPG 26 |
32 | #define TEGRA_SWGROUP_SE 27 |
33 | #define TEGRA_SWGROUP_AXIAP 28 |
34 | #define TEGRA_SWGROUP_ETR 29 |
35 | #define TEGRA_SWGROUP_TSECB 30 |
36 | #define TEGRA_SWGROUP_NV 31 |
37 | #define TEGRA_SWGROUP_NV2 32 |
38 | #define TEGRA_SWGROUP_PPCS1 33 |
39 | #define TEGRA_SWGROUP_DC1 34 |
40 | #define TEGRA_SWGROUP_PPCS2 35 |
41 | #define TEGRA_SWGROUP_HC1 36 |
42 | #define TEGRA_SWGROUP_SE1 37 |
43 | #define TEGRA_SWGROUP_TSEC1 38 |
44 | #define TEGRA_SWGROUP_TSECB1 39 |
45 | #define TEGRA_SWGROUP_NVDEC1 40 |
46 | |
47 | #define TEGRA210_MC_RESET_AFI 0 |
48 | #define TEGRA210_MC_RESET_AVPC 1 |
49 | #define TEGRA210_MC_RESET_DC 2 |
50 | #define TEGRA210_MC_RESET_DCB 3 |
51 | #define TEGRA210_MC_RESET_HC 4 |
52 | #define TEGRA210_MC_RESET_HDA 5 |
53 | #define TEGRA210_MC_RESET_ISP2 6 |
54 | #define TEGRA210_MC_RESET_MPCORE 7 |
55 | #define TEGRA210_MC_RESET_NVENC 8 |
56 | #define TEGRA210_MC_RESET_PPCS 9 |
57 | #define TEGRA210_MC_RESET_SATA 10 |
58 | #define TEGRA210_MC_RESET_VI 11 |
59 | #define TEGRA210_MC_RESET_VIC 12 |
60 | #define TEGRA210_MC_RESET_XUSB_HOST 13 |
61 | #define TEGRA210_MC_RESET_XUSB_DEV 14 |
62 | #define TEGRA210_MC_RESET_A9AVP 15 |
63 | #define TEGRA210_MC_RESET_TSEC 16 |
64 | #define TEGRA210_MC_RESET_SDMMC1 17 |
65 | #define TEGRA210_MC_RESET_SDMMC2 18 |
66 | #define TEGRA210_MC_RESET_SDMMC3 19 |
67 | #define TEGRA210_MC_RESET_SDMMC4 20 |
68 | #define TEGRA210_MC_RESET_ISP2B 21 |
69 | #define TEGRA210_MC_RESET_GPU 22 |
70 | #define TEGRA210_MC_RESET_NVDEC 23 |
71 | #define TEGRA210_MC_RESET_APE 24 |
72 | #define TEGRA210_MC_RESET_SE 25 |
73 | #define TEGRA210_MC_RESET_NVJPG 26 |
74 | #define TEGRA210_MC_RESET_AXIAP 27 |
75 | #define TEGRA210_MC_RESET_ETR 28 |
76 | #define TEGRA210_MC_RESET_TSECB 29 |
77 | |
78 | #endif |
79 | |