| 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
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| 2 | /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ |
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| 3 | |
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| 4 | #ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H |
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| 5 | #define DT_BINDINGS_MEMORY_TEGRA234_MC_H |
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| 6 | |
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| 7 | /* special clients */ |
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| 8 | #define TEGRA234_SID_INVALID 0x00 |
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| 9 | #define TEGRA234_SID_PASSTHROUGH 0x7f |
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| 10 | |
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| 11 | /* ISO stream IDs */ |
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| 12 | #define TEGRA234_SID_ISO_NVDISPLAY 0x01 |
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| 13 | #define TEGRA234_SID_ISO_VI 0x02 |
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| 14 | #define TEGRA234_SID_ISO_VIFALC 0x03 |
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| 15 | #define TEGRA234_SID_ISO_VI2 0x04 |
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| 16 | #define TEGRA234_SID_ISO_VI2FALC 0x05 |
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| 17 | #define TEGRA234_SID_ISO_VI_VM2 0x06 |
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| 18 | #define TEGRA234_SID_ISO_VI2_VM2 0x07 |
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| 19 | |
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| 20 | /* NISO0 stream IDs */ |
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| 21 | #define TEGRA234_SID_AON 0x01 |
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| 22 | #define TEGRA234_SID_APE 0x02 |
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| 23 | #define TEGRA234_SID_HDA 0x03 |
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| 24 | #define TEGRA234_SID_GPCDMA 0x04 |
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| 25 | #define TEGRA234_SID_ETR 0x05 |
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| 26 | #define TEGRA234_SID_MGBE 0x06 |
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| 27 | #define TEGRA234_SID_NVDISPLAY 0x07 |
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| 28 | #define TEGRA234_SID_DCE 0x08 |
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| 29 | #define TEGRA234_SID_PSC 0x09 |
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| 30 | #define TEGRA234_SID_RCE 0x0a |
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| 31 | #define TEGRA234_SID_SCE 0x0b |
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| 32 | #define TEGRA234_SID_UFSHC 0x0c |
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| 33 | #define TEGRA234_SID_APE_1 0x0d |
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| 34 | #define TEGRA234_SID_GPCDMA_1 0x0e |
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| 35 | #define TEGRA234_SID_GPCDMA_2 0x0f |
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| 36 | #define TEGRA234_SID_GPCDMA_3 0x10 |
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| 37 | #define TEGRA234_SID_GPCDMA_4 0x11 |
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| 38 | #define TEGRA234_SID_PCIE0 0x12 |
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| 39 | #define TEGRA234_SID_PCIE4 0x13 |
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| 40 | #define TEGRA234_SID_PCIE5 0x14 |
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| 41 | #define TEGRA234_SID_PCIE6 0x15 |
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| 42 | #define TEGRA234_SID_RCE_VM2 0x16 |
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| 43 | #define TEGRA234_SID_RCE_SERVER 0x17 |
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| 44 | #define TEGRA234_SID_SMMU_TEST 0x18 |
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| 45 | #define TEGRA234_SID_UFS_1 0x19 |
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| 46 | #define TEGRA234_SID_UFS_2 0x1a |
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| 47 | #define TEGRA234_SID_UFS_3 0x1b |
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| 48 | #define TEGRA234_SID_UFS_4 0x1c |
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| 49 | #define TEGRA234_SID_UFS_5 0x1d |
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| 50 | #define TEGRA234_SID_UFS_6 0x1e |
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| 51 | #define TEGRA234_SID_PCIE9 0x1f |
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| 52 | #define TEGRA234_SID_VSE_GPCDMA_VM0 0x20 |
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| 53 | #define TEGRA234_SID_VSE_GPCDMA_VM1 0x21 |
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| 54 | #define TEGRA234_SID_VSE_GPCDMA_VM2 0x22 |
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| 55 | #define TEGRA234_SID_NVDLA1 0x23 |
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| 56 | #define TEGRA234_SID_NVENC 0x24 |
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| 57 | #define TEGRA234_SID_NVJPG1 0x25 |
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| 58 | #define TEGRA234_SID_OFA 0x26 |
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| 59 | #define TEGRA234_SID_MGBE_VF1 0x49 |
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| 60 | #define TEGRA234_SID_MGBE_VF2 0x4a |
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| 61 | #define TEGRA234_SID_MGBE_VF3 0x4b |
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| 62 | #define TEGRA234_SID_MGBE_VF4 0x4c |
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| 63 | #define TEGRA234_SID_MGBE_VF5 0x4d |
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| 64 | #define TEGRA234_SID_MGBE_VF6 0x4e |
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| 65 | #define TEGRA234_SID_MGBE_VF7 0x4f |
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| 66 | #define TEGRA234_SID_MGBE_VF8 0x50 |
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| 67 | #define TEGRA234_SID_MGBE_VF9 0x51 |
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| 68 | #define TEGRA234_SID_MGBE_VF10 0x52 |
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| 69 | #define TEGRA234_SID_MGBE_VF11 0x53 |
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| 70 | #define TEGRA234_SID_MGBE_VF12 0x54 |
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| 71 | #define TEGRA234_SID_MGBE_VF13 0x55 |
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| 72 | #define TEGRA234_SID_MGBE_VF14 0x56 |
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| 73 | #define TEGRA234_SID_MGBE_VF15 0x57 |
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| 74 | #define TEGRA234_SID_MGBE_VF16 0x58 |
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| 75 | #define TEGRA234_SID_MGBE_VF17 0x59 |
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| 76 | #define TEGRA234_SID_MGBE_VF18 0x5a |
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| 77 | #define TEGRA234_SID_MGBE_VF19 0x5b |
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| 78 | #define TEGRA234_SID_MGBE_VF20 0x5c |
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| 79 | #define TEGRA234_SID_APE_2 0x5e |
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| 80 | #define TEGRA234_SID_APE_3 0x5f |
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| 81 | #define TEGRA234_SID_UFS_7 0x60 |
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| 82 | #define TEGRA234_SID_UFS_8 0x61 |
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| 83 | #define TEGRA234_SID_UFS_9 0x62 |
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| 84 | #define TEGRA234_SID_UFS_10 0x63 |
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| 85 | #define TEGRA234_SID_UFS_11 0x64 |
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| 86 | #define TEGRA234_SID_UFS_12 0x65 |
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| 87 | #define TEGRA234_SID_UFS_13 0x66 |
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| 88 | #define TEGRA234_SID_UFS_14 0x67 |
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| 89 | #define TEGRA234_SID_UFS_15 0x68 |
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| 90 | #define TEGRA234_SID_UFS_16 0x69 |
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| 91 | #define TEGRA234_SID_UFS_17 0x6a |
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| 92 | #define TEGRA234_SID_UFS_18 0x6b |
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| 93 | #define TEGRA234_SID_UFS_19 0x6c |
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| 94 | #define TEGRA234_SID_UFS_20 0x6d |
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| 95 | #define TEGRA234_SID_GPCDMA_5 0x6e |
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| 96 | #define TEGRA234_SID_GPCDMA_6 0x6f |
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| 97 | #define TEGRA234_SID_GPCDMA_7 0x70 |
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| 98 | #define TEGRA234_SID_GPCDMA_8 0x71 |
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| 99 | #define TEGRA234_SID_GPCDMA_9 0x72 |
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| 100 | |
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| 101 | /* NISO1 stream IDs */ |
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| 102 | #define TEGRA234_SID_SDMMC1A 0x01 |
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| 103 | #define TEGRA234_SID_SDMMC4 0x02 |
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| 104 | #define TEGRA234_SID_EQOS 0x03 |
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| 105 | #define TEGRA234_SID_HWMP_PMA 0x04 |
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| 106 | #define TEGRA234_SID_PCIE1 0x05 |
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| 107 | #define TEGRA234_SID_PCIE2 0x06 |
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| 108 | #define TEGRA234_SID_PCIE3 0x07 |
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| 109 | #define TEGRA234_SID_PCIE7 0x08 |
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| 110 | #define TEGRA234_SID_PCIE8 0x09 |
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| 111 | #define TEGRA234_SID_PCIE10 0x0b |
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| 112 | #define TEGRA234_SID_QSPI0 0x0c |
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| 113 | #define TEGRA234_SID_QSPI1 0x0d |
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| 114 | #define TEGRA234_SID_XUSB_HOST 0x0e |
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| 115 | #define TEGRA234_SID_XUSB_DEV 0x0f |
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| 116 | #define TEGRA234_SID_BPMP 0x10 |
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| 117 | #define TEGRA234_SID_FSI 0x11 |
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| 118 | #define TEGRA234_SID_PVA0_VM0 0x12 |
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| 119 | #define TEGRA234_SID_PVA0_VM1 0x13 |
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| 120 | #define TEGRA234_SID_PVA0_VM2 0x14 |
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| 121 | #define TEGRA234_SID_PVA0_VM3 0x15 |
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| 122 | #define TEGRA234_SID_PVA0_VM4 0x16 |
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| 123 | #define TEGRA234_SID_PVA0_VM5 0x17 |
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| 124 | #define TEGRA234_SID_PVA0_VM6 0x18 |
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| 125 | #define TEGRA234_SID_PVA0_VM7 0x19 |
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| 126 | #define TEGRA234_SID_XUSB_VF0 0x1a |
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| 127 | #define TEGRA234_SID_XUSB_VF1 0x1b |
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| 128 | #define TEGRA234_SID_XUSB_VF2 0x1c |
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| 129 | #define TEGRA234_SID_XUSB_VF3 0x1d |
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| 130 | #define TEGRA234_SID_EQOS_VF1 0x1e |
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| 131 | #define TEGRA234_SID_EQOS_VF2 0x1f |
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| 132 | #define TEGRA234_SID_EQOS_VF3 0x20 |
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| 133 | #define TEGRA234_SID_EQOS_VF4 0x21 |
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| 134 | #define TEGRA234_SID_ISP_VM2 0x22 |
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| 135 | #define TEGRA234_SID_HOST1X 0x27 |
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| 136 | #define TEGRA234_SID_ISP 0x28 |
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| 137 | #define TEGRA234_SID_NVDEC 0x29 |
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| 138 | #define TEGRA234_SID_NVJPG 0x2a |
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| 139 | #define TEGRA234_SID_NVDLA0 0x2b |
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| 140 | #define TEGRA234_SID_PVA0 0x2c |
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| 141 | #define TEGRA234_SID_SES_SE0 0x2d |
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| 142 | #define TEGRA234_SID_SES_SE1 0x2e |
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| 143 | #define TEGRA234_SID_SES_SE2 0x2f |
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| 144 | #define TEGRA234_SID_SEU1_SE0 0x30 |
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| 145 | #define TEGRA234_SID_SEU1_SE1 0x31 |
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| 146 | #define TEGRA234_SID_SEU1_SE2 0x32 |
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| 147 | #define TEGRA234_SID_TSEC 0x33 |
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| 148 | #define TEGRA234_SID_VIC 0x34 |
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| 149 | #define TEGRA234_SID_HC_VM0 0x3d |
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| 150 | #define TEGRA234_SID_HC_VM1 0x3e |
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| 151 | #define TEGRA234_SID_HC_VM2 0x3f |
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| 152 | #define TEGRA234_SID_HC_VM3 0x40 |
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| 153 | #define TEGRA234_SID_HC_VM4 0x41 |
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| 154 | #define TEGRA234_SID_HC_VM5 0x42 |
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| 155 | #define TEGRA234_SID_HC_VM6 0x43 |
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| 156 | #define TEGRA234_SID_HC_VM7 0x44 |
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| 157 | #define TEGRA234_SID_SE_VM0 0x45 |
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| 158 | #define TEGRA234_SID_SE_VM1 0x46 |
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| 159 | #define TEGRA234_SID_SE_VM2 0x47 |
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| 160 | #define TEGRA234_SID_ISPFALC 0x48 |
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| 161 | #define TEGRA234_SID_NISO1_SMMU_TEST 0x49 |
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| 162 | #define TEGRA234_SID_TSEC_VM0 0x4a |
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| 163 | |
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| 164 | /* Shared stream IDs */ |
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| 165 | #define TEGRA234_SID_HOST1X_CTX0 0x35 |
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| 166 | #define TEGRA234_SID_HOST1X_CTX1 0x36 |
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| 167 | #define TEGRA234_SID_HOST1X_CTX2 0x37 |
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| 168 | #define TEGRA234_SID_HOST1X_CTX3 0x38 |
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| 169 | #define TEGRA234_SID_HOST1X_CTX4 0x39 |
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| 170 | #define TEGRA234_SID_HOST1X_CTX5 0x3a |
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| 171 | #define TEGRA234_SID_HOST1X_CTX6 0x3b |
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| 172 | #define TEGRA234_SID_HOST1X_CTX7 0x3c |
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| 173 | |
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| 174 | /* |
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| 175 | * memory client IDs |
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| 176 | */ |
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| 177 | |
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| 178 | /* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ |
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| 179 | #define TEGRA234_MEMORY_CLIENT_PTCR 0x00 |
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| 180 | /* MSS internal memqual MIU7 read clients */ |
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| 181 | #define TEGRA234_MEMORY_CLIENT_MIU7R 0x01 |
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| 182 | /* MSS internal memqual MIU7 write clients */ |
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| 183 | #define TEGRA234_MEMORY_CLIENT_MIU7W 0x02 |
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| 184 | /* MSS internal memqual MIU8 read clients */ |
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| 185 | #define TEGRA234_MEMORY_CLIENT_MIU8R 0x03 |
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| 186 | /* MSS internal memqual MIU8 write clients */ |
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| 187 | #define TEGRA234_MEMORY_CLIENT_MIU8W 0x04 |
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| 188 | /* MSS internal memqual MIU9 read clients */ |
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| 189 | #define TEGRA234_MEMORY_CLIENT_MIU9R 0x05 |
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| 190 | /* MSS internal memqual MIU9 write clients */ |
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| 191 | #define TEGRA234_MEMORY_CLIENT_MIU9W 0x06 |
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| 192 | /* MSS internal memqual MIU10 read clients */ |
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| 193 | #define TEGRA234_MEMORY_CLIENT_MIU10R 0x07 |
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| 194 | /* MSS internal memqual MIU10 write clients */ |
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| 195 | #define TEGRA234_MEMORY_CLIENT_MIU10W 0x08 |
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| 196 | /* MSS internal memqual MIU11 read clients */ |
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| 197 | #define TEGRA234_MEMORY_CLIENT_MIU11R 0x09 |
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| 198 | /* MSS internal memqual MIU11 write clients */ |
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| 199 | #define TEGRA234_MEMORY_CLIENT_MIU11W 0x0a |
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| 200 | /* MSS internal memqual MIU12 read clients */ |
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| 201 | #define TEGRA234_MEMORY_CLIENT_MIU12R 0x0b |
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| 202 | /* MSS internal memqual MIU12 write clients */ |
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| 203 | #define TEGRA234_MEMORY_CLIENT_MIU12W 0x0c |
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| 204 | /* MSS internal memqual MIU13 read clients */ |
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| 205 | #define TEGRA234_MEMORY_CLIENT_MIU13R 0x0d |
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| 206 | /* MSS internal memqual MIU13 write clients */ |
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| 207 | #define TEGRA234_MEMORY_CLIENT_MIU13W 0x0e |
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| 208 | #define TEGRA234_MEMORY_CLIENT_NVL5RHP 0x13 |
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| 209 | #define TEGRA234_MEMORY_CLIENT_NVL5R 0x14 |
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| 210 | /* High-definition audio (HDA) read clients */ |
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| 211 | #define TEGRA234_MEMORY_CLIENT_HDAR 0x15 |
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| 212 | /* Host channel data read clients */ |
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| 213 | #define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16 |
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| 214 | #define TEGRA234_MEMORY_CLIENT_NVL5W 0x17 |
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| 215 | #define TEGRA234_MEMORY_CLIENT_NVL6RHP 0x18 |
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| 216 | #define TEGRA234_MEMORY_CLIENT_NVL6R 0x19 |
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| 217 | #define TEGRA234_MEMORY_CLIENT_NVL6W 0x1a |
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| 218 | #define TEGRA234_MEMORY_CLIENT_NVL7RHP 0x1b |
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| 219 | #define TEGRA234_MEMORY_CLIENT_NVENCSRD 0x1c |
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| 220 | #define TEGRA234_MEMORY_CLIENT_NVL7R 0x1d |
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| 221 | #define TEGRA234_MEMORY_CLIENT_NVL7W 0x1e |
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| 222 | #define TEGRA234_MEMORY_CLIENT_NVL8RHP 0x20 |
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| 223 | #define TEGRA234_MEMORY_CLIENT_NVL8R 0x21 |
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| 224 | #define TEGRA234_MEMORY_CLIENT_NVL8W 0x22 |
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| 225 | #define TEGRA234_MEMORY_CLIENT_NVL9RHP 0x23 |
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| 226 | #define TEGRA234_MEMORY_CLIENT_NVL9R 0x24 |
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| 227 | #define TEGRA234_MEMORY_CLIENT_NVL9W 0x25 |
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| 228 | /* PCIE6 read clients */ |
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| 229 | #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 |
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| 230 | /* PCIE6 write clients */ |
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| 231 | #define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 |
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| 232 | /* PCIE7 read clients */ |
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| 233 | #define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a |
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| 234 | #define TEGRA234_MEMORY_CLIENT_NVENCSWR 0x2b |
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| 235 | /* DLA0ARDB read clients */ |
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| 236 | #define TEGRA234_MEMORY_CLIENT_DLA0RDB 0x2c |
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| 237 | /* DLA0ARDB1 read clients */ |
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| 238 | #define TEGRA234_MEMORY_CLIENT_DLA0RDB1 0x2d |
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| 239 | /* DLA0 writes */ |
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| 240 | #define TEGRA234_MEMORY_CLIENT_DLA0WRB 0x2e |
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| 241 | /* DLA1ARDB read clients */ |
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| 242 | #define TEGRA234_MEMORY_CLIENT_DLA1RDB 0x2f |
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| 243 | /* PCIE7 write clients */ |
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| 244 | #define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30 |
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| 245 | /* PCIE8 read clients */ |
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| 246 | #define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32 |
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| 247 | /* High-definition audio (HDA) write clients */ |
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| 248 | #define TEGRA234_MEMORY_CLIENT_HDAW 0x35 |
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| 249 | /* Writes from Cortex-A9 4 CPU cores via the L2 cache */ |
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| 250 | #define TEGRA234_MEMORY_CLIENT_MPCOREW 0x39 |
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| 251 | /* OFAA client */ |
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| 252 | #define TEGRA234_MEMORY_CLIENT_OFAR1 0x3a |
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| 253 | /* PCIE8 write clients */ |
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| 254 | #define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b |
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| 255 | /* PCIE9 read clients */ |
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| 256 | #define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c |
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| 257 | /* PCIE6r1 read clients */ |
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| 258 | #define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d |
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| 259 | /* PCIE9 write clients */ |
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| 260 | #define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e |
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| 261 | /* PCIE10 read clients */ |
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| 262 | #define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f |
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| 263 | /* PCIE10 write clients */ |
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| 264 | #define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40 |
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| 265 | /* ISP read client for Crossbar A */ |
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| 266 | #define TEGRA234_MEMORY_CLIENT_ISPRA 0x44 |
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| 267 | /* ISP read client 1 for Crossbar A */ |
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| 268 | #define TEGRA234_MEMORY_CLIENT_ISPFALR 0x45 |
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| 269 | /* ISP Write client for Crossbar A */ |
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| 270 | #define TEGRA234_MEMORY_CLIENT_ISPWA 0x46 |
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| 271 | /* ISP Write client Crossbar B */ |
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| 272 | #define TEGRA234_MEMORY_CLIENT_ISPWB 0x47 |
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| 273 | /* PCIE10r1 read clients */ |
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| 274 | #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 |
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| 275 | /* PCIE7r1 read clients */ |
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| 276 | #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 |
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| 277 | /* XUSB_HOST read clients */ |
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| 278 | #define TEGRA234_MEMORY_CLIENT_XUSB_HOSTR 0x4a |
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| 279 | /* XUSB_HOST write clients */ |
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| 280 | #define TEGRA234_MEMORY_CLIENT_XUSB_HOSTW 0x4b |
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| 281 | /* XUSB read clients */ |
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| 282 | #define TEGRA234_MEMORY_CLIENT_XUSB_DEVR 0x4c |
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| 283 | /* XUSB_DEV write clients */ |
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| 284 | #define TEGRA234_MEMORY_CLIENT_XUSB_DEVW 0x4d |
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| 285 | /* TSEC Memory Return Data Client Description */ |
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| 286 | #define TEGRA234_MEMORY_CLIENT_TSECSRD 0x54 |
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| 287 | /* TSEC Memory Write Client Description */ |
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| 288 | #define TEGRA234_MEMORY_CLIENT_TSECSWR 0x55 |
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| 289 | /* XSPI writes */ |
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| 290 | #define TEGRA234_MEMORY_CLIENT_XSPI1W 0x56 |
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| 291 | /* MGBE0 read client */ |
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| 292 | #define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58 |
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| 293 | /* MGBEB read client */ |
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| 294 | #define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59 |
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| 295 | /* MGBEC read client */ |
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| 296 | #define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a |
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| 297 | /* MGBED read client */ |
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| 298 | #define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b |
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| 299 | /* MGBE0 write client */ |
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| 300 | #define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c |
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| 301 | /* OFAA client */ |
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| 302 | #define TEGRA234_MEMORY_CLIENT_OFAR 0x5d |
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| 303 | /* OFAA writes */ |
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| 304 | #define TEGRA234_MEMORY_CLIENT_OFAW 0x5e |
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| 305 | /* MGBEB write client */ |
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| 306 | #define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f |
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| 307 | /* sdmmca memory read client */ |
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| 308 | #define TEGRA234_MEMORY_CLIENT_SDMMCRA 0x60 |
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| 309 | /* MGBEC write client */ |
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| 310 | #define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61 |
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| 311 | /* sdmmcd memory read client */ |
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| 312 | #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 |
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| 313 | /* sdmmca memory write client */ |
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| 314 | #define TEGRA234_MEMORY_CLIENT_SDMMCWA 0x64 |
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| 315 | /* MGBED write client */ |
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| 316 | #define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 |
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| 317 | /* sdmmcd memory write client */ |
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| 318 | #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 |
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| 319 | /* SE Memory Return Data Client Description */ |
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| 320 | #define TEGRA234_MEMORY_CLIENT_SEU1RD 0x68 |
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| 321 | /* SE Memory Write Client Description */ |
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| 322 | #define TEGRA234_MEMORY_CLIENT_SUE1WR 0x69 |
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| 323 | #define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c |
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| 324 | #define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d |
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| 325 | /* DLA1ARDB1 read clients */ |
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| 326 | #define TEGRA234_MEMORY_CLIENT_DLA1RDB1 0x6e |
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| 327 | /* DLA1 writes */ |
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| 328 | #define TEGRA234_MEMORY_CLIENT_DLA1WRB 0x6f |
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| 329 | /* VI FLACON read clients */ |
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| 330 | #define TEGRA234_MEMORY_CLIENT_VI2FALR 0x71 |
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| 331 | /* VI Write client */ |
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| 332 | #define TEGRA234_MEMORY_CLIENT_VI2W 0x70 |
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| 333 | /* VI Write client */ |
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| 334 | #define TEGRA234_MEMORY_CLIENT_VIW 0x72 |
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| 335 | /* NISO display read client */ |
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| 336 | #define TEGRA234_MEMORY_CLIENT_NVDISPNISOR 0x73 |
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| 337 | /* NVDISPNISO writes */ |
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| 338 | #define TEGRA234_MEMORY_CLIENT_NVDISPNISOW 0x74 |
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| 339 | /* XSPI client */ |
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| 340 | #define TEGRA234_MEMORY_CLIENT_XSPI0R 0x75 |
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| 341 | /* XSPI writes */ |
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| 342 | #define TEGRA234_MEMORY_CLIENT_XSPI0W 0x76 |
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| 343 | /* XSPI client */ |
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| 344 | #define TEGRA234_MEMORY_CLIENT_XSPI1R 0x77 |
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| 345 | #define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78 |
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| 346 | #define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79 |
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| 347 | /* Audio Processing (APE) engine read clients */ |
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| 348 | #define TEGRA234_MEMORY_CLIENT_APER 0x7a |
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| 349 | /* Audio Processing (APE) engine write clients */ |
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| 350 | #define TEGRA234_MEMORY_CLIENT_APEW 0x7b |
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| 351 | /* VI2FAL writes */ |
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| 352 | #define TEGRA234_MEMORY_CLIENT_VI2FALW 0x7c |
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| 353 | #define TEGRA234_MEMORY_CLIENT_NVJPGSRD 0x7e |
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| 354 | #define TEGRA234_MEMORY_CLIENT_NVJPGSWR 0x7f |
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| 355 | /* SE Memory Return Data Client Description */ |
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| 356 | #define TEGRA234_MEMORY_CLIENT_SESRD 0x80 |
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| 357 | /* SE Memory Write Client Description */ |
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| 358 | #define TEGRA234_MEMORY_CLIENT_SESWR 0x81 |
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| 359 | /* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ |
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| 360 | #define TEGRA234_MEMORY_CLIENT_AXIAPR 0x82 |
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| 361 | /* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ |
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| 362 | #define TEGRA234_MEMORY_CLIENT_AXIAPW 0x83 |
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| 363 | /* ETR read clients */ |
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| 364 | #define TEGRA234_MEMORY_CLIENT_ETRR 0x84 |
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| 365 | /* ETR write clients */ |
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| 366 | #define TEGRA234_MEMORY_CLIENT_ETRW 0x85 |
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| 367 | /* AXI Switch read client */ |
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| 368 | #define TEGRA234_MEMORY_CLIENT_AXISR 0x8c |
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| 369 | /* AXI Switch write client */ |
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| 370 | #define TEGRA234_MEMORY_CLIENT_AXISW 0x8d |
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| 371 | /* EQOS read client */ |
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| 372 | #define TEGRA234_MEMORY_CLIENT_EQOSR 0x8e |
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| 373 | /* EQOS write client */ |
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| 374 | #define TEGRA234_MEMORY_CLIENT_EQOSW 0x8f |
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| 375 | /* UFSHC read client */ |
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| 376 | #define TEGRA234_MEMORY_CLIENT_UFSHCR 0x90 |
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| 377 | /* UFSHC write client */ |
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| 378 | #define TEGRA234_MEMORY_CLIENT_UFSHCW 0x91 |
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| 379 | /* NVDISPLAY read client */ |
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| 380 | #define TEGRA234_MEMORY_CLIENT_NVDISPLAYR 0x92 |
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| 381 | /* BPMP read client */ |
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| 382 | #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 |
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| 383 | /* BPMP write client */ |
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| 384 | #define TEGRA234_MEMORY_CLIENT_BPMPW 0x94 |
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| 385 | /* BPMPDMA read client */ |
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| 386 | #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 |
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| 387 | /* BPMPDMA write client */ |
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| 388 | #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 |
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| 389 | /* AON read client */ |
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| 390 | #define TEGRA234_MEMORY_CLIENT_AONR 0x97 |
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| 391 | /* AON write client */ |
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| 392 | #define TEGRA234_MEMORY_CLIENT_AONW 0x98 |
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| 393 | /* AONDMA read client */ |
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| 394 | #define TEGRA234_MEMORY_CLIENT_AONDMAR 0x99 |
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| 395 | /* AONDMA write client */ |
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| 396 | #define TEGRA234_MEMORY_CLIENT_AONDMAW 0x9a |
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| 397 | /* SCE read client */ |
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| 398 | #define TEGRA234_MEMORY_CLIENT_SCER 0x9b |
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| 399 | /* SCE write client */ |
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| 400 | #define TEGRA234_MEMORY_CLIENT_SCEW 0x9c |
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| 401 | /* SCEDMA read client */ |
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| 402 | #define TEGRA234_MEMORY_CLIENT_SCEDMAR 0x9d |
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| 403 | /* SCEDMA write client */ |
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| 404 | #define TEGRA234_MEMORY_CLIENT_SCEDMAW 0x9e |
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| 405 | /* APEDMA read client */ |
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| 406 | #define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f |
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| 407 | /* APEDMA write client */ |
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| 408 | #define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0 |
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| 409 | /* NVDISPLAY read client instance 2 */ |
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| 410 | #define TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 0xa1 |
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| 411 | #define TEGRA234_MEMORY_CLIENT_VICSRD1 0xa2 |
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| 412 | /* MSS internal memqual MIU0 read clients */ |
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| 413 | #define TEGRA234_MEMORY_CLIENT_MIU0R 0xa6 |
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| 414 | /* MSS internal memqual MIU0 write clients */ |
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| 415 | #define TEGRA234_MEMORY_CLIENT_MIU0W 0xa7 |
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| 416 | /* MSS internal memqual MIU1 read clients */ |
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| 417 | #define TEGRA234_MEMORY_CLIENT_MIU1R 0xa8 |
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| 418 | /* MSS internal memqual MIU1 write clients */ |
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| 419 | #define TEGRA234_MEMORY_CLIENT_MIU1W 0xa9 |
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| 420 | /* MSS internal memqual MIU2 read clients */ |
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| 421 | #define TEGRA234_MEMORY_CLIENT_MIU2R 0xae |
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| 422 | /* MSS internal memqual MIU2 write clients */ |
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| 423 | #define TEGRA234_MEMORY_CLIENT_MIU2W 0xaf |
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| 424 | /* MSS internal memqual MIU3 read clients */ |
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| 425 | #define TEGRA234_MEMORY_CLIENT_MIU3R 0xb0 |
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| 426 | /* MSS internal memqual MIU3 write clients */ |
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| 427 | #define TEGRA234_MEMORY_CLIENT_MIU3W 0xb1 |
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| 428 | /* MSS internal memqual MIU4 read clients */ |
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| 429 | #define TEGRA234_MEMORY_CLIENT_MIU4R 0xb2 |
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| 430 | /* MSS internal memqual MIU4 write clients */ |
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| 431 | #define TEGRA234_MEMORY_CLIENT_MIU4W 0xb3 |
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| 432 | #define TEGRA234_MEMORY_CLIENT_DPMUR 0xb4 |
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| 433 | #define TEGRA234_MEMORY_CLIENT_DPMUW 0xb5 |
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| 434 | #define TEGRA234_MEMORY_CLIENT_NVL0R 0xb6 |
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| 435 | #define TEGRA234_MEMORY_CLIENT_NVL0W 0xb7 |
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| 436 | #define TEGRA234_MEMORY_CLIENT_NVL1R 0xb8 |
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| 437 | #define TEGRA234_MEMORY_CLIENT_NVL1W 0xb9 |
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| 438 | #define TEGRA234_MEMORY_CLIENT_NVL2R 0xba |
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| 439 | #define TEGRA234_MEMORY_CLIENT_NVL2W 0xbb |
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| 440 | /* VI FLACON read clients */ |
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| 441 | #define TEGRA234_MEMORY_CLIENT_VIFALR 0xbc |
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| 442 | /* VIFAL write clients */ |
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| 443 | #define TEGRA234_MEMORY_CLIENT_VIFALW 0xbd |
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| 444 | /* DLA0ARDA read clients */ |
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| 445 | #define TEGRA234_MEMORY_CLIENT_DLA0RDA 0xbe |
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| 446 | /* DLA0 Falcon read clients */ |
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| 447 | #define TEGRA234_MEMORY_CLIENT_DLA0FALRDB 0xbf |
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| 448 | /* DLA0 write clients */ |
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| 449 | #define TEGRA234_MEMORY_CLIENT_DLA0WRA 0xc0 |
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| 450 | /* DLA0 write clients */ |
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| 451 | #define TEGRA234_MEMORY_CLIENT_DLA0FALWRB 0xc1 |
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| 452 | /* DLA1ARDA read clients */ |
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| 453 | #define TEGRA234_MEMORY_CLIENT_DLA1RDA 0xc2 |
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| 454 | /* DLA1 Falcon read clients */ |
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| 455 | #define TEGRA234_MEMORY_CLIENT_DLA1FALRDB 0xc3 |
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| 456 | /* DLA1 write clients */ |
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| 457 | #define TEGRA234_MEMORY_CLIENT_DLA1WRA 0xc4 |
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| 458 | /* DLA1 write clients */ |
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| 459 | #define TEGRA234_MEMORY_CLIENT_DLA1FALWRB 0xc5 |
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| 460 | /* PVA0RDA read clients */ |
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| 461 | #define TEGRA234_MEMORY_CLIENT_PVA0RDA 0xc6 |
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| 462 | /* PVA0RDB read clients */ |
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| 463 | #define TEGRA234_MEMORY_CLIENT_PVA0RDB 0xc7 |
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| 464 | /* PVA0RDC read clients */ |
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| 465 | #define TEGRA234_MEMORY_CLIENT_PVA0RDC 0xc8 |
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| 466 | /* PVA0WRA write clients */ |
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| 467 | #define TEGRA234_MEMORY_CLIENT_PVA0WRA 0xc9 |
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| 468 | /* PVA0WRB write clients */ |
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| 469 | #define TEGRA234_MEMORY_CLIENT_PVA0WRB 0xca |
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| 470 | /* PVA0WRC write clients */ |
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| 471 | #define TEGRA234_MEMORY_CLIENT_PVA0WRC 0xcb |
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| 472 | /* RCE read client */ |
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| 473 | #define TEGRA234_MEMORY_CLIENT_RCER 0xd2 |
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| 474 | /* RCE write client */ |
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| 475 | #define TEGRA234_MEMORY_CLIENT_RCEW 0xd3 |
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| 476 | /* RCEDMA read client */ |
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| 477 | #define TEGRA234_MEMORY_CLIENT_RCEDMAR 0xd4 |
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| 478 | /* RCEDMA write client */ |
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| 479 | #define TEGRA234_MEMORY_CLIENT_RCEDMAW 0xd5 |
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| 480 | /* PCIE0 read clients */ |
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| 481 | #define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8 |
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| 482 | /* PCIE0 write clients */ |
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| 483 | #define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9 |
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| 484 | /* PCIE1 read clients */ |
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| 485 | #define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda |
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| 486 | /* PCIE1 write clients */ |
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| 487 | #define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb |
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| 488 | /* PCIE2 read clients */ |
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| 489 | #define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc |
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| 490 | /* PCIE2 write clients */ |
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| 491 | #define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd |
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| 492 | /* PCIE3 read clients */ |
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| 493 | #define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde |
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| 494 | /* PCIE3 write clients */ |
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| 495 | #define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf |
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| 496 | /* PCIE4 read clients */ |
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| 497 | #define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0 |
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| 498 | /* PCIE4 write clients */ |
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| 499 | #define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1 |
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| 500 | /* PCIE5 read clients */ |
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| 501 | #define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2 |
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| 502 | /* PCIE5 write clients */ |
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| 503 | #define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3 |
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| 504 | /* ISP read client 1 for Crossbar A */ |
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| 505 | #define TEGRA234_MEMORY_CLIENT_ISPFALW 0xe4 |
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| 506 | #define TEGRA234_MEMORY_CLIENT_NVL3R 0xe5 |
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| 507 | #define TEGRA234_MEMORY_CLIENT_NVL3W 0xe6 |
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| 508 | #define TEGRA234_MEMORY_CLIENT_NVL4R 0xe7 |
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| 509 | #define TEGRA234_MEMORY_CLIENT_NVL4W 0xe8 |
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| 510 | /* DLA0ARDA1 read clients */ |
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| 511 | #define TEGRA234_MEMORY_CLIENT_DLA0RDA1 0xe9 |
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| 512 | /* DLA1ARDA1 read clients */ |
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| 513 | #define TEGRA234_MEMORY_CLIENT_DLA1RDA1 0xea |
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| 514 | /* PVA0RDA1 read clients */ |
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| 515 | #define TEGRA234_MEMORY_CLIENT_PVA0RDA1 0xeb |
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| 516 | /* PVA0RDB1 read clients */ |
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| 517 | #define TEGRA234_MEMORY_CLIENT_PVA0RDB1 0xec |
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| 518 | /* PCIE5r1 read clients */ |
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| 519 | #define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef |
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| 520 | #define TEGRA234_MEMORY_CLIENT_NVENCSRD1 0xf0 |
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| 521 | /* ISP read client for Crossbar A */ |
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| 522 | #define TEGRA234_MEMORY_CLIENT_ISPRA1 0xf2 |
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| 523 | #define TEGRA234_MEMORY_CLIENT_NVL0RHP 0xf4 |
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| 524 | #define TEGRA234_MEMORY_CLIENT_NVL1RHP 0xf5 |
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| 525 | #define TEGRA234_MEMORY_CLIENT_NVL2RHP 0xf6 |
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| 526 | #define TEGRA234_MEMORY_CLIENT_NVL3RHP 0xf7 |
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| 527 | #define TEGRA234_MEMORY_CLIENT_NVL4RHP 0xf8 |
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| 528 | /* MSS internal memqual MIU5 read clients */ |
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| 529 | #define TEGRA234_MEMORY_CLIENT_MIU5R 0xfc |
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| 530 | /* MSS internal memqual MIU5 write clients */ |
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| 531 | #define TEGRA234_MEMORY_CLIENT_MIU5W 0xfd |
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| 532 | /* MSS internal memqual MIU6 read clients */ |
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| 533 | #define TEGRA234_MEMORY_CLIENT_MIU6R 0xfe |
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| 534 | /* MSS internal memqual MIU6 write clients */ |
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| 535 | #define TEGRA234_MEMORY_CLIENT_MIU6W 0xff |
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| 536 | #define TEGRA234_MEMORY_CLIENT_NVJPG1SRD 0x123 |
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| 537 | #define TEGRA234_MEMORY_CLIENT_NVJPG1SWR 0x124 |
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| 538 | |
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| 539 | /* ICC ID's for dummy MC clients used to represent CPU Clusters */ |
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| 540 | #define TEGRA_ICC_MC_CPU_CLUSTER0 1003 |
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| 541 | #define TEGRA_ICC_MC_CPU_CLUSTER1 1004 |
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| 542 | #define TEGRA_ICC_MC_CPU_CLUSTER2 1005 |
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| 543 | |
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| 544 | #endif |
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| 545 | |
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