1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright (C) 2018 Xilinx, Inc. |
4 | */ |
5 | |
6 | #ifndef _DT_BINDINGS_ZYNQMP_POWER_H |
7 | #define _DT_BINDINGS_ZYNQMP_POWER_H |
8 | |
9 | #define PD_RPU_0 7 |
10 | #define PD_RPU_1 8 |
11 | #define PD_R5_0_ATCM 15 |
12 | #define PD_R5_0_BTCM 16 |
13 | #define PD_R5_1_ATCM 17 |
14 | #define PD_R5_1_BTCM 18 |
15 | #define PD_USB_0 22 |
16 | #define PD_USB_1 23 |
17 | #define PD_TTC_0 24 |
18 | #define PD_TTC_1 25 |
19 | #define PD_TTC_2 26 |
20 | #define PD_TTC_3 27 |
21 | #define PD_SATA 28 |
22 | #define PD_ETH_0 29 |
23 | #define PD_ETH_1 30 |
24 | #define PD_ETH_2 31 |
25 | #define PD_ETH_3 32 |
26 | #define PD_UART_0 33 |
27 | #define PD_UART_1 34 |
28 | #define PD_SPI_0 35 |
29 | #define PD_SPI_1 36 |
30 | #define PD_I2C_0 37 |
31 | #define PD_I2C_1 38 |
32 | #define PD_SD_0 39 |
33 | #define PD_SD_1 40 |
34 | #define PD_DP 41 |
35 | #define PD_GDMA 42 |
36 | #define PD_ADMA 43 |
37 | #define PD_NAND 44 |
38 | #define PD_QSPI 45 |
39 | #define PD_GPIO 46 |
40 | #define PD_CAN_0 47 |
41 | #define PD_CAN_1 48 |
42 | #define PD_GPU 58 |
43 | #define PD_PCIE 59 |
44 | |
45 | #endif |
46 | |