| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright Intel Corporation (C) 2017. All Rights Reserved |
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| 4 | * |
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| 5 | * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip |
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| 6 | * |
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| 7 | * Adapted from altr,rst-mgr-a10.h |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H |
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| 11 | #define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H |
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| 12 | |
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| 13 | /* Peripheral PHY resets */ |
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| 14 | #define A10SR_RESET_ENET_HPS 0 |
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| 15 | #define A10SR_RESET_PCIE 1 |
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| 16 | #define A10SR_RESET_FILE 2 |
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| 17 | #define A10SR_RESET_BQSPI 3 |
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| 18 | #define A10SR_RESET_USB 4 |
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| 19 | |
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| 20 | #define A10SR_RESET_NUM 5 |
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| 21 | |
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| 22 | #endif |
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| 23 | |
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