| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC |
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| 4 | * |
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| 5 | * Baikal-T1 CCU reset indices |
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| 6 | */ |
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| 7 | #ifndef __DT_BINDINGS_RESET_BT1_CCU_H |
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| 8 | #define __DT_BINDINGS_RESET_BT1_CCU_H |
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| 9 | |
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| 10 | #define CCU_AXI_MAIN_RST 0 |
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| 11 | #define CCU_AXI_DDR_RST 1 |
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| 12 | #define CCU_AXI_SATA_RST 2 |
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| 13 | #define CCU_AXI_GMAC0_RST 3 |
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| 14 | #define CCU_AXI_GMAC1_RST 4 |
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| 15 | #define CCU_AXI_XGMAC_RST 5 |
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| 16 | #define CCU_AXI_PCIE_M_RST 6 |
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| 17 | #define CCU_AXI_PCIE_S_RST 7 |
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| 18 | #define CCU_AXI_USB_RST 8 |
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| 19 | #define CCU_AXI_HWA_RST 9 |
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| 20 | #define CCU_AXI_SRAM_RST 10 |
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| 21 | |
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| 22 | #define CCU_SYS_SATA_REF_RST 0 |
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| 23 | #define CCU_SYS_APB_RST 1 |
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| 24 | #define CCU_SYS_DDR_FULL_RST 2 |
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| 25 | #define CCU_SYS_DDR_INIT_RST 3 |
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| 26 | #define CCU_SYS_PCIE_PCS_PHY_RST 4 |
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| 27 | #define CCU_SYS_PCIE_PIPE0_RST 5 |
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| 28 | #define CCU_SYS_PCIE_CORE_RST 6 |
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| 29 | #define CCU_SYS_PCIE_PWR_RST 7 |
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| 30 | #define CCU_SYS_PCIE_STICKY_RST 8 |
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| 31 | #define CCU_SYS_PCIE_NSTICKY_RST 9 |
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| 32 | #define CCU_SYS_PCIE_HOT_RST 10 |
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| 33 | |
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| 34 | #endif /* __DT_BINDINGS_RESET_BT1_CCU_H */ |
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| 35 | |
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