| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2017 Impinj, Inc. |
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| 4 | * |
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| 5 | * Author: Andrey Smirnov <andrew.smirnov@gmail.com> |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef DT_BINDING_RESET_IMX7_H |
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| 9 | #define DT_BINDING_RESET_IMX7_H |
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| 10 | |
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| 11 | #define IMX7_RESET_A7_CORE_POR_RESET0 0 |
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| 12 | #define IMX7_RESET_A7_CORE_POR_RESET1 1 |
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| 13 | #define IMX7_RESET_A7_CORE_RESET0 2 |
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| 14 | #define IMX7_RESET_A7_CORE_RESET1 3 |
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| 15 | #define IMX7_RESET_A7_DBG_RESET0 4 |
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| 16 | #define IMX7_RESET_A7_DBG_RESET1 5 |
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| 17 | #define IMX7_RESET_A7_ETM_RESET0 6 |
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| 18 | #define IMX7_RESET_A7_ETM_RESET1 7 |
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| 19 | #define IMX7_RESET_A7_SOC_DBG_RESET 8 |
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| 20 | #define IMX7_RESET_A7_L2RESET 9 |
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| 21 | #define IMX7_RESET_SW_M4C_RST 10 |
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| 22 | #define IMX7_RESET_SW_M4P_RST 11 |
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| 23 | #define IMX7_RESET_EIM_RST 12 |
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| 24 | #define IMX7_RESET_HSICPHY_PORT_RST 13 |
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| 25 | #define IMX7_RESET_USBPHY1_POR 14 |
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| 26 | #define IMX7_RESET_USBPHY1_PORT_RST 15 |
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| 27 | #define IMX7_RESET_USBPHY2_POR 16 |
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| 28 | #define IMX7_RESET_USBPHY2_PORT_RST 17 |
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| 29 | #define IMX7_RESET_MIPI_PHY_MRST 18 |
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| 30 | #define IMX7_RESET_MIPI_PHY_SRST 19 |
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| 31 | |
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| 32 | /* |
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| 33 | * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN |
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| 34 | * and PCIEPHY_G_RST |
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| 35 | */ |
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| 36 | #define IMX7_RESET_PCIEPHY 20 |
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| 37 | #define IMX7_RESET_PCIEPHY_PERST 21 |
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| 38 | |
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| 39 | /* |
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| 40 | * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it |
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| 41 | * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht |
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| 42 | * of as one |
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| 43 | */ |
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| 44 | #define IMX7_RESET_PCIE_CTRL_APPS_EN 22 |
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| 45 | #define IMX7_RESET_DDRC_PRST 23 |
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| 46 | #define IMX7_RESET_DDRC_CORE_RST 24 |
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| 47 | |
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| 48 | #define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25 |
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| 49 | |
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| 50 | #define IMX7_RESET_NUM 26 |
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| 51 | |
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| 52 | #endif |
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| 53 | |
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| 54 | |
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