| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com> |
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| 4 | * Copyright (c) 2020 Western Digital Corporation or its affiliates. |
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| 5 | */ |
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| 6 | #ifndef RESET_K210_SYSCTL_H |
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| 7 | #define RESET_K210_SYSCTL_H |
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| 8 | |
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| 9 | /* |
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| 10 | * Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits. |
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| 11 | * Taken from Kendryte SDK (kendryte-standalone-sdk). |
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| 12 | */ |
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| 13 | #define K210_RST_ROM 0 |
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| 14 | #define K210_RST_DMA 1 |
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| 15 | #define K210_RST_AI 2 |
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| 16 | #define K210_RST_DVP 3 |
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| 17 | #define K210_RST_FFT 4 |
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| 18 | #define K210_RST_GPIO 5 |
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| 19 | #define K210_RST_SPI0 6 |
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| 20 | #define K210_RST_SPI1 7 |
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| 21 | #define K210_RST_SPI2 8 |
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| 22 | #define K210_RST_SPI3 9 |
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| 23 | #define K210_RST_I2S0 10 |
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| 24 | #define K210_RST_I2S1 11 |
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| 25 | #define K210_RST_I2S2 12 |
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| 26 | #define K210_RST_I2C0 13 |
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| 27 | #define K210_RST_I2C1 14 |
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| 28 | #define K210_RST_I2C2 15 |
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| 29 | #define K210_RST_UART1 16 |
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| 30 | #define K210_RST_UART2 17 |
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| 31 | #define K210_RST_UART3 18 |
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| 32 | #define K210_RST_AES 19 |
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| 33 | #define K210_RST_FPIOA 20 |
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| 34 | #define K210_RST_TIMER0 21 |
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| 35 | #define K210_RST_TIMER1 22 |
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| 36 | #define K210_RST_TIMER2 23 |
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| 37 | #define K210_RST_WDT0 24 |
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| 38 | #define K210_RST_WDT1 25 |
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| 39 | #define K210_RST_SHA 26 |
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| 40 | #define K210_RST_RTC 29 |
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| 41 | |
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| 42 | #endif /* RESET_K210_SYSCTL_H */ |
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| 43 | |
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