| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2020 MediaTek Inc. |
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| 4 | * Author: Yong Liang <yong.liang@mediatek.com> |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 |
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| 8 | #define _DT_BINDINGS_RESET_CONTROLLER_MT8192 |
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| 9 | |
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| 10 | /* TOPRGU resets */ |
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| 11 | #define MT8192_TOPRGU_MM_SW_RST 1 |
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| 12 | #define MT8192_TOPRGU_MFG_SW_RST 2 |
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| 13 | #define MT8192_TOPRGU_VENC_SW_RST 3 |
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| 14 | #define MT8192_TOPRGU_VDEC_SW_RST 4 |
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| 15 | #define MT8192_TOPRGU_IMG_SW_RST 5 |
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| 16 | #define MT8192_TOPRGU_MD_SW_RST 7 |
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| 17 | #define MT8192_TOPRGU_CONN_SW_RST 9 |
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| 18 | #define MT8192_TOPRGU_CONN_MCU_SW_RST 12 |
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| 19 | #define MT8192_TOPRGU_IPU0_SW_RST 14 |
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| 20 | #define MT8192_TOPRGU_IPU1_SW_RST 15 |
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| 21 | #define MT8192_TOPRGU_AUDIO_SW_RST 17 |
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| 22 | #define MT8192_TOPRGU_CAMSYS_SW_RST 18 |
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| 23 | #define MT8192_TOPRGU_MJC_SW_RST 19 |
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| 24 | #define MT8192_TOPRGU_C2K_S2_SW_RST 20 |
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| 25 | #define MT8192_TOPRGU_C2K_SW_RST 21 |
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| 26 | #define MT8192_TOPRGU_PERI_SW_RST 22 |
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| 27 | #define MT8192_TOPRGU_PERI_AO_SW_RST 23 |
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| 28 | |
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| 29 | #define MT8192_TOPRGU_SW_RST_NUM 23 |
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| 30 | |
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| 31 | /* MMSYS resets */ |
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| 32 | #define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15 |
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| 33 | |
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| 34 | /* INFRA resets */ |
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| 35 | #define MT8192_INFRA_RST0_THERM_CTRL_SWRST 0 |
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| 36 | #define MT8192_INFRA_RST2_PEXTP_PHY_SWRST 1 |
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| 37 | #define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST 2 |
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| 38 | #define MT8192_INFRA_RST4_PCIE_TOP_SWRST 3 |
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| 39 | #define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST 4 |
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| 40 | |
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| 41 | #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ |
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| 42 | |
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