| 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2023 MediaTek Inc. |
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| 4 | * Author: Balsam CHIHI <bchihi@baylibre.com> |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef __MEDIATEK_LVTS_DT_H |
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| 8 | #define __MEDIATEK_LVTS_DT_H |
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| 9 | |
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| 10 | #define MT7988_CPU_0 0 |
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| 11 | #define MT7988_CPU_1 1 |
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| 12 | #define MT7988_ETH2P5G_0 2 |
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| 13 | #define MT7988_ETH2P5G_1 3 |
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| 14 | #define MT7988_TOPS_0 4 |
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| 15 | #define MT7988_TOPS_1 5 |
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| 16 | #define MT7988_ETHWARP_0 6 |
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| 17 | #define MT7988_ETHWARP_1 7 |
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| 18 | |
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| 19 | #define MT8195_MCU_BIG_CPU0 0 |
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| 20 | #define MT8195_MCU_BIG_CPU1 1 |
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| 21 | #define MT8195_MCU_BIG_CPU2 2 |
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| 22 | #define MT8195_MCU_BIG_CPU3 3 |
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| 23 | #define MT8195_MCU_LITTLE_CPU0 4 |
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| 24 | #define MT8195_MCU_LITTLE_CPU1 5 |
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| 25 | #define MT8195_MCU_LITTLE_CPU2 6 |
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| 26 | #define MT8195_MCU_LITTLE_CPU3 7 |
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| 27 | |
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| 28 | #define MT8195_AP_VPU0 8 |
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| 29 | #define MT8195_AP_VPU1 9 |
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| 30 | #define MT8195_AP_GPU0 10 |
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| 31 | #define MT8195_AP_GPU1 11 |
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| 32 | #define MT8195_AP_VDEC 12 |
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| 33 | #define MT8195_AP_IMG 13 |
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| 34 | #define MT8195_AP_INFRA 14 |
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| 35 | #define MT8195_AP_CAM0 15 |
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| 36 | #define MT8195_AP_CAM1 16 |
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| 37 | |
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| 38 | #define MT8192_MCU_BIG_CPU0 0 |
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| 39 | #define MT8192_MCU_BIG_CPU1 1 |
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| 40 | #define MT8192_MCU_BIG_CPU2 2 |
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| 41 | #define MT8192_MCU_BIG_CPU3 3 |
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| 42 | #define MT8192_MCU_LITTLE_CPU0 4 |
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| 43 | #define MT8192_MCU_LITTLE_CPU1 5 |
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| 44 | #define MT8192_MCU_LITTLE_CPU2 6 |
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| 45 | #define MT8192_MCU_LITTLE_CPU3 7 |
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| 46 | |
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| 47 | #define MT8192_AP_VPU0 8 |
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| 48 | #define MT8192_AP_VPU1 9 |
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| 49 | #define MT8192_AP_GPU0 10 |
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| 50 | #define MT8192_AP_GPU1 11 |
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| 51 | #define MT8192_AP_INFRA 12 |
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| 52 | #define MT8192_AP_CAM 13 |
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| 53 | #define MT8192_AP_MD0 14 |
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| 54 | #define MT8192_AP_MD1 15 |
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| 55 | #define MT8192_AP_MD2 16 |
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| 56 | |
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| 57 | #endif /* __MEDIATEK_LVTS_DT_H */ |
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| 58 | |
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