| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * linux/include/asm-arm/hardware/amba_kmi.h |
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| 4 | * |
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| 5 | * Internal header file for AMBA KMI ports |
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| 6 | * |
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| 7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. |
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| 8 | * |
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| 9 | * --------------------------------------------------------------------------- |
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| 10 | * From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical |
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| 11 | * Reference Manual - ARM DDI 0143B - see http://www.arm.com/ |
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| 12 | * --------------------------------------------------------------------------- |
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| 13 | */ |
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| 14 | #ifndef ASM_ARM_HARDWARE_AMBA_KMI_H |
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| 15 | #define ASM_ARM_HARDWARE_AMBA_KMI_H |
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| 16 | |
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| 17 | /* |
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| 18 | * KMI control register: |
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| 19 | * KMICR_TYPE 0 = PS2/AT mode, 1 = No line control bit mode |
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| 20 | * KMICR_RXINTREN 1 = enable RX interrupts |
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| 21 | * KMICR_TXINTREN 1 = enable TX interrupts |
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| 22 | * KMICR_EN 1 = enable KMI |
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| 23 | * KMICR_FD 1 = force KMI data low |
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| 24 | * KMICR_FC 1 = force KMI clock low |
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| 25 | */ |
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| 26 | #define KMICR (KMI_BASE + 0x00) |
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| 27 | #define KMICR_TYPE (1 << 5) |
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| 28 | #define KMICR_RXINTREN (1 << 4) |
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| 29 | #define KMICR_TXINTREN (1 << 3) |
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| 30 | #define KMICR_EN (1 << 2) |
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| 31 | #define KMICR_FD (1 << 1) |
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| 32 | #define KMICR_FC (1 << 0) |
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| 33 | |
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| 34 | /* |
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| 35 | * KMI status register: |
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| 36 | * KMISTAT_TXEMPTY 1 = transmitter register empty |
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| 37 | * KMISTAT_TXBUSY 1 = currently sending data |
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| 38 | * KMISTAT_RXFULL 1 = receiver register ready to be read |
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| 39 | * KMISTAT_RXBUSY 1 = currently receiving data |
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| 40 | * KMISTAT_RXPARITY parity of last databyte received |
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| 41 | * KMISTAT_IC current level of KMI clock input |
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| 42 | * KMISTAT_ID current level of KMI data input |
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| 43 | */ |
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| 44 | #define KMISTAT (KMI_BASE + 0x04) |
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| 45 | #define KMISTAT_TXEMPTY (1 << 6) |
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| 46 | #define KMISTAT_TXBUSY (1 << 5) |
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| 47 | #define KMISTAT_RXFULL (1 << 4) |
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| 48 | #define KMISTAT_RXBUSY (1 << 3) |
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| 49 | #define KMISTAT_RXPARITY (1 << 2) |
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| 50 | #define KMISTAT_IC (1 << 1) |
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| 51 | #define KMISTAT_ID (1 << 0) |
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| 52 | |
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| 53 | /* |
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| 54 | * KMI data register |
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| 55 | */ |
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| 56 | #define KMIDATA (KMI_BASE + 0x08) |
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| 57 | |
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| 58 | /* |
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| 59 | * KMI clock divisor: to generate 8MHz internal clock |
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| 60 | * div = (ref / 8MHz) - 1; 0 <= div <= 15 |
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| 61 | */ |
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| 62 | #define KMICLKDIV (KMI_BASE + 0x0c) |
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| 63 | |
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| 64 | /* |
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| 65 | * KMI interrupt register: |
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| 66 | * KMIIR_TXINTR 1 = transmit interrupt asserted |
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| 67 | * KMIIR_RXINTR 1 = receive interrupt asserted |
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| 68 | */ |
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| 69 | #define KMIIR (KMI_BASE + 0x10) |
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| 70 | #define KMIIR_TXINTR (1 << 1) |
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| 71 | #define KMIIR_RXINTR (1 << 0) |
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| 72 | |
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| 73 | /* |
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| 74 | * The size of the KMI primecell |
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| 75 | */ |
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| 76 | #define KMI_SIZE (0x100) |
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| 77 | |
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| 78 | #endif |
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| 79 | |
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