1/* Freescale Integrated Flash Controller
2 *
3 * Copyright 2011 Freescale Semiconductor, Inc
4 *
5 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef __ASM_FSL_IFC_H
23#define __ASM_FSL_IFC_H
24
25#include <linux/compiler.h>
26#include <linux/types.h>
27#include <linux/io.h>
28
29#include <linux/of_platform.h>
30#include <linux/interrupt.h>
31
32/*
33 * The actual number of banks implemented depends on the IFC version
34 * - IFC version 1.0 implements 4 banks.
35 * - IFC version 1.1 onward implements 8 banks.
36 */
37#define FSL_IFC_BANK_COUNT 8
38
39#define FSL_IFC_VERSION_MASK 0x0F0F0000
40#define FSL_IFC_VERSION_1_0_0 0x01000000
41#define FSL_IFC_VERSION_1_1_0 0x01010000
42#define FSL_IFC_VERSION_2_0_0 0x02000000
43
44#define PGOFFSET_64K (64*1024)
45#define PGOFFSET_4K (4*1024)
46
47/*
48 * CSPR - Chip Select Property Register
49 */
50#define CSPR_BA 0xFFFF0000
51#define CSPR_BA_SHIFT 16
52#define CSPR_PORT_SIZE 0x00000180
53#define CSPR_PORT_SIZE_SHIFT 7
54/* Port Size 8 bit */
55#define CSPR_PORT_SIZE_8 0x00000080
56/* Port Size 16 bit */
57#define CSPR_PORT_SIZE_16 0x00000100
58/* Port Size 32 bit */
59#define CSPR_PORT_SIZE_32 0x00000180
60/* Write Protect */
61#define CSPR_WP 0x00000040
62#define CSPR_WP_SHIFT 6
63/* Machine Select */
64#define CSPR_MSEL 0x00000006
65#define CSPR_MSEL_SHIFT 1
66/* NOR */
67#define CSPR_MSEL_NOR 0x00000000
68/* NAND */
69#define CSPR_MSEL_NAND 0x00000002
70/* GPCM */
71#define CSPR_MSEL_GPCM 0x00000004
72/* Bank Valid */
73#define CSPR_V 0x00000001
74#define CSPR_V_SHIFT 0
75
76/*
77 * Address Mask Register
78 */
79#define IFC_AMASK_MASK 0xFFFF0000
80#define IFC_AMASK_SHIFT 16
81#define IFC_AMASK(n) (IFC_AMASK_MASK << \
82 (__ilog2(n) - IFC_AMASK_SHIFT))
83
84/*
85 * Chip Select Option Register IFC_NAND Machine
86 */
87/* Enable ECC Encoder */
88#define CSOR_NAND_ECC_ENC_EN 0x80000000
89#define CSOR_NAND_ECC_MODE_MASK 0x30000000
90/* 4 bit correction per 520 Byte sector */
91#define CSOR_NAND_ECC_MODE_4 0x00000000
92/* 8 bit correction per 528 Byte sector */
93#define CSOR_NAND_ECC_MODE_8 0x10000000
94/* Enable ECC Decoder */
95#define CSOR_NAND_ECC_DEC_EN 0x04000000
96/* Row Address Length */
97#define CSOR_NAND_RAL_MASK 0x01800000
98#define CSOR_NAND_RAL_SHIFT 20
99#define CSOR_NAND_RAL_1 0x00000000
100#define CSOR_NAND_RAL_2 0x00800000
101#define CSOR_NAND_RAL_3 0x01000000
102#define CSOR_NAND_RAL_4 0x01800000
103/* Page Size 512b, 2k, 4k */
104#define CSOR_NAND_PGS_MASK 0x00180000
105#define CSOR_NAND_PGS_SHIFT 16
106#define CSOR_NAND_PGS_512 0x00000000
107#define CSOR_NAND_PGS_2K 0x00080000
108#define CSOR_NAND_PGS_4K 0x00100000
109#define CSOR_NAND_PGS_8K 0x00180000
110/* Spare region Size */
111#define CSOR_NAND_SPRZ_MASK 0x0000E000
112#define CSOR_NAND_SPRZ_SHIFT 13
113#define CSOR_NAND_SPRZ_16 0x00000000
114#define CSOR_NAND_SPRZ_64 0x00002000
115#define CSOR_NAND_SPRZ_128 0x00004000
116#define CSOR_NAND_SPRZ_210 0x00006000
117#define CSOR_NAND_SPRZ_218 0x00008000
118#define CSOR_NAND_SPRZ_224 0x0000A000
119#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
120/* Pages Per Block */
121#define CSOR_NAND_PB_MASK 0x00000700
122#define CSOR_NAND_PB_SHIFT 8
123#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
124/* Time for Read Enable High to Output High Impedance */
125#define CSOR_NAND_TRHZ_MASK 0x0000001C
126#define CSOR_NAND_TRHZ_SHIFT 2
127#define CSOR_NAND_TRHZ_20 0x00000000
128#define CSOR_NAND_TRHZ_40 0x00000004
129#define CSOR_NAND_TRHZ_60 0x00000008
130#define CSOR_NAND_TRHZ_80 0x0000000C
131#define CSOR_NAND_TRHZ_100 0x00000010
132/* Buffer control disable */
133#define CSOR_NAND_BCTLD 0x00000001
134
135/*
136 * Chip Select Option Register - NOR Flash Mode
137 */
138/* Enable Address shift Mode */
139#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
140/* Page Read Enable from NOR device */
141#define CSOR_NOR_PGRD_EN 0x10000000
142/* AVD Toggle Enable during Burst Program */
143#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
144/* Address Data Multiplexing Shift */
145#define CSOR_NOR_ADM_MASK 0x0003E000
146#define CSOR_NOR_ADM_SHIFT_SHIFT 13
147#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
148/* Type of the NOR device hooked */
149#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
150#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
151/* Time for Read Enable High to Output High Impedance */
152#define CSOR_NOR_TRHZ_MASK 0x0000001C
153#define CSOR_NOR_TRHZ_SHIFT 2
154#define CSOR_NOR_TRHZ_20 0x00000000
155#define CSOR_NOR_TRHZ_40 0x00000004
156#define CSOR_NOR_TRHZ_60 0x00000008
157#define CSOR_NOR_TRHZ_80 0x0000000C
158#define CSOR_NOR_TRHZ_100 0x00000010
159/* Buffer control disable */
160#define CSOR_NOR_BCTLD 0x00000001
161
162/*
163 * Chip Select Option Register - GPCM Mode
164 */
165/* GPCM Mode - Normal */
166#define CSOR_GPCM_GPMODE_NORMAL 0x00000000
167/* GPCM Mode - GenericASIC */
168#define CSOR_GPCM_GPMODE_ASIC 0x80000000
169/* Parity Mode odd/even */
170#define CSOR_GPCM_PARITY_EVEN 0x40000000
171/* Parity Checking enable/disable */
172#define CSOR_GPCM_PAR_EN 0x20000000
173/* GPCM Timeout Count */
174#define CSOR_GPCM_GPTO_MASK 0x0F000000
175#define CSOR_GPCM_GPTO_SHIFT 24
176#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
177/* GPCM External Access Termination mode for read access */
178#define CSOR_GPCM_RGETA_EXT 0x00080000
179/* GPCM External Access Termination mode for write access */
180#define CSOR_GPCM_WGETA_EXT 0x00040000
181/* Address Data Multiplexing Shift */
182#define CSOR_GPCM_ADM_MASK 0x0003E000
183#define CSOR_GPCM_ADM_SHIFT_SHIFT 13
184#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
185/* Generic ASIC Parity error indication delay */
186#define CSOR_GPCM_GAPERRD_MASK 0x00000180
187#define CSOR_GPCM_GAPERRD_SHIFT 7
188#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
189/* Time for Read Enable High to Output High Impedance */
190#define CSOR_GPCM_TRHZ_MASK 0x0000001C
191#define CSOR_GPCM_TRHZ_20 0x00000000
192#define CSOR_GPCM_TRHZ_40 0x00000004
193#define CSOR_GPCM_TRHZ_60 0x00000008
194#define CSOR_GPCM_TRHZ_80 0x0000000C
195#define CSOR_GPCM_TRHZ_100 0x00000010
196/* Buffer control disable */
197#define CSOR_GPCM_BCTLD 0x00000001
198
199/*
200 * Ready Busy Status Register (RB_STAT)
201 */
202/* CSn is READY */
203#define IFC_RB_STAT_READY_CS0 0x80000000
204#define IFC_RB_STAT_READY_CS1 0x40000000
205#define IFC_RB_STAT_READY_CS2 0x20000000
206#define IFC_RB_STAT_READY_CS3 0x10000000
207
208/*
209 * General Control Register (GCR)
210 */
211#define IFC_GCR_MASK 0x8000F800
212/* reset all IFC hardware */
213#define IFC_GCR_SOFT_RST_ALL 0x80000000
214/* Turnaroud Time of external buffer */
215#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
216#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
217
218/*
219 * Common Event and Error Status Register (CM_EVTER_STAT)
220 */
221/* Chip select error */
222#define IFC_CM_EVTER_STAT_CSER 0x80000000
223
224/*
225 * Common Event and Error Enable Register (CM_EVTER_EN)
226 */
227/* Chip select error checking enable */
228#define IFC_CM_EVTER_EN_CSEREN 0x80000000
229
230/*
231 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
232 */
233/* Chip select error interrupt enable */
234#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
235
236/*
237 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
238 */
239/* transaction type of error Read/Write */
240#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
241#define IFC_CM_ERATTR0_ERAID 0x0FF00000
242#define IFC_CM_ERATTR0_ERAID_SHIFT 20
243#define IFC_CM_ERATTR0_ESRCID 0x0000FF00
244#define IFC_CM_ERATTR0_ESRCID_SHIFT 8
245
246/*
247 * Clock Control Register (CCR)
248 */
249#define IFC_CCR_MASK 0x0F0F8800
250/* Clock division ratio */
251#define IFC_CCR_CLK_DIV_MASK 0x0F000000
252#define IFC_CCR_CLK_DIV_SHIFT 24
253#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
254/* IFC Clock Delay */
255#define IFC_CCR_CLK_DLY_MASK 0x000F0000
256#define IFC_CCR_CLK_DLY_SHIFT 16
257#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
258/* Invert IFC clock before sending out */
259#define IFC_CCR_INV_CLK_EN 0x00008000
260/* Fedback IFC Clock */
261#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
262
263/*
264 * Clock Status Register (CSR)
265 */
266/* Clk is stable */
267#define IFC_CSR_CLK_STAT_STABLE 0x80000000
268
269/*
270 * IFC_NAND Machine Specific Registers
271 */
272/*
273 * NAND Configuration Register (NCFGR)
274 */
275/* Auto Boot Mode */
276#define IFC_NAND_NCFGR_BOOT 0x80000000
277/* SRAM Initialization */
278#define IFC_NAND_NCFGR_SRAM_INIT_EN 0x20000000
279/* Addressing Mode-ROW0+n/COL0 */
280#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
281/* Addressing Mode-ROW0+n/COL0+n */
282#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
283/* Number of loop iterations of FIR sequences for multi page operations */
284#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
285#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
286#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
287/* Number of wait cycles */
288#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
289#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
290
291/*
292 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
293 */
294/* General purpose FCM flash command bytes CMD0-CMD7 */
295#define IFC_NAND_FCR0_CMD0 0xFF000000
296#define IFC_NAND_FCR0_CMD0_SHIFT 24
297#define IFC_NAND_FCR0_CMD1 0x00FF0000
298#define IFC_NAND_FCR0_CMD1_SHIFT 16
299#define IFC_NAND_FCR0_CMD2 0x0000FF00
300#define IFC_NAND_FCR0_CMD2_SHIFT 8
301#define IFC_NAND_FCR0_CMD3 0x000000FF
302#define IFC_NAND_FCR0_CMD3_SHIFT 0
303#define IFC_NAND_FCR1_CMD4 0xFF000000
304#define IFC_NAND_FCR1_CMD4_SHIFT 24
305#define IFC_NAND_FCR1_CMD5 0x00FF0000
306#define IFC_NAND_FCR1_CMD5_SHIFT 16
307#define IFC_NAND_FCR1_CMD6 0x0000FF00
308#define IFC_NAND_FCR1_CMD6_SHIFT 8
309#define IFC_NAND_FCR1_CMD7 0x000000FF
310#define IFC_NAND_FCR1_CMD7_SHIFT 0
311
312/*
313 * Flash ROW and COL Address Register (ROWn, COLn)
314 */
315/* Main/spare region locator */
316#define IFC_NAND_COL_MS 0x80000000
317/* Column Address */
318#define IFC_NAND_COL_CA_MASK 0x00000FFF
319
320/*
321 * NAND Flash Byte Count Register (NAND_BC)
322 */
323/* Byte Count for read/Write */
324#define IFC_NAND_BC 0x000001FF
325
326/*
327 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
328 */
329/* NAND Machine specific opcodes OP0-OP14*/
330#define IFC_NAND_FIR0_OP0 0xFC000000
331#define IFC_NAND_FIR0_OP0_SHIFT 26
332#define IFC_NAND_FIR0_OP1 0x03F00000
333#define IFC_NAND_FIR0_OP1_SHIFT 20
334#define IFC_NAND_FIR0_OP2 0x000FC000
335#define IFC_NAND_FIR0_OP2_SHIFT 14
336#define IFC_NAND_FIR0_OP3 0x00003F00
337#define IFC_NAND_FIR0_OP3_SHIFT 8
338#define IFC_NAND_FIR0_OP4 0x000000FC
339#define IFC_NAND_FIR0_OP4_SHIFT 2
340#define IFC_NAND_FIR1_OP5 0xFC000000
341#define IFC_NAND_FIR1_OP5_SHIFT 26
342#define IFC_NAND_FIR1_OP6 0x03F00000
343#define IFC_NAND_FIR1_OP6_SHIFT 20
344#define IFC_NAND_FIR1_OP7 0x000FC000
345#define IFC_NAND_FIR1_OP7_SHIFT 14
346#define IFC_NAND_FIR1_OP8 0x00003F00
347#define IFC_NAND_FIR1_OP8_SHIFT 8
348#define IFC_NAND_FIR1_OP9 0x000000FC
349#define IFC_NAND_FIR1_OP9_SHIFT 2
350#define IFC_NAND_FIR2_OP10 0xFC000000
351#define IFC_NAND_FIR2_OP10_SHIFT 26
352#define IFC_NAND_FIR2_OP11 0x03F00000
353#define IFC_NAND_FIR2_OP11_SHIFT 20
354#define IFC_NAND_FIR2_OP12 0x000FC000
355#define IFC_NAND_FIR2_OP12_SHIFT 14
356#define IFC_NAND_FIR2_OP13 0x00003F00
357#define IFC_NAND_FIR2_OP13_SHIFT 8
358#define IFC_NAND_FIR2_OP14 0x000000FC
359#define IFC_NAND_FIR2_OP14_SHIFT 2
360
361/*
362 * Instruction opcodes to be programmed
363 * in FIR registers- 6bits
364 */
365enum ifc_nand_fir_opcodes {
366 IFC_FIR_OP_NOP,
367 IFC_FIR_OP_CA0,
368 IFC_FIR_OP_CA1,
369 IFC_FIR_OP_CA2,
370 IFC_FIR_OP_CA3,
371 IFC_FIR_OP_RA0,
372 IFC_FIR_OP_RA1,
373 IFC_FIR_OP_RA2,
374 IFC_FIR_OP_RA3,
375 IFC_FIR_OP_CMD0,
376 IFC_FIR_OP_CMD1,
377 IFC_FIR_OP_CMD2,
378 IFC_FIR_OP_CMD3,
379 IFC_FIR_OP_CMD4,
380 IFC_FIR_OP_CMD5,
381 IFC_FIR_OP_CMD6,
382 IFC_FIR_OP_CMD7,
383 IFC_FIR_OP_CW0,
384 IFC_FIR_OP_CW1,
385 IFC_FIR_OP_CW2,
386 IFC_FIR_OP_CW3,
387 IFC_FIR_OP_CW4,
388 IFC_FIR_OP_CW5,
389 IFC_FIR_OP_CW6,
390 IFC_FIR_OP_CW7,
391 IFC_FIR_OP_WBCD,
392 IFC_FIR_OP_RBCD,
393 IFC_FIR_OP_BTRD,
394 IFC_FIR_OP_RDSTAT,
395 IFC_FIR_OP_NWAIT,
396 IFC_FIR_OP_WFR,
397 IFC_FIR_OP_SBRD,
398 IFC_FIR_OP_UA,
399 IFC_FIR_OP_RB,
400};
401
402/*
403 * NAND Chip Select Register (NAND_CSEL)
404 */
405#define IFC_NAND_CSEL 0x0C000000
406#define IFC_NAND_CSEL_SHIFT 26
407#define IFC_NAND_CSEL_CS0 0x00000000
408#define IFC_NAND_CSEL_CS1 0x04000000
409#define IFC_NAND_CSEL_CS2 0x08000000
410#define IFC_NAND_CSEL_CS3 0x0C000000
411
412/*
413 * NAND Operation Sequence Start (NANDSEQ_STRT)
414 */
415/* NAND Flash Operation Start */
416#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
417/* Automatic Erase */
418#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
419/* Automatic Program */
420#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
421/* Automatic Copyback */
422#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
423/* Automatic Read Operation */
424#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
425/* Automatic Status Read */
426#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
427
428/*
429 * NAND Event and Error Status Register (NAND_EVTER_STAT)
430 */
431/* Operation Complete */
432#define IFC_NAND_EVTER_STAT_OPC 0x80000000
433/* Flash Timeout Error */
434#define IFC_NAND_EVTER_STAT_FTOER 0x08000000
435/* Write Protect Error */
436#define IFC_NAND_EVTER_STAT_WPER 0x04000000
437/* ECC Error */
438#define IFC_NAND_EVTER_STAT_ECCER 0x02000000
439/* RCW Load Done */
440#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
441/* Boot Loadr Done */
442#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
443/* Bad Block Indicator search select */
444#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
445
446/*
447 * NAND Flash Page Read Completion Event Status Register
448 * (PGRDCMPL_EVT_STAT)
449 */
450#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
451/* Small Page 0-15 Done */
452#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
453/* Large Page(2K) 0-3 Done */
454#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
455/* Large Page(4K) 0-1 Done */
456#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
457
458/*
459 * NAND Event and Error Enable Register (NAND_EVTER_EN)
460 */
461/* Operation complete event enable */
462#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
463/* Page read complete event enable */
464#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
465/* Flash Timeout error enable */
466#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
467/* Write Protect error enable */
468#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
469/* ECC error logging enable */
470#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
471
472/*
473 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
474 */
475/* Enable interrupt for operation complete */
476#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
477/* Enable interrupt for Page read complete */
478#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
479/* Enable interrupt for Flash timeout error */
480#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
481/* Enable interrupt for Write protect error */
482#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
483/* Enable interrupt for ECC error*/
484#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
485
486/*
487 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
488 */
489#define IFC_NAND_ERATTR0_MASK 0x0C080000
490/* Error on CS0-3 for NAND */
491#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
492#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
493#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
494#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
495/* Transaction type of error Read/Write */
496#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
497
498/*
499 * NAND Flash Status Register (NAND_FSR)
500 */
501/* First byte of data read from read status op */
502#define IFC_NAND_NFSR_RS0 0xFF000000
503/* Second byte of data read from read status op */
504#define IFC_NAND_NFSR_RS1 0x00FF0000
505
506/*
507 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
508 */
509/* Number of ECC errors on sector n (n = 0-15) */
510#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
511#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
512#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
513#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
514#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
515#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
516#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
517#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
518#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
519#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
520#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
521#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
522#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
523#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
524#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
525#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
526#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
527#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
528#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
529#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
530#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
531#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
532#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
533#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
534#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
535#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
536#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
537#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
538#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
539#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
540#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
541#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
542
543/*
544 * NAND Control Register (NANDCR)
545 */
546#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
547#define IFC_NAND_NCR_FTOCNT_SHIFT 25
548#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
549
550/*
551 * NAND_AUTOBOOT_TRGR
552 */
553/* Trigger RCW load */
554#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
555/* Trigget Auto Boot */
556#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
557
558/*
559 * NAND_MDR
560 */
561/* 1st read data byte when opcode SBRD */
562#define IFC_NAND_MDR_RDATA0 0xFF000000
563/* 2nd read data byte when opcode SBRD */
564#define IFC_NAND_MDR_RDATA1 0x00FF0000
565
566/*
567 * NOR Machine Specific Registers
568 */
569/*
570 * NOR Event and Error Status Register (NOR_EVTER_STAT)
571 */
572/* NOR Command Sequence Operation Complete */
573#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
574/* Write Protect Error */
575#define IFC_NOR_EVTER_STAT_WPER 0x04000000
576/* Command Sequence Timeout Error */
577#define IFC_NOR_EVTER_STAT_STOER 0x01000000
578
579/*
580 * NOR Event and Error Enable Register (NOR_EVTER_EN)
581 */
582/* NOR Command Seq complete event enable */
583#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
584/* Write Protect Error Checking Enable */
585#define IFC_NOR_EVTER_EN_WPEREN 0x04000000
586/* Timeout Error Enable */
587#define IFC_NOR_EVTER_EN_STOEREN 0x01000000
588
589/*
590 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
591 */
592/* Enable interrupt for OPC complete */
593#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
594/* Enable interrupt for write protect error */
595#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
596/* Enable interrupt for timeout error */
597#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
598
599/*
600 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
601 */
602/* Source ID for error transaction */
603#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
604/* AXI ID for error transation */
605#define IFC_NOR_ERATTR0_ERAID 0x000FF000
606/* Chip select corresponds to NOR error */
607#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
608#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
609#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
610#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
611/* Type of transaction read/write */
612#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
613
614/*
615 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
616 */
617#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
618#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
619
620/*
621 * NOR Control Register (NORCR)
622 */
623#define IFC_NORCR_MASK 0x0F0F0000
624/* No. of Address/Data Phase */
625#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
626#define IFC_NORCR_NUM_PHASE_SHIFT 24
627#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
628/* Sequence Timeout Count */
629#define IFC_NORCR_STOCNT_MASK 0x000F0000
630#define IFC_NORCR_STOCNT_SHIFT 16
631#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
632
633/*
634 * GPCM Machine specific registers
635 */
636/*
637 * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
638 */
639/* Timeout error */
640#define IFC_GPCM_EVTER_STAT_TOER 0x04000000
641/* Parity error */
642#define IFC_GPCM_EVTER_STAT_PER 0x01000000
643
644/*
645 * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
646 */
647/* Timeout error enable */
648#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
649/* Parity error enable */
650#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
651
652/*
653 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
654 */
655/* Enable Interrupt for timeout error */
656#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
657/* Enable Interrupt for Parity error */
658#define IFC_GPCM_EEIER_PERIR_EN 0x01000000
659
660/*
661 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
662 */
663/* Source ID for error transaction */
664#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
665/* AXI ID for error transaction */
666#define IFC_GPCM_ERATTR0_ERAID 0x000FF000
667/* Chip select corresponds to GPCM error */
668#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
669#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
670#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
671#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
672/* Type of transaction read/Write */
673#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
674
675/*
676 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
677 */
678/* On which beat of address/data parity error is observed */
679#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
680/* Parity Error on byte */
681#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
682/* Parity Error reported in addr or data phase */
683#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
684
685/*
686 * GPCM Status Register (GPCM_STAT)
687 */
688#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
689
690/*
691 * IFC Controller NAND Machine registers
692 */
693struct fsl_ifc_nand {
694 __be32 ncfgr;
695 u32 res1[0x4];
696 __be32 nand_fcr0;
697 __be32 nand_fcr1;
698 u32 res2[0x8];
699 __be32 row0;
700 u32 res3;
701 __be32 col0;
702 u32 res4;
703 __be32 row1;
704 u32 res5;
705 __be32 col1;
706 u32 res6;
707 __be32 row2;
708 u32 res7;
709 __be32 col2;
710 u32 res8;
711 __be32 row3;
712 u32 res9;
713 __be32 col3;
714 u32 res10[0x24];
715 __be32 nand_fbcr;
716 u32 res11;
717 __be32 nand_fir0;
718 __be32 nand_fir1;
719 __be32 nand_fir2;
720 u32 res12[0x10];
721 __be32 nand_csel;
722 u32 res13;
723 __be32 nandseq_strt;
724 u32 res14;
725 __be32 nand_evter_stat;
726 u32 res15;
727 __be32 pgrdcmpl_evt_stat;
728 u32 res16[0x2];
729 __be32 nand_evter_en;
730 u32 res17[0x2];
731 __be32 nand_evter_intr_en;
732 __be32 nand_vol_addr_stat;
733 u32 res18;
734 __be32 nand_erattr0;
735 __be32 nand_erattr1;
736 u32 res19[0x10];
737 __be32 nand_fsr;
738 u32 res20;
739 __be32 nand_eccstat[8];
740 u32 res21[0x1c];
741 __be32 nanndcr;
742 u32 res22[0x2];
743 __be32 nand_autoboot_trgr;
744 u32 res23;
745 __be32 nand_mdr;
746 u32 res24[0x1C];
747 __be32 nand_dll_lowcfg0;
748 __be32 nand_dll_lowcfg1;
749 u32 res25;
750 __be32 nand_dll_lowstat;
751 u32 res26[0x3c];
752};
753
754/*
755 * IFC controller NOR Machine registers
756 */
757struct fsl_ifc_nor {
758 __be32 nor_evter_stat;
759 u32 res1[0x2];
760 __be32 nor_evter_en;
761 u32 res2[0x2];
762 __be32 nor_evter_intr_en;
763 u32 res3[0x2];
764 __be32 nor_erattr0;
765 __be32 nor_erattr1;
766 __be32 nor_erattr2;
767 u32 res4[0x4];
768 __be32 norcr;
769 u32 res5[0xEF];
770};
771
772/*
773 * IFC controller GPCM Machine registers
774 */
775struct fsl_ifc_gpcm {
776 __be32 gpcm_evter_stat;
777 u32 res1[0x2];
778 __be32 gpcm_evter_en;
779 u32 res2[0x2];
780 __be32 gpcm_evter_intr_en;
781 u32 res3[0x2];
782 __be32 gpcm_erattr0;
783 __be32 gpcm_erattr1;
784 __be32 gpcm_erattr2;
785 __be32 gpcm_stat;
786};
787
788/*
789 * IFC Controller Registers
790 */
791struct fsl_ifc_global {
792 __be32 ifc_rev;
793 u32 res1[0x2];
794 struct {
795 __be32 cspr_ext;
796 __be32 cspr;
797 u32 res2;
798 } cspr_cs[FSL_IFC_BANK_COUNT];
799 u32 res3[0xd];
800 struct {
801 __be32 amask;
802 u32 res4[0x2];
803 } amask_cs[FSL_IFC_BANK_COUNT];
804 u32 res5[0xc];
805 struct {
806 __be32 csor;
807 __be32 csor_ext;
808 u32 res6;
809 } csor_cs[FSL_IFC_BANK_COUNT];
810 u32 res7[0xc];
811 struct {
812 __be32 ftim[4];
813 u32 res8[0x8];
814 } ftim_cs[FSL_IFC_BANK_COUNT];
815 u32 res9[0x30];
816 __be32 rb_stat;
817 __be32 rb_map;
818 __be32 wb_map;
819 __be32 ifc_gcr;
820 u32 res10[0x2];
821 __be32 cm_evter_stat;
822 u32 res11[0x2];
823 __be32 cm_evter_en;
824 u32 res12[0x2];
825 __be32 cm_evter_intr_en;
826 u32 res13[0x2];
827 __be32 cm_erattr0;
828 __be32 cm_erattr1;
829 u32 res14[0x2];
830 __be32 ifc_ccr;
831 __be32 ifc_csr;
832 __be32 ddr_ccr_low;
833};
834
835
836struct fsl_ifc_runtime {
837 struct fsl_ifc_nand ifc_nand;
838 struct fsl_ifc_nor ifc_nor;
839 struct fsl_ifc_gpcm ifc_gpcm;
840};
841
842extern unsigned int convert_ifc_address(phys_addr_t addr_base);
843extern int fsl_ifc_find(phys_addr_t addr_base);
844
845/* overview of the fsl ifc controller */
846
847struct fsl_ifc_ctrl {
848 /* device info */
849 struct device *dev;
850 struct fsl_ifc_global __iomem *gregs;
851 struct fsl_ifc_runtime __iomem *rregs;
852 int irq;
853 int nand_irq;
854 spinlock_t lock;
855 void *nand;
856 int version;
857 int banks;
858
859 u32 nand_stat;
860 wait_queue_head_t nand_wait;
861 bool little_endian;
862};
863
864extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
865
866static inline u32 ifc_in32(void __iomem *addr)
867{
868 u32 val;
869
870 if (fsl_ifc_ctrl_dev->little_endian)
871 val = ioread32(addr);
872 else
873 val = ioread32be(addr);
874
875 return val;
876}
877
878static inline u16 ifc_in16(void __iomem *addr)
879{
880 u16 val;
881
882 if (fsl_ifc_ctrl_dev->little_endian)
883 val = ioread16(addr);
884 else
885 val = ioread16be(addr);
886
887 return val;
888}
889
890static inline u8 ifc_in8(void __iomem *addr)
891{
892 return ioread8(addr);
893}
894
895static inline void ifc_out32(u32 val, void __iomem *addr)
896{
897 if (fsl_ifc_ctrl_dev->little_endian)
898 iowrite32(val, addr);
899 else
900 iowrite32be(val, addr);
901}
902
903static inline void ifc_out16(u16 val, void __iomem *addr)
904{
905 if (fsl_ifc_ctrl_dev->little_endian)
906 iowrite16(val, addr);
907 else
908 iowrite16be(val, addr);
909}
910
911static inline void ifc_out8(u8 val, void __iomem *addr)
912{
913 iowrite8(val, addr);
914}
915
916#endif /* __ASM_FSL_IFC_H */
917