1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright (c) 2021 MediaTek Inc. |
4 | */ |
5 | |
6 | #ifndef __MFD_MT6359_CORE_H__ |
7 | #define __MFD_MT6359_CORE_H__ |
8 | |
9 | enum mt6359_irq_top_status_shift { |
10 | MT6359_BUCK_TOP = 0, |
11 | MT6359_LDO_TOP, |
12 | MT6359_PSC_TOP, |
13 | MT6359_SCK_TOP, |
14 | MT6359_BM_TOP, |
15 | MT6359_HK_TOP, |
16 | MT6359_AUD_TOP = 7, |
17 | MT6359_MISC_TOP, |
18 | }; |
19 | |
20 | enum mt6359_irq_numbers { |
21 | MT6359_IRQ_VCORE_OC = 1, |
22 | MT6359_IRQ_VGPU11_OC, |
23 | MT6359_IRQ_VGPU12_OC, |
24 | MT6359_IRQ_VMODEM_OC, |
25 | MT6359_IRQ_VPROC1_OC, |
26 | MT6359_IRQ_VPROC2_OC, |
27 | MT6359_IRQ_VS1_OC, |
28 | MT6359_IRQ_VS2_OC, |
29 | MT6359_IRQ_VPA_OC = 9, |
30 | MT6359_IRQ_VFE28_OC = 16, |
31 | MT6359_IRQ_VXO22_OC, |
32 | MT6359_IRQ_VRF18_OC, |
33 | MT6359_IRQ_VRF12_OC, |
34 | MT6359_IRQ_VEFUSE_OC, |
35 | MT6359_IRQ_VCN33_1_OC, |
36 | MT6359_IRQ_VCN33_2_OC, |
37 | MT6359_IRQ_VCN13_OC, |
38 | MT6359_IRQ_VCN18_OC, |
39 | MT6359_IRQ_VA09_OC, |
40 | MT6359_IRQ_VCAMIO_OC, |
41 | MT6359_IRQ_VA12_OC, |
42 | MT6359_IRQ_VAUX18_OC, |
43 | MT6359_IRQ_VAUD18_OC, |
44 | MT6359_IRQ_VIO18_OC, |
45 | MT6359_IRQ_VSRAM_PROC1_OC, |
46 | MT6359_IRQ_VSRAM_PROC2_OC, |
47 | MT6359_IRQ_VSRAM_OTHERS_OC, |
48 | MT6359_IRQ_VSRAM_MD_OC, |
49 | MT6359_IRQ_VEMC_OC, |
50 | MT6359_IRQ_VSIM1_OC, |
51 | MT6359_IRQ_VSIM2_OC, |
52 | MT6359_IRQ_VUSB_OC, |
53 | MT6359_IRQ_VRFCK_OC, |
54 | MT6359_IRQ_VBBCK_OC, |
55 | MT6359_IRQ_VBIF28_OC, |
56 | MT6359_IRQ_VIBR_OC, |
57 | MT6359_IRQ_VIO28_OC, |
58 | MT6359_IRQ_VM18_OC, |
59 | MT6359_IRQ_VUFS_OC = 45, |
60 | MT6359_IRQ_PWRKEY = 48, |
61 | MT6359_IRQ_HOMEKEY, |
62 | MT6359_IRQ_PWRKEY_R, |
63 | MT6359_IRQ_HOMEKEY_R, |
64 | MT6359_IRQ_NI_LBAT_INT, |
65 | MT6359_IRQ_CHRDET_EDGE = 53, |
66 | MT6359_IRQ_RTC = 64, |
67 | MT6359_IRQ_FG_BAT_H = 80, |
68 | MT6359_IRQ_FG_BAT_L, |
69 | MT6359_IRQ_FG_CUR_H, |
70 | MT6359_IRQ_FG_CUR_L, |
71 | MT6359_IRQ_FG_ZCV = 84, |
72 | MT6359_IRQ_FG_N_CHARGE_L = 87, |
73 | MT6359_IRQ_FG_IAVG_H, |
74 | MT6359_IRQ_FG_IAVG_L = 89, |
75 | MT6359_IRQ_FG_DISCHARGE = 91, |
76 | MT6359_IRQ_FG_CHARGE, |
77 | MT6359_IRQ_BATON_LV = 96, |
78 | MT6359_IRQ_BATON_BAT_IN = 98, |
79 | MT6359_IRQ_BATON_BAT_OU, |
80 | MT6359_IRQ_BIF = 100, |
81 | MT6359_IRQ_BAT_H = 112, |
82 | MT6359_IRQ_BAT_L, |
83 | MT6359_IRQ_BAT2_H, |
84 | MT6359_IRQ_BAT2_L, |
85 | MT6359_IRQ_BAT_TEMP_H, |
86 | MT6359_IRQ_BAT_TEMP_L, |
87 | MT6359_IRQ_THR_H, |
88 | MT6359_IRQ_THR_L, |
89 | MT6359_IRQ_AUXADC_IMP, |
90 | MT6359_IRQ_NAG_C_DLTV = 121, |
91 | MT6359_IRQ_AUDIO = 128, |
92 | MT6359_IRQ_ACCDET = 133, |
93 | MT6359_IRQ_ACCDET_EINT0, |
94 | MT6359_IRQ_ACCDET_EINT1, |
95 | MT6359_IRQ_SPI_CMD_ALERT = 144, |
96 | MT6359_IRQ_NR, |
97 | }; |
98 | |
99 | #define MT6359_IRQ_BUCK_BASE MT6359_IRQ_VCORE_OC |
100 | #define MT6359_IRQ_LDO_BASE MT6359_IRQ_VFE28_OC |
101 | #define MT6359_IRQ_PSC_BASE MT6359_IRQ_PWRKEY |
102 | #define MT6359_IRQ_SCK_BASE MT6359_IRQ_RTC |
103 | #define MT6359_IRQ_BM_BASE MT6359_IRQ_FG_BAT_H |
104 | #define MT6359_IRQ_HK_BASE MT6359_IRQ_BAT_H |
105 | #define MT6359_IRQ_AUD_BASE MT6359_IRQ_AUDIO |
106 | #define MT6359_IRQ_MISC_BASE MT6359_IRQ_SPI_CMD_ALERT |
107 | |
108 | #define MT6359_IRQ_BUCK_BITS (MT6359_IRQ_VPA_OC - MT6359_IRQ_BUCK_BASE + 1) |
109 | #define MT6359_IRQ_LDO_BITS (MT6359_IRQ_VUFS_OC - MT6359_IRQ_LDO_BASE + 1) |
110 | #define MT6359_IRQ_PSC_BITS \ |
111 | (MT6359_IRQ_CHRDET_EDGE - MT6359_IRQ_PSC_BASE + 1) |
112 | #define MT6359_IRQ_SCK_BITS (MT6359_IRQ_RTC - MT6359_IRQ_SCK_BASE + 1) |
113 | #define MT6359_IRQ_BM_BITS (MT6359_IRQ_BIF - MT6359_IRQ_BM_BASE + 1) |
114 | #define MT6359_IRQ_HK_BITS (MT6359_IRQ_NAG_C_DLTV - MT6359_IRQ_HK_BASE + 1) |
115 | #define MT6359_IRQ_AUD_BITS \ |
116 | (MT6359_IRQ_ACCDET_EINT1 - MT6359_IRQ_AUD_BASE + 1) |
117 | #define MT6359_IRQ_MISC_BITS \ |
118 | (MT6359_IRQ_SPI_CMD_ALERT - MT6359_IRQ_MISC_BASE + 1) |
119 | |
120 | #define MT6359_TOP_GEN(sp) \ |
121 | { \ |
122 | .hwirq_base = MT6359_IRQ_##sp##_BASE, \ |
123 | .num_int_regs = \ |
124 | ((MT6359_IRQ_##sp##_BITS - 1) / \ |
125 | MTK_PMIC_REG_WIDTH) + 1, \ |
126 | .en_reg = MT6359_##sp##_TOP_INT_CON0, \ |
127 | .en_reg_shift = 0x6, \ |
128 | .sta_reg = MT6359_##sp##_TOP_INT_STATUS0, \ |
129 | .sta_reg_shift = 0x2, \ |
130 | .top_offset = MT6359_##sp##_TOP, \ |
131 | } |
132 | |
133 | #endif /* __MFD_MT6359_CORE_H__ */ |
134 | |