| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Register definitions for Rockchip's RK808/RK818 PMIC |
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| 4 | * |
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| 5 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd |
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| 6 | * |
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| 7 | * Author: Chris Zhong <zyw@rock-chips.com> |
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| 8 | * Author: Zhang Qing <zhangqing@rock-chips.com> |
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| 9 | * |
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| 10 | * Copyright (C) 2016 PHYTEC Messtechnik GmbH |
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| 11 | * |
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| 12 | * Author: Wadim Egorov <w.egorov@phytec.de> |
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| 13 | */ |
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| 14 | |
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| 15 | #ifndef __LINUX_REGULATOR_RK808_H |
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| 16 | #define __LINUX_REGULATOR_RK808_H |
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| 17 | |
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| 18 | #include <linux/regulator/machine.h> |
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| 19 | #include <linux/regmap.h> |
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| 20 | |
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| 21 | /* |
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| 22 | * rk808 Global Register Map. |
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| 23 | */ |
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| 24 | |
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| 25 | #define RK808_DCDC1 0 /* (0+RK808_START) */ |
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| 26 | #define RK808_LDO1 4 /* (4+RK808_START) */ |
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| 27 | #define RK808_NUM_REGULATORS 14 |
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| 28 | |
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| 29 | enum rk808_reg { |
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| 30 | RK808_ID_DCDC1, |
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| 31 | RK808_ID_DCDC2, |
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| 32 | RK808_ID_DCDC3, |
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| 33 | RK808_ID_DCDC4, |
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| 34 | RK808_ID_LDO1, |
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| 35 | RK808_ID_LDO2, |
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| 36 | RK808_ID_LDO3, |
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| 37 | RK808_ID_LDO4, |
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| 38 | RK808_ID_LDO5, |
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| 39 | RK808_ID_LDO6, |
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| 40 | RK808_ID_LDO7, |
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| 41 | RK808_ID_LDO8, |
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| 42 | RK808_ID_SWITCH1, |
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| 43 | RK808_ID_SWITCH2, |
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| 44 | }; |
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| 45 | |
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| 46 | #define RK808_SECONDS_REG 0x00 |
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| 47 | #define RK808_MINUTES_REG 0x01 |
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| 48 | #define RK808_HOURS_REG 0x02 |
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| 49 | #define RK808_DAYS_REG 0x03 |
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| 50 | #define RK808_MONTHS_REG 0x04 |
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| 51 | #define RK808_YEARS_REG 0x05 |
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| 52 | #define RK808_WEEKS_REG 0x06 |
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| 53 | #define RK808_ALARM_SECONDS_REG 0x08 |
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| 54 | #define RK808_ALARM_MINUTES_REG 0x09 |
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| 55 | #define RK808_ALARM_HOURS_REG 0x0a |
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| 56 | #define RK808_ALARM_DAYS_REG 0x0b |
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| 57 | #define RK808_ALARM_MONTHS_REG 0x0c |
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| 58 | #define RK808_ALARM_YEARS_REG 0x0d |
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| 59 | #define RK808_RTC_CTRL_REG 0x10 |
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| 60 | #define RK808_RTC_STATUS_REG 0x11 |
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| 61 | #define RK808_RTC_INT_REG 0x12 |
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| 62 | #define RK808_RTC_COMP_LSB_REG 0x13 |
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| 63 | #define RK808_RTC_COMP_MSB_REG 0x14 |
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| 64 | #define RK808_ID_MSB 0x17 |
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| 65 | #define RK808_ID_LSB 0x18 |
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| 66 | #define RK808_CLK32OUT_REG 0x20 |
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| 67 | #define RK808_VB_MON_REG 0x21 |
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| 68 | #define RK808_THERMAL_REG 0x22 |
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| 69 | #define RK808_DCDC_EN_REG 0x23 |
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| 70 | #define RK808_LDO_EN_REG 0x24 |
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| 71 | #define RK808_SLEEP_SET_OFF_REG1 0x25 |
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| 72 | #define RK808_SLEEP_SET_OFF_REG2 0x26 |
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| 73 | #define RK808_DCDC_UV_STS_REG 0x27 |
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| 74 | #define RK808_DCDC_UV_ACT_REG 0x28 |
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| 75 | #define RK808_LDO_UV_STS_REG 0x29 |
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| 76 | #define RK808_LDO_UV_ACT_REG 0x2a |
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| 77 | #define RK808_DCDC_PG_REG 0x2b |
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| 78 | #define RK808_LDO_PG_REG 0x2c |
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| 79 | #define RK808_VOUT_MON_TDB_REG 0x2d |
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| 80 | #define RK808_BUCK1_CONFIG_REG 0x2e |
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| 81 | #define RK808_BUCK1_ON_VSEL_REG 0x2f |
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| 82 | #define RK808_BUCK1_SLP_VSEL_REG 0x30 |
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| 83 | #define RK808_BUCK1_DVS_VSEL_REG 0x31 |
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| 84 | #define RK808_BUCK2_CONFIG_REG 0x32 |
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| 85 | #define RK808_BUCK2_ON_VSEL_REG 0x33 |
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| 86 | #define RK808_BUCK2_SLP_VSEL_REG 0x34 |
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| 87 | #define RK808_BUCK2_DVS_VSEL_REG 0x35 |
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| 88 | #define RK808_BUCK3_CONFIG_REG 0x36 |
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| 89 | #define RK808_BUCK4_CONFIG_REG 0x37 |
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| 90 | #define RK808_BUCK4_ON_VSEL_REG 0x38 |
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| 91 | #define RK808_BUCK4_SLP_VSEL_REG 0x39 |
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| 92 | #define RK808_BOOST_CONFIG_REG 0x3a |
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| 93 | #define RK808_LDO1_ON_VSEL_REG 0x3b |
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| 94 | #define RK808_LDO1_SLP_VSEL_REG 0x3c |
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| 95 | #define RK808_LDO2_ON_VSEL_REG 0x3d |
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| 96 | #define RK808_LDO2_SLP_VSEL_REG 0x3e |
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| 97 | #define RK808_LDO3_ON_VSEL_REG 0x3f |
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| 98 | #define RK808_LDO3_SLP_VSEL_REG 0x40 |
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| 99 | #define RK808_LDO4_ON_VSEL_REG 0x41 |
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| 100 | #define RK808_LDO4_SLP_VSEL_REG 0x42 |
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| 101 | #define RK808_LDO5_ON_VSEL_REG 0x43 |
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| 102 | #define RK808_LDO5_SLP_VSEL_REG 0x44 |
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| 103 | #define RK808_LDO6_ON_VSEL_REG 0x45 |
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| 104 | #define RK808_LDO6_SLP_VSEL_REG 0x46 |
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| 105 | #define RK808_LDO7_ON_VSEL_REG 0x47 |
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| 106 | #define RK808_LDO7_SLP_VSEL_REG 0x48 |
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| 107 | #define RK808_LDO8_ON_VSEL_REG 0x49 |
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| 108 | #define RK808_LDO8_SLP_VSEL_REG 0x4a |
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| 109 | #define RK808_DEVCTRL_REG 0x4b |
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| 110 | #define RK808_INT_STS_REG1 0x4c |
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| 111 | #define RK808_INT_STS_MSK_REG1 0x4d |
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| 112 | #define RK808_INT_STS_REG2 0x4e |
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| 113 | #define RK808_INT_STS_MSK_REG2 0x4f |
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| 114 | #define RK808_IO_POL_REG 0x50 |
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| 115 | |
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| 116 | /* RK818 */ |
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| 117 | #define RK818_DCDC1 0 |
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| 118 | #define RK818_LDO1 4 |
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| 119 | #define RK818_NUM_REGULATORS 17 |
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| 120 | |
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| 121 | enum rk818_reg { |
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| 122 | RK818_ID_DCDC1, |
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| 123 | RK818_ID_DCDC2, |
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| 124 | RK818_ID_DCDC3, |
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| 125 | RK818_ID_DCDC4, |
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| 126 | RK818_ID_BOOST, |
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| 127 | RK818_ID_LDO1, |
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| 128 | RK818_ID_LDO2, |
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| 129 | RK818_ID_LDO3, |
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| 130 | RK818_ID_LDO4, |
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| 131 | RK818_ID_LDO5, |
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| 132 | RK818_ID_LDO6, |
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| 133 | RK818_ID_LDO7, |
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| 134 | RK818_ID_LDO8, |
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| 135 | RK818_ID_LDO9, |
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| 136 | RK818_ID_SWITCH, |
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| 137 | RK818_ID_HDMI_SWITCH, |
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| 138 | RK818_ID_OTG_SWITCH, |
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| 139 | }; |
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| 140 | |
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| 141 | #define RK818_DCDC_EN_REG 0x23 |
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| 142 | #define RK818_LDO_EN_REG 0x24 |
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| 143 | #define RK818_SLEEP_SET_OFF_REG1 0x25 |
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| 144 | #define RK818_SLEEP_SET_OFF_REG2 0x26 |
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| 145 | #define RK818_DCDC_UV_STS_REG 0x27 |
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| 146 | #define RK818_DCDC_UV_ACT_REG 0x28 |
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| 147 | #define RK818_LDO_UV_STS_REG 0x29 |
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| 148 | #define RK818_LDO_UV_ACT_REG 0x2a |
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| 149 | #define RK818_DCDC_PG_REG 0x2b |
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| 150 | #define RK818_LDO_PG_REG 0x2c |
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| 151 | #define RK818_VOUT_MON_TDB_REG 0x2d |
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| 152 | #define RK818_BUCK1_CONFIG_REG 0x2e |
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| 153 | #define RK818_BUCK1_ON_VSEL_REG 0x2f |
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| 154 | #define RK818_BUCK1_SLP_VSEL_REG 0x30 |
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| 155 | #define RK818_BUCK2_CONFIG_REG 0x32 |
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| 156 | #define RK818_BUCK2_ON_VSEL_REG 0x33 |
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| 157 | #define RK818_BUCK2_SLP_VSEL_REG 0x34 |
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| 158 | #define RK818_BUCK3_CONFIG_REG 0x36 |
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| 159 | #define RK818_BUCK4_CONFIG_REG 0x37 |
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| 160 | #define RK818_BUCK4_ON_VSEL_REG 0x38 |
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| 161 | #define RK818_BUCK4_SLP_VSEL_REG 0x39 |
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| 162 | #define RK818_BOOST_CONFIG_REG 0x3a |
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| 163 | #define RK818_LDO1_ON_VSEL_REG 0x3b |
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| 164 | #define RK818_LDO1_SLP_VSEL_REG 0x3c |
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| 165 | #define RK818_LDO2_ON_VSEL_REG 0x3d |
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| 166 | #define RK818_LDO2_SLP_VSEL_REG 0x3e |
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| 167 | #define RK818_LDO3_ON_VSEL_REG 0x3f |
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| 168 | #define RK818_LDO3_SLP_VSEL_REG 0x40 |
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| 169 | #define RK818_LDO4_ON_VSEL_REG 0x41 |
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| 170 | #define RK818_LDO4_SLP_VSEL_REG 0x42 |
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| 171 | #define RK818_LDO5_ON_VSEL_REG 0x43 |
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| 172 | #define RK818_LDO5_SLP_VSEL_REG 0x44 |
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| 173 | #define RK818_LDO6_ON_VSEL_REG 0x45 |
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| 174 | #define RK818_LDO6_SLP_VSEL_REG 0x46 |
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| 175 | #define RK818_LDO7_ON_VSEL_REG 0x47 |
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| 176 | #define RK818_LDO7_SLP_VSEL_REG 0x48 |
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| 177 | #define RK818_LDO8_ON_VSEL_REG 0x49 |
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| 178 | #define RK818_LDO8_SLP_VSEL_REG 0x4a |
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| 179 | #define RK818_BOOST_LDO9_ON_VSEL_REG 0x54 |
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| 180 | #define RK818_BOOST_LDO9_SLP_VSEL_REG 0x55 |
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| 181 | #define RK818_DEVCTRL_REG 0x4b |
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| 182 | #define RK818_INT_STS_REG1 0X4c |
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| 183 | #define RK818_INT_STS_MSK_REG1 0x4d |
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| 184 | #define RK818_INT_STS_REG2 0x4e |
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| 185 | #define RK818_INT_STS_MSK_REG2 0x4f |
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| 186 | #define RK818_IO_POL_REG 0x50 |
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| 187 | #define RK818_H5V_EN_REG 0x52 |
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| 188 | #define RK818_SLEEP_SET_OFF_REG3 0x53 |
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| 189 | #define RK818_BOOST_LDO9_ON_VSEL_REG 0x54 |
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| 190 | #define RK818_BOOST_LDO9_SLP_VSEL_REG 0x55 |
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| 191 | #define RK818_BOOST_CTRL_REG 0x56 |
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| 192 | #define RK818_DCDC_ILMAX 0x90 |
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| 193 | #define RK818_USB_CTRL_REG 0xa1 |
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| 194 | |
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| 195 | #define RK818_H5V_EN BIT(0) |
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| 196 | #define RK818_REF_RDY_CTRL BIT(1) |
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| 197 | #define RK818_USB_ILIM_SEL_MASK 0xf |
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| 198 | #define RK818_USB_ILMIN_2000MA 0x7 |
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| 199 | #define RK818_USB_CHG_SD_VSEL_MASK 0x70 |
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| 200 | |
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| 201 | /* RK805 */ |
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| 202 | enum rk805_reg { |
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| 203 | RK805_ID_DCDC1, |
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| 204 | RK805_ID_DCDC2, |
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| 205 | RK805_ID_DCDC3, |
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| 206 | RK805_ID_DCDC4, |
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| 207 | RK805_ID_LDO1, |
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| 208 | RK805_ID_LDO2, |
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| 209 | RK805_ID_LDO3, |
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| 210 | }; |
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| 211 | |
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| 212 | /* CONFIG REGISTER */ |
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| 213 | #define RK805_VB_MON_REG 0x21 |
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| 214 | #define RK805_THERMAL_REG 0x22 |
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| 215 | |
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| 216 | /* POWER CHANNELS ENABLE REGISTER */ |
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| 217 | #define RK805_DCDC_EN_REG 0x23 |
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| 218 | #define RK805_SLP_DCDC_EN_REG 0x25 |
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| 219 | #define RK805_SLP_LDO_EN_REG 0x26 |
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| 220 | #define RK805_LDO_EN_REG 0x27 |
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| 221 | |
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| 222 | /* BUCK AND LDO CONFIG REGISTER */ |
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| 223 | #define RK805_BUCK_LDO_SLP_LP_EN_REG 0x2A |
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| 224 | #define RK805_BUCK1_CONFIG_REG 0x2E |
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| 225 | #define RK805_BUCK1_ON_VSEL_REG 0x2F |
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| 226 | #define RK805_BUCK1_SLP_VSEL_REG 0x30 |
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| 227 | #define RK805_BUCK2_CONFIG_REG 0x32 |
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| 228 | #define RK805_BUCK2_ON_VSEL_REG 0x33 |
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| 229 | #define RK805_BUCK2_SLP_VSEL_REG 0x34 |
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| 230 | #define RK805_BUCK3_CONFIG_REG 0x36 |
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| 231 | #define RK805_BUCK4_CONFIG_REG 0x37 |
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| 232 | #define RK805_BUCK4_ON_VSEL_REG 0x38 |
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| 233 | #define RK805_BUCK4_SLP_VSEL_REG 0x39 |
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| 234 | #define RK805_LDO1_ON_VSEL_REG 0x3B |
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| 235 | #define RK805_LDO1_SLP_VSEL_REG 0x3C |
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| 236 | #define RK805_LDO2_ON_VSEL_REG 0x3D |
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| 237 | #define RK805_LDO2_SLP_VSEL_REG 0x3E |
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| 238 | #define RK805_LDO3_ON_VSEL_REG 0x3F |
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| 239 | #define RK805_LDO3_SLP_VSEL_REG 0x40 |
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| 240 | |
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| 241 | /* INTERRUPT REGISTER */ |
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| 242 | #define RK805_PWRON_LP_INT_TIME_REG 0x47 |
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| 243 | #define RK805_PWRON_DB_REG 0x48 |
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| 244 | #define RK805_DEV_CTRL_REG 0x4B |
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| 245 | #define RK805_INT_STS_REG 0x4C |
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| 246 | #define RK805_INT_STS_MSK_REG 0x4D |
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| 247 | #define RK805_GPIO_IO_POL_REG 0x50 |
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| 248 | #define RK805_OUT_REG 0x52 |
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| 249 | #define RK805_ON_SOURCE_REG 0xAE |
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| 250 | #define RK805_OFF_SOURCE_REG 0xAF |
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| 251 | |
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| 252 | #define RK805_NUM_REGULATORS 7 |
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| 253 | |
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| 254 | #define RK805_PWRON_FALL_RISE_INT_EN 0x0 |
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| 255 | #define RK805_PWRON_FALL_RISE_INT_MSK 0x81 |
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| 256 | |
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| 257 | /* RK805 IRQ Definitions */ |
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| 258 | #define RK805_IRQ_PWRON_RISE 0 |
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| 259 | #define RK805_IRQ_VB_LOW 1 |
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| 260 | #define RK805_IRQ_PWRON 2 |
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| 261 | #define RK805_IRQ_PWRON_LP 3 |
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| 262 | #define RK805_IRQ_HOTDIE 4 |
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| 263 | #define RK805_IRQ_RTC_ALARM 5 |
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| 264 | #define RK805_IRQ_RTC_PERIOD 6 |
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| 265 | #define RK805_IRQ_PWRON_FALL 7 |
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| 266 | |
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| 267 | #define RK805_IRQ_PWRON_RISE_MSK BIT(0) |
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| 268 | #define RK805_IRQ_VB_LOW_MSK BIT(1) |
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| 269 | #define RK805_IRQ_PWRON_MSK BIT(2) |
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| 270 | #define RK805_IRQ_PWRON_LP_MSK BIT(3) |
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| 271 | #define RK805_IRQ_HOTDIE_MSK BIT(4) |
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| 272 | #define RK805_IRQ_RTC_ALARM_MSK BIT(5) |
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| 273 | #define RK805_IRQ_RTC_PERIOD_MSK BIT(6) |
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| 274 | #define RK805_IRQ_PWRON_FALL_MSK BIT(7) |
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| 275 | |
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| 276 | #define RK805_PWR_RISE_INT_STATUS BIT(0) |
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| 277 | #define RK805_VB_LOW_INT_STATUS BIT(1) |
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| 278 | #define RK805_PWRON_INT_STATUS BIT(2) |
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| 279 | #define RK805_PWRON_LP_INT_STATUS BIT(3) |
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| 280 | #define RK805_HOTDIE_INT_STATUS BIT(4) |
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| 281 | #define RK805_ALARM_INT_STATUS BIT(5) |
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| 282 | #define RK805_PERIOD_INT_STATUS BIT(6) |
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| 283 | #define RK805_PWR_FALL_INT_STATUS BIT(7) |
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| 284 | |
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| 285 | #define RK805_BUCK1_2_ILMAX_MASK (3 << 6) |
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| 286 | #define RK805_BUCK3_4_ILMAX_MASK (3 << 3) |
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| 287 | #define RK805_RTC_PERIOD_INT_MASK (1 << 6) |
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| 288 | #define RK805_RTC_ALARM_INT_MASK (1 << 5) |
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| 289 | #define RK805_INT_ALARM_EN (1 << 3) |
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| 290 | #define RK805_INT_TIMER_EN (1 << 2) |
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| 291 | |
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| 292 | /* RK806 */ |
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| 293 | #define RK806_POWER_EN0 0x0 |
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| 294 | #define RK806_POWER_EN1 0x1 |
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| 295 | #define RK806_POWER_EN2 0x2 |
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| 296 | #define RK806_POWER_EN3 0x3 |
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| 297 | #define RK806_POWER_EN4 0x4 |
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| 298 | #define RK806_POWER_EN5 0x5 |
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| 299 | #define RK806_POWER_SLP_EN0 0x6 |
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| 300 | #define RK806_POWER_SLP_EN1 0x7 |
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| 301 | #define RK806_POWER_SLP_EN2 0x8 |
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| 302 | #define RK806_POWER_DISCHRG_EN0 0x9 |
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| 303 | #define RK806_POWER_DISCHRG_EN1 0xA |
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| 304 | #define RK806_POWER_DISCHRG_EN2 0xB |
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| 305 | #define RK806_BUCK_FB_CONFIG 0xC |
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| 306 | #define RK806_SLP_LP_CONFIG 0xD |
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| 307 | #define RK806_POWER_FPWM_EN0 0xE |
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| 308 | #define RK806_POWER_FPWM_EN1 0xF |
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| 309 | #define RK806_BUCK1_CONFIG 0x10 |
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| 310 | #define RK806_BUCK2_CONFIG 0x11 |
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| 311 | #define RK806_BUCK3_CONFIG 0x12 |
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| 312 | #define RK806_BUCK4_CONFIG 0x13 |
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| 313 | #define RK806_BUCK5_CONFIG 0x14 |
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| 314 | #define RK806_BUCK6_CONFIG 0x15 |
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| 315 | #define RK806_BUCK7_CONFIG 0x16 |
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| 316 | #define RK806_BUCK8_CONFIG 0x17 |
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| 317 | #define RK806_BUCK9_CONFIG 0x18 |
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| 318 | #define RK806_BUCK10_CONFIG 0x19 |
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| 319 | #define RK806_BUCK1_ON_VSEL 0x1A |
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| 320 | #define RK806_BUCK2_ON_VSEL 0x1B |
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| 321 | #define RK806_BUCK3_ON_VSEL 0x1C |
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| 322 | #define RK806_BUCK4_ON_VSEL 0x1D |
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| 323 | #define RK806_BUCK5_ON_VSEL 0x1E |
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| 324 | #define RK806_BUCK6_ON_VSEL 0x1F |
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| 325 | #define RK806_BUCK7_ON_VSEL 0x20 |
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| 326 | #define RK806_BUCK8_ON_VSEL 0x21 |
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| 327 | #define RK806_BUCK9_ON_VSEL 0x22 |
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| 328 | #define RK806_BUCK10_ON_VSEL 0x23 |
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| 329 | #define RK806_BUCK1_SLP_VSEL 0x24 |
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| 330 | #define RK806_BUCK2_SLP_VSEL 0x25 |
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| 331 | #define RK806_BUCK3_SLP_VSEL 0x26 |
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| 332 | #define RK806_BUCK4_SLP_VSEL 0x27 |
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| 333 | #define RK806_BUCK5_SLP_VSEL 0x28 |
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| 334 | #define RK806_BUCK6_SLP_VSEL 0x29 |
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| 335 | #define RK806_BUCK7_SLP_VSEL 0x2A |
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| 336 | #define RK806_BUCK8_SLP_VSEL 0x2B |
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| 337 | #define RK806_BUCK9_SLP_VSEL 0x2D |
|---|
| 338 | #define RK806_BUCK10_SLP_VSEL 0x2E |
|---|
| 339 | #define RK806_BUCK_DEBUG1 0x30 |
|---|
| 340 | #define RK806_BUCK_DEBUG2 0x31 |
|---|
| 341 | #define RK806_BUCK_DEBUG3 0x32 |
|---|
| 342 | #define RK806_BUCK_DEBUG4 0x33 |
|---|
| 343 | #define RK806_BUCK_DEBUG5 0x34 |
|---|
| 344 | #define RK806_BUCK_DEBUG6 0x35 |
|---|
| 345 | #define RK806_BUCK_DEBUG7 0x36 |
|---|
| 346 | #define RK806_BUCK_DEBUG8 0x37 |
|---|
| 347 | #define RK806_BUCK_DEBUG9 0x38 |
|---|
| 348 | #define RK806_BUCK_DEBUG10 0x39 |
|---|
| 349 | #define RK806_BUCK_DEBUG11 0x3A |
|---|
| 350 | #define RK806_BUCK_DEBUG12 0x3B |
|---|
| 351 | #define RK806_BUCK_DEBUG13 0x3C |
|---|
| 352 | #define RK806_BUCK_DEBUG14 0x3D |
|---|
| 353 | #define RK806_BUCK_DEBUG15 0x3E |
|---|
| 354 | #define RK806_BUCK_DEBUG16 0x3F |
|---|
| 355 | #define RK806_BUCK_DEBUG17 0x40 |
|---|
| 356 | #define RK806_BUCK_DEBUG18 0x41 |
|---|
| 357 | #define RK806_NLDO_IMAX 0x42 |
|---|
| 358 | #define RK806_NLDO1_ON_VSEL 0x43 |
|---|
| 359 | #define RK806_NLDO2_ON_VSEL 0x44 |
|---|
| 360 | #define RK806_NLDO3_ON_VSEL 0x45 |
|---|
| 361 | #define RK806_NLDO4_ON_VSEL 0x46 |
|---|
| 362 | #define RK806_NLDO5_ON_VSEL 0x47 |
|---|
| 363 | #define RK806_NLDO1_SLP_VSEL 0x48 |
|---|
| 364 | #define RK806_NLDO2_SLP_VSEL 0x49 |
|---|
| 365 | #define RK806_NLDO3_SLP_VSEL 0x4A |
|---|
| 366 | #define RK806_NLDO4_SLP_VSEL 0x4B |
|---|
| 367 | #define RK806_NLDO5_SLP_VSEL 0x4C |
|---|
| 368 | #define RK806_PLDO_IMAX 0x4D |
|---|
| 369 | #define RK806_PLDO1_ON_VSEL 0x4E |
|---|
| 370 | #define RK806_PLDO2_ON_VSEL 0x4F |
|---|
| 371 | #define RK806_PLDO3_ON_VSEL 0x50 |
|---|
| 372 | #define RK806_PLDO4_ON_VSEL 0x51 |
|---|
| 373 | #define RK806_PLDO5_ON_VSEL 0x52 |
|---|
| 374 | #define RK806_PLDO6_ON_VSEL 0x53 |
|---|
| 375 | #define RK806_PLDO1_SLP_VSEL 0x54 |
|---|
| 376 | #define RK806_PLDO2_SLP_VSEL 0x55 |
|---|
| 377 | #define RK806_PLDO3_SLP_VSEL 0x56 |
|---|
| 378 | #define RK806_PLDO4_SLP_VSEL 0x57 |
|---|
| 379 | #define RK806_PLDO5_SLP_VSEL 0x58 |
|---|
| 380 | #define RK806_PLDO6_SLP_VSEL 0x59 |
|---|
| 381 | #define RK806_CHIP_NAME 0x5A |
|---|
| 382 | #define RK806_CHIP_VER 0x5B |
|---|
| 383 | #define RK806_OTP_VER 0x5C |
|---|
| 384 | #define RK806_SYS_STS 0x5D |
|---|
| 385 | #define RK806_SYS_CFG0 0x5E |
|---|
| 386 | #define RK806_SYS_CFG1 0x5F |
|---|
| 387 | #define RK806_SYS_OPTION 0x61 |
|---|
| 388 | #define RK806_SLEEP_CONFIG0 0x62 |
|---|
| 389 | #define RK806_SLEEP_CONFIG1 0x63 |
|---|
| 390 | #define RK806_SLEEP_CTR_SEL0 0x64 |
|---|
| 391 | #define RK806_SLEEP_CTR_SEL1 0x65 |
|---|
| 392 | #define RK806_SLEEP_CTR_SEL2 0x66 |
|---|
| 393 | #define RK806_SLEEP_CTR_SEL3 0x67 |
|---|
| 394 | #define RK806_SLEEP_CTR_SEL4 0x68 |
|---|
| 395 | #define RK806_SLEEP_CTR_SEL5 0x69 |
|---|
| 396 | #define RK806_DVS_CTRL_SEL0 0x6A |
|---|
| 397 | #define RK806_DVS_CTRL_SEL1 0x6B |
|---|
| 398 | #define RK806_DVS_CTRL_SEL2 0x6C |
|---|
| 399 | #define RK806_DVS_CTRL_SEL3 0x6D |
|---|
| 400 | #define RK806_DVS_CTRL_SEL4 0x6E |
|---|
| 401 | #define RK806_DVS_CTRL_SEL5 0x6F |
|---|
| 402 | #define RK806_DVS_START_CTRL 0x70 |
|---|
| 403 | #define RK806_SLEEP_GPIO 0x71 |
|---|
| 404 | #define RK806_SYS_CFG3 0x72 |
|---|
| 405 | #define RK806_ON_SOURCE 0x74 |
|---|
| 406 | #define RK806_OFF_SOURCE 0x75 |
|---|
| 407 | #define RK806_PWRON_KEY 0x76 |
|---|
| 408 | #define RK806_INT_STS0 0x77 |
|---|
| 409 | #define RK806_INT_MSK0 0x78 |
|---|
| 410 | #define RK806_INT_STS1 0x79 |
|---|
| 411 | #define RK806_INT_MSK1 0x7A |
|---|
| 412 | #define RK806_GPIO_INT_CONFIG 0x7B |
|---|
| 413 | #define RK806_DATA_REG0 0x7C |
|---|
| 414 | #define RK806_DATA_REG1 0x7D |
|---|
| 415 | #define RK806_DATA_REG2 0x7E |
|---|
| 416 | #define RK806_DATA_REG3 0x7F |
|---|
| 417 | #define RK806_DATA_REG4 0x80 |
|---|
| 418 | #define RK806_DATA_REG5 0x81 |
|---|
| 419 | #define RK806_DATA_REG6 0x82 |
|---|
| 420 | #define RK806_DATA_REG7 0x83 |
|---|
| 421 | #define RK806_DATA_REG8 0x84 |
|---|
| 422 | #define RK806_DATA_REG9 0x85 |
|---|
| 423 | #define RK806_DATA_REG10 0x86 |
|---|
| 424 | #define RK806_DATA_REG11 0x87 |
|---|
| 425 | #define RK806_DATA_REG12 0x88 |
|---|
| 426 | #define RK806_DATA_REG13 0x89 |
|---|
| 427 | #define RK806_DATA_REG14 0x8A |
|---|
| 428 | #define RK806_DATA_REG15 0x8B |
|---|
| 429 | #define RK806_TM_REG 0x8C |
|---|
| 430 | #define RK806_OTP_EN_REG 0x8D |
|---|
| 431 | #define RK806_FUNC_OTP_EN_REG 0x8E |
|---|
| 432 | #define RK806_TEST_REG1 0x8F |
|---|
| 433 | #define RK806_TEST_REG2 0x90 |
|---|
| 434 | #define RK806_TEST_REG3 0x91 |
|---|
| 435 | #define RK806_TEST_REG4 0x92 |
|---|
| 436 | #define RK806_TEST_REG5 0x93 |
|---|
| 437 | #define RK806_BUCK_VSEL_OTP_REG0 0x94 |
|---|
| 438 | #define RK806_BUCK_VSEL_OTP_REG1 0x95 |
|---|
| 439 | #define RK806_BUCK_VSEL_OTP_REG2 0x96 |
|---|
| 440 | #define RK806_BUCK_VSEL_OTP_REG3 0x97 |
|---|
| 441 | #define RK806_BUCK_VSEL_OTP_REG4 0x98 |
|---|
| 442 | #define RK806_BUCK_VSEL_OTP_REG5 0x99 |
|---|
| 443 | #define RK806_BUCK_VSEL_OTP_REG6 0x9A |
|---|
| 444 | #define RK806_BUCK_VSEL_OTP_REG7 0x9B |
|---|
| 445 | #define RK806_BUCK_VSEL_OTP_REG8 0x9C |
|---|
| 446 | #define RK806_BUCK_VSEL_OTP_REG9 0x9D |
|---|
| 447 | #define RK806_NLDO1_VSEL_OTP_REG0 0x9E |
|---|
| 448 | #define RK806_NLDO1_VSEL_OTP_REG1 0x9F |
|---|
| 449 | #define RK806_NLDO1_VSEL_OTP_REG2 0xA0 |
|---|
| 450 | #define RK806_NLDO1_VSEL_OTP_REG3 0xA1 |
|---|
| 451 | #define RK806_NLDO1_VSEL_OTP_REG4 0xA2 |
|---|
| 452 | #define RK806_PLDO_VSEL_OTP_REG0 0xA3 |
|---|
| 453 | #define RK806_PLDO_VSEL_OTP_REG1 0xA4 |
|---|
| 454 | #define RK806_PLDO_VSEL_OTP_REG2 0xA5 |
|---|
| 455 | #define RK806_PLDO_VSEL_OTP_REG3 0xA6 |
|---|
| 456 | #define RK806_PLDO_VSEL_OTP_REG4 0xA7 |
|---|
| 457 | #define RK806_PLDO_VSEL_OTP_REG5 0xA8 |
|---|
| 458 | #define RK806_BUCK_EN_OTP_REG1 0xA9 |
|---|
| 459 | #define RK806_NLDO_EN_OTP_REG1 0xAA |
|---|
| 460 | #define RK806_PLDO_EN_OTP_REG1 0xAB |
|---|
| 461 | #define RK806_BUCK_FB_RES_OTP_REG1 0xAC |
|---|
| 462 | #define RK806_OTP_RESEV_REG0 0xAD |
|---|
| 463 | #define RK806_OTP_RESEV_REG1 0xAE |
|---|
| 464 | #define RK806_OTP_RESEV_REG2 0xAF |
|---|
| 465 | #define RK806_OTP_RESEV_REG3 0xB0 |
|---|
| 466 | #define RK806_OTP_RESEV_REG4 0xB1 |
|---|
| 467 | #define RK806_BUCK_SEQ_REG0 0xB2 |
|---|
| 468 | #define RK806_BUCK_SEQ_REG1 0xB3 |
|---|
| 469 | #define RK806_BUCK_SEQ_REG2 0xB4 |
|---|
| 470 | #define RK806_BUCK_SEQ_REG3 0xB5 |
|---|
| 471 | #define RK806_BUCK_SEQ_REG4 0xB6 |
|---|
| 472 | #define RK806_BUCK_SEQ_REG5 0xB7 |
|---|
| 473 | #define RK806_BUCK_SEQ_REG6 0xB8 |
|---|
| 474 | #define RK806_BUCK_SEQ_REG7 0xB9 |
|---|
| 475 | #define RK806_BUCK_SEQ_REG8 0xBA |
|---|
| 476 | #define RK806_BUCK_SEQ_REG9 0xBB |
|---|
| 477 | #define RK806_BUCK_SEQ_REG10 0xBC |
|---|
| 478 | #define RK806_BUCK_SEQ_REG11 0xBD |
|---|
| 479 | #define RK806_BUCK_SEQ_REG12 0xBE |
|---|
| 480 | #define RK806_BUCK_SEQ_REG13 0xBF |
|---|
| 481 | #define RK806_BUCK_SEQ_REG14 0xC0 |
|---|
| 482 | #define RK806_BUCK_SEQ_REG15 0xC1 |
|---|
| 483 | #define RK806_BUCK_SEQ_REG16 0xC2 |
|---|
| 484 | #define RK806_BUCK_SEQ_REG17 0xC3 |
|---|
| 485 | #define RK806_HK_TRIM_REG1 0xC4 |
|---|
| 486 | #define RK806_HK_TRIM_REG2 0xC5 |
|---|
| 487 | #define RK806_BUCK_REF_TRIM_REG1 0xC6 |
|---|
| 488 | #define RK806_BUCK_REF_TRIM_REG2 0xC7 |
|---|
| 489 | #define RK806_BUCK_REF_TRIM_REG3 0xC8 |
|---|
| 490 | #define RK806_BUCK_REF_TRIM_REG4 0xC9 |
|---|
| 491 | #define RK806_BUCK_REF_TRIM_REG5 0xCA |
|---|
| 492 | #define RK806_BUCK_OSC_TRIM_REG1 0xCB |
|---|
| 493 | #define RK806_BUCK_OSC_TRIM_REG2 0xCC |
|---|
| 494 | #define RK806_BUCK_OSC_TRIM_REG3 0xCD |
|---|
| 495 | #define RK806_BUCK_OSC_TRIM_REG4 0xCE |
|---|
| 496 | #define RK806_BUCK_OSC_TRIM_REG5 0xCF |
|---|
| 497 | #define RK806_BUCK_TRIM_ZCDIOS_REG1 0xD0 |
|---|
| 498 | #define RK806_BUCK_TRIM_ZCDIOS_REG2 0xD1 |
|---|
| 499 | #define RK806_NLDO_TRIM_REG1 0xD2 |
|---|
| 500 | #define RK806_NLDO_TRIM_REG2 0xD3 |
|---|
| 501 | #define RK806_NLDO_TRIM_REG3 0xD4 |
|---|
| 502 | #define RK806_PLDO_TRIM_REG1 0xD5 |
|---|
| 503 | #define RK806_PLDO_TRIM_REG2 0xD6 |
|---|
| 504 | #define RK806_PLDO_TRIM_REG3 0xD7 |
|---|
| 505 | #define RK806_TRIM_ICOMP_REG1 0xD8 |
|---|
| 506 | #define RK806_TRIM_ICOMP_REG2 0xD9 |
|---|
| 507 | #define RK806_EFUSE_CONTROL_REGH 0xDA |
|---|
| 508 | #define RK806_FUSE_PROG_REG 0xDB |
|---|
| 509 | #define RK806_MAIN_FSM_STS_REG 0xDD |
|---|
| 510 | #define RK806_FSM_REG 0xDE |
|---|
| 511 | #define RK806_TOP_RESEV_OFFR 0xEC |
|---|
| 512 | #define RK806_TOP_RESEV_POR 0xED |
|---|
| 513 | #define RK806_BUCK_VRSN_REG1 0xEE |
|---|
| 514 | #define RK806_BUCK_VRSN_REG2 0xEF |
|---|
| 515 | #define RK806_NLDO_RLOAD_SEL_REG1 0xF0 |
|---|
| 516 | #define RK806_PLDO_RLOAD_SEL_REG1 0xF1 |
|---|
| 517 | #define RK806_PLDO_RLOAD_SEL_REG2 0xF2 |
|---|
| 518 | #define RK806_BUCK_CMIN_MX_REG1 0xF3 |
|---|
| 519 | #define RK806_BUCK_CMIN_MX_REG2 0xF4 |
|---|
| 520 | #define RK806_BUCK_FREQ_SET_REG1 0xF5 |
|---|
| 521 | #define RK806_BUCK_FREQ_SET_REG2 0xF6 |
|---|
| 522 | #define RK806_BUCK_RS_MEABS_REG1 0xF7 |
|---|
| 523 | #define RK806_BUCK_RS_MEABS_REG2 0xF8 |
|---|
| 524 | #define RK806_BUCK_RS_ZDLEB_REG1 0xF9 |
|---|
| 525 | #define RK806_BUCK_RS_ZDLEB_REG2 0xFA |
|---|
| 526 | #define RK806_BUCK_RSERVE_REG1 0xFB |
|---|
| 527 | #define RK806_BUCK_RSERVE_REG2 0xFC |
|---|
| 528 | #define RK806_BUCK_RSERVE_REG3 0xFD |
|---|
| 529 | #define RK806_BUCK_RSERVE_REG4 0xFE |
|---|
| 530 | #define RK806_BUCK_RSERVE_REG5 0xFF |
|---|
| 531 | |
|---|
| 532 | /* INT_STS Register field definitions */ |
|---|
| 533 | #define RK806_INT_STS_PWRON_FALL BIT(0) |
|---|
| 534 | #define RK806_INT_STS_PWRON_RISE BIT(1) |
|---|
| 535 | #define RK806_INT_STS_PWRON BIT(2) |
|---|
| 536 | #define RK806_INT_STS_PWRON_LP BIT(3) |
|---|
| 537 | #define RK806_INT_STS_HOTDIE BIT(4) |
|---|
| 538 | #define RK806_INT_STS_VDC_RISE BIT(5) |
|---|
| 539 | #define RK806_INT_STS_VDC_FALL BIT(6) |
|---|
| 540 | #define RK806_INT_STS_VB_LO BIT(7) |
|---|
| 541 | #define RK806_INT_STS_REV0 BIT(0) |
|---|
| 542 | #define RK806_INT_STS_REV1 BIT(1) |
|---|
| 543 | #define RK806_INT_STS_REV2 BIT(2) |
|---|
| 544 | #define RK806_INT_STS_CRC_ERROR BIT(3) |
|---|
| 545 | #define RK806_INT_STS_SLP3_GPIO BIT(4) |
|---|
| 546 | #define RK806_INT_STS_SLP2_GPIO BIT(5) |
|---|
| 547 | #define RK806_INT_STS_SLP1_GPIO BIT(6) |
|---|
| 548 | #define RK806_INT_STS_WDT BIT(7) |
|---|
| 549 | |
|---|
| 550 | /* SPI command */ |
|---|
| 551 | #define RK806_CMD_READ 0 |
|---|
| 552 | #define RK806_CMD_WRITE BIT(7) |
|---|
| 553 | #define RK806_CMD_CRC_EN BIT(6) |
|---|
| 554 | #define RK806_CMD_CRC_DIS 0 |
|---|
| 555 | #define RK806_CMD_LEN_MSK 0x0f |
|---|
| 556 | #define RK806_REG_H 0x00 |
|---|
| 557 | |
|---|
| 558 | #define VERSION_AB 0x01 |
|---|
| 559 | |
|---|
| 560 | enum rk806_reg_id { |
|---|
| 561 | RK806_ID_DCDC1 = 0, |
|---|
| 562 | RK806_ID_DCDC2, |
|---|
| 563 | RK806_ID_DCDC3, |
|---|
| 564 | RK806_ID_DCDC4, |
|---|
| 565 | RK806_ID_DCDC5, |
|---|
| 566 | RK806_ID_DCDC6, |
|---|
| 567 | RK806_ID_DCDC7, |
|---|
| 568 | RK806_ID_DCDC8, |
|---|
| 569 | RK806_ID_DCDC9, |
|---|
| 570 | RK806_ID_DCDC10, |
|---|
| 571 | |
|---|
| 572 | RK806_ID_NLDO1, |
|---|
| 573 | RK806_ID_NLDO2, |
|---|
| 574 | RK806_ID_NLDO3, |
|---|
| 575 | RK806_ID_NLDO4, |
|---|
| 576 | RK806_ID_NLDO5, |
|---|
| 577 | |
|---|
| 578 | RK806_ID_PLDO1, |
|---|
| 579 | RK806_ID_PLDO2, |
|---|
| 580 | RK806_ID_PLDO3, |
|---|
| 581 | RK806_ID_PLDO4, |
|---|
| 582 | RK806_ID_PLDO5, |
|---|
| 583 | RK806_ID_PLDO6, |
|---|
| 584 | RK806_ID_END, |
|---|
| 585 | }; |
|---|
| 586 | |
|---|
| 587 | /* Define the RK806 IRQ numbers */ |
|---|
| 588 | enum rk806_irqs { |
|---|
| 589 | /* INT_STS0 registers */ |
|---|
| 590 | RK806_IRQ_PWRON_FALL, |
|---|
| 591 | RK806_IRQ_PWRON_RISE, |
|---|
| 592 | RK806_IRQ_PWRON, |
|---|
| 593 | RK806_IRQ_PWRON_LP, |
|---|
| 594 | RK806_IRQ_HOTDIE, |
|---|
| 595 | RK806_IRQ_VDC_RISE, |
|---|
| 596 | RK806_IRQ_VDC_FALL, |
|---|
| 597 | RK806_IRQ_VB_LO, |
|---|
| 598 | |
|---|
| 599 | /* INT_STS0 registers */ |
|---|
| 600 | RK806_IRQ_REV0, |
|---|
| 601 | RK806_IRQ_REV1, |
|---|
| 602 | RK806_IRQ_REV2, |
|---|
| 603 | RK806_IRQ_CRC_ERROR, |
|---|
| 604 | RK806_IRQ_SLP3_GPIO, |
|---|
| 605 | RK806_IRQ_SLP2_GPIO, |
|---|
| 606 | RK806_IRQ_SLP1_GPIO, |
|---|
| 607 | RK806_IRQ_WDT, |
|---|
| 608 | }; |
|---|
| 609 | |
|---|
| 610 | /* VCC1 Low Voltage Threshold */ |
|---|
| 611 | enum rk806_lv_sel { |
|---|
| 612 | VB_LO_SEL_2800, |
|---|
| 613 | VB_LO_SEL_2900, |
|---|
| 614 | VB_LO_SEL_3000, |
|---|
| 615 | VB_LO_SEL_3100, |
|---|
| 616 | VB_LO_SEL_3200, |
|---|
| 617 | VB_LO_SEL_3300, |
|---|
| 618 | VB_LO_SEL_3400, |
|---|
| 619 | VB_LO_SEL_3500, |
|---|
| 620 | }; |
|---|
| 621 | |
|---|
| 622 | /* System Shutdown Voltage Select */ |
|---|
| 623 | enum rk806_uv_sel { |
|---|
| 624 | VB_UV_SEL_2700, |
|---|
| 625 | VB_UV_SEL_2800, |
|---|
| 626 | VB_UV_SEL_2900, |
|---|
| 627 | VB_UV_SEL_3000, |
|---|
| 628 | VB_UV_SEL_3100, |
|---|
| 629 | VB_UV_SEL_3200, |
|---|
| 630 | VB_UV_SEL_3300, |
|---|
| 631 | VB_UV_SEL_3400, |
|---|
| 632 | }; |
|---|
| 633 | |
|---|
| 634 | /* Pin Function */ |
|---|
| 635 | enum rk806_pwrctrl_fun { |
|---|
| 636 | PWRCTRL_NULL_FUN, |
|---|
| 637 | PWRCTRL_SLP_FUN, |
|---|
| 638 | PWRCTRL_POWOFF_FUN, |
|---|
| 639 | PWRCTRL_RST_FUN, |
|---|
| 640 | PWRCTRL_DVS_FUN, |
|---|
| 641 | PWRCTRL_GPIO_FUN, |
|---|
| 642 | }; |
|---|
| 643 | |
|---|
| 644 | /* Pin Polarity */ |
|---|
| 645 | enum rk806_pin_level { |
|---|
| 646 | POL_LOW, |
|---|
| 647 | POL_HIGH, |
|---|
| 648 | }; |
|---|
| 649 | |
|---|
| 650 | enum rk806_vsel_ctr_sel { |
|---|
| 651 | CTR_BY_NO_EFFECT, |
|---|
| 652 | CTR_BY_PWRCTRL1, |
|---|
| 653 | CTR_BY_PWRCTRL2, |
|---|
| 654 | CTR_BY_PWRCTRL3, |
|---|
| 655 | }; |
|---|
| 656 | |
|---|
| 657 | enum rk806_dvs_ctr_sel { |
|---|
| 658 | CTR_SEL_NO_EFFECT, |
|---|
| 659 | CTR_SEL_DVS_START1, |
|---|
| 660 | CTR_SEL_DVS_START2, |
|---|
| 661 | CTR_SEL_DVS_START3, |
|---|
| 662 | }; |
|---|
| 663 | |
|---|
| 664 | enum rk806_pin_dr_sel { |
|---|
| 665 | RK806_PIN_INPUT, |
|---|
| 666 | RK806_PIN_OUTPUT, |
|---|
| 667 | }; |
|---|
| 668 | |
|---|
| 669 | #define RK806_INT_POL_MSK BIT(1) |
|---|
| 670 | #define RK806_INT_POL_H BIT(1) |
|---|
| 671 | #define RK806_INT_POL_L 0 |
|---|
| 672 | |
|---|
| 673 | #define RK806_SLAVE_RESTART_FUN_MSK BIT(1) |
|---|
| 674 | #define RK806_SLAVE_RESTART_FUN_EN BIT(1) |
|---|
| 675 | #define RK806_SLAVE_RESTART_FUN_OFF 0 |
|---|
| 676 | |
|---|
| 677 | #define RK806_SYS_ENB2_2M_MSK BIT(1) |
|---|
| 678 | #define RK806_SYS_ENB2_2M_EN BIT(1) |
|---|
| 679 | #define RK806_SYS_ENB2_2M_OFF 0 |
|---|
| 680 | |
|---|
| 681 | enum rk806_int_fun { |
|---|
| 682 | RK806_INT_ONLY, |
|---|
| 683 | RK806_INT_ADN_WKUP, |
|---|
| 684 | }; |
|---|
| 685 | |
|---|
| 686 | enum rk806_dvs_mode { |
|---|
| 687 | RK806_DVS_NOT_SUPPORT, |
|---|
| 688 | RK806_DVS_START1, |
|---|
| 689 | RK806_DVS_START2, |
|---|
| 690 | RK806_DVS_START3, |
|---|
| 691 | RK806_DVS_PWRCTRL1, |
|---|
| 692 | RK806_DVS_PWRCTRL2, |
|---|
| 693 | RK806_DVS_PWRCTRL3, |
|---|
| 694 | RK806_DVS_START_PWRCTR1, |
|---|
| 695 | RK806_DVS_START_PWRCTR2, |
|---|
| 696 | RK806_DVS_START_PWRCTR3, |
|---|
| 697 | RK806_DVS_END, |
|---|
| 698 | }; |
|---|
| 699 | |
|---|
| 700 | /* RK808 IRQ Definitions */ |
|---|
| 701 | #define RK808_IRQ_VOUT_LO 0 |
|---|
| 702 | #define RK808_IRQ_VB_LO 1 |
|---|
| 703 | #define RK808_IRQ_PWRON 2 |
|---|
| 704 | #define RK808_IRQ_PWRON_LP 3 |
|---|
| 705 | #define RK808_IRQ_HOTDIE 4 |
|---|
| 706 | #define RK808_IRQ_RTC_ALARM 5 |
|---|
| 707 | #define RK808_IRQ_RTC_PERIOD 6 |
|---|
| 708 | #define RK808_IRQ_PLUG_IN_INT 7 |
|---|
| 709 | #define RK808_IRQ_PLUG_OUT_INT 8 |
|---|
| 710 | #define RK808_NUM_IRQ 9 |
|---|
| 711 | |
|---|
| 712 | #define RK808_IRQ_VOUT_LO_MSK BIT(0) |
|---|
| 713 | #define RK808_IRQ_VB_LO_MSK BIT(1) |
|---|
| 714 | #define RK808_IRQ_PWRON_MSK BIT(2) |
|---|
| 715 | #define RK808_IRQ_PWRON_LP_MSK BIT(3) |
|---|
| 716 | #define RK808_IRQ_HOTDIE_MSK BIT(4) |
|---|
| 717 | #define RK808_IRQ_RTC_ALARM_MSK BIT(5) |
|---|
| 718 | #define RK808_IRQ_RTC_PERIOD_MSK BIT(6) |
|---|
| 719 | #define RK808_IRQ_PLUG_IN_INT_MSK BIT(0) |
|---|
| 720 | #define RK808_IRQ_PLUG_OUT_INT_MSK BIT(1) |
|---|
| 721 | |
|---|
| 722 | /* RK818 IRQ Definitions */ |
|---|
| 723 | #define RK818_IRQ_VOUT_LO 0 |
|---|
| 724 | #define RK818_IRQ_VB_LO 1 |
|---|
| 725 | #define RK818_IRQ_PWRON 2 |
|---|
| 726 | #define RK818_IRQ_PWRON_LP 3 |
|---|
| 727 | #define RK818_IRQ_HOTDIE 4 |
|---|
| 728 | #define RK818_IRQ_RTC_ALARM 5 |
|---|
| 729 | #define RK818_IRQ_RTC_PERIOD 6 |
|---|
| 730 | #define RK818_IRQ_USB_OV 7 |
|---|
| 731 | #define RK818_IRQ_PLUG_IN 8 |
|---|
| 732 | #define RK818_IRQ_PLUG_OUT 9 |
|---|
| 733 | #define RK818_IRQ_CHG_OK 10 |
|---|
| 734 | #define RK818_IRQ_CHG_TE 11 |
|---|
| 735 | #define RK818_IRQ_CHG_TS1 12 |
|---|
| 736 | #define RK818_IRQ_TS2 13 |
|---|
| 737 | #define RK818_IRQ_CHG_CVTLIM 14 |
|---|
| 738 | #define RK818_IRQ_DISCHG_ILIM 15 |
|---|
| 739 | |
|---|
| 740 | #define RK818_IRQ_VOUT_LO_MSK BIT(0) |
|---|
| 741 | #define RK818_IRQ_VB_LO_MSK BIT(1) |
|---|
| 742 | #define RK818_IRQ_PWRON_MSK BIT(2) |
|---|
| 743 | #define RK818_IRQ_PWRON_LP_MSK BIT(3) |
|---|
| 744 | #define RK818_IRQ_HOTDIE_MSK BIT(4) |
|---|
| 745 | #define RK818_IRQ_RTC_ALARM_MSK BIT(5) |
|---|
| 746 | #define RK818_IRQ_RTC_PERIOD_MSK BIT(6) |
|---|
| 747 | #define RK818_IRQ_USB_OV_MSK BIT(7) |
|---|
| 748 | #define RK818_IRQ_PLUG_IN_MSK BIT(0) |
|---|
| 749 | #define RK818_IRQ_PLUG_OUT_MSK BIT(1) |
|---|
| 750 | #define RK818_IRQ_CHG_OK_MSK BIT(2) |
|---|
| 751 | #define RK818_IRQ_CHG_TE_MSK BIT(3) |
|---|
| 752 | #define RK818_IRQ_CHG_TS1_MSK BIT(4) |
|---|
| 753 | #define RK818_IRQ_TS2_MSK BIT(5) |
|---|
| 754 | #define RK818_IRQ_CHG_CVTLIM_MSK BIT(6) |
|---|
| 755 | #define RK818_IRQ_DISCHG_ILIM_MSK BIT(7) |
|---|
| 756 | |
|---|
| 757 | #define RK818_NUM_IRQ 16 |
|---|
| 758 | |
|---|
| 759 | #define RK808_VBAT_LOW_2V8 0x00 |
|---|
| 760 | #define RK808_VBAT_LOW_2V9 0x01 |
|---|
| 761 | #define RK808_VBAT_LOW_3V0 0x02 |
|---|
| 762 | #define RK808_VBAT_LOW_3V1 0x03 |
|---|
| 763 | #define RK808_VBAT_LOW_3V2 0x04 |
|---|
| 764 | #define RK808_VBAT_LOW_3V3 0x05 |
|---|
| 765 | #define RK808_VBAT_LOW_3V4 0x06 |
|---|
| 766 | #define RK808_VBAT_LOW_3V5 0x07 |
|---|
| 767 | #define VBAT_LOW_VOL_MASK (0x07 << 0) |
|---|
| 768 | #define EN_VABT_LOW_SHUT_DOWN (0x00 << 4) |
|---|
| 769 | #define EN_VBAT_LOW_IRQ (0x1 << 4) |
|---|
| 770 | #define VBAT_LOW_ACT_MASK (0x1 << 4) |
|---|
| 771 | |
|---|
| 772 | #define BUCK_ILMIN_MASK (7 << 0) |
|---|
| 773 | #define BOOST_ILMIN_MASK (7 << 0) |
|---|
| 774 | #define BUCK1_RATE_MASK (3 << 3) |
|---|
| 775 | #define BUCK2_RATE_MASK (3 << 3) |
|---|
| 776 | #define MASK_ALL 0xff |
|---|
| 777 | |
|---|
| 778 | #define BUCK_UV_ACT_MASK 0x0f |
|---|
| 779 | #define BUCK_UV_ACT_DISABLE 0 |
|---|
| 780 | |
|---|
| 781 | #define SWITCH2_EN BIT(6) |
|---|
| 782 | #define SWITCH1_EN BIT(5) |
|---|
| 783 | #define DEV_OFF_RST BIT(3) |
|---|
| 784 | #define DEV_RST BIT(2) |
|---|
| 785 | #define DEV_OFF BIT(0) |
|---|
| 786 | #define RTC_STOP BIT(0) |
|---|
| 787 | |
|---|
| 788 | #define VB_LO_ACT BIT(4) |
|---|
| 789 | #define VB_LO_SEL_3500MV (7 << 0) |
|---|
| 790 | |
|---|
| 791 | #define VOUT_LO_INT BIT(0) |
|---|
| 792 | #define CLK32KOUT2_EN BIT(0) |
|---|
| 793 | |
|---|
| 794 | #define TEMP115C 0x0c |
|---|
| 795 | #define TEMP_HOTDIE_MSK 0x0c |
|---|
| 796 | #define SLP_SD_MSK (0x3 << 2) |
|---|
| 797 | #define SHUTDOWN_FUN (0x2 << 2) |
|---|
| 798 | #define SLEEP_FUN (0x1 << 2) |
|---|
| 799 | #define RK8XX_ID_MSK 0xfff0 |
|---|
| 800 | #define PWM_MODE_MSK BIT(7) |
|---|
| 801 | #define FPWM_MODE BIT(7) |
|---|
| 802 | #define AUTO_PWM_MODE 0 |
|---|
| 803 | |
|---|
| 804 | enum rk817_reg_id { |
|---|
| 805 | RK817_ID_DCDC1 = 0, |
|---|
| 806 | RK817_ID_DCDC2, |
|---|
| 807 | RK817_ID_DCDC3, |
|---|
| 808 | RK817_ID_DCDC4, |
|---|
| 809 | RK817_ID_LDO1, |
|---|
| 810 | RK817_ID_LDO2, |
|---|
| 811 | RK817_ID_LDO3, |
|---|
| 812 | RK817_ID_LDO4, |
|---|
| 813 | RK817_ID_LDO5, |
|---|
| 814 | RK817_ID_LDO6, |
|---|
| 815 | RK817_ID_LDO7, |
|---|
| 816 | RK817_ID_LDO8, |
|---|
| 817 | RK817_ID_LDO9, |
|---|
| 818 | RK817_ID_BOOST, |
|---|
| 819 | RK817_ID_BOOST_OTG_SW, |
|---|
| 820 | RK817_NUM_REGULATORS |
|---|
| 821 | }; |
|---|
| 822 | |
|---|
| 823 | enum rk809_reg_id { |
|---|
| 824 | RK809_ID_DCDC5 = RK817_ID_BOOST, |
|---|
| 825 | RK809_ID_SW1, |
|---|
| 826 | RK809_ID_SW2, |
|---|
| 827 | RK809_NUM_REGULATORS |
|---|
| 828 | }; |
|---|
| 829 | |
|---|
| 830 | #define RK817_SECONDS_REG 0x00 |
|---|
| 831 | #define RK817_MINUTES_REG 0x01 |
|---|
| 832 | #define RK817_HOURS_REG 0x02 |
|---|
| 833 | #define RK817_DAYS_REG 0x03 |
|---|
| 834 | #define RK817_MONTHS_REG 0x04 |
|---|
| 835 | #define RK817_YEARS_REG 0x05 |
|---|
| 836 | #define RK817_WEEKS_REG 0x06 |
|---|
| 837 | #define RK817_ALARM_SECONDS_REG 0x07 |
|---|
| 838 | #define RK817_ALARM_MINUTES_REG 0x08 |
|---|
| 839 | #define RK817_ALARM_HOURS_REG 0x09 |
|---|
| 840 | #define RK817_ALARM_DAYS_REG 0x0a |
|---|
| 841 | #define RK817_ALARM_MONTHS_REG 0x0b |
|---|
| 842 | #define RK817_ALARM_YEARS_REG 0x0c |
|---|
| 843 | #define RK817_RTC_CTRL_REG 0xd |
|---|
| 844 | #define RK817_RTC_STATUS_REG 0xe |
|---|
| 845 | #define RK817_RTC_INT_REG 0xf |
|---|
| 846 | #define RK817_RTC_COMP_LSB_REG 0x10 |
|---|
| 847 | #define RK817_RTC_COMP_MSB_REG 0x11 |
|---|
| 848 | |
|---|
| 849 | /* RK817 Codec Registers */ |
|---|
| 850 | #define RK817_CODEC_DTOP_VUCTL 0x12 |
|---|
| 851 | #define RK817_CODEC_DTOP_VUCTIME 0x13 |
|---|
| 852 | #define RK817_CODEC_DTOP_LPT_SRST 0x14 |
|---|
| 853 | #define RK817_CODEC_DTOP_DIGEN_CLKE 0x15 |
|---|
| 854 | #define RK817_CODEC_AREF_RTCFG0 0x16 |
|---|
| 855 | #define RK817_CODEC_AREF_RTCFG1 0x17 |
|---|
| 856 | #define RK817_CODEC_AADC_CFG0 0x18 |
|---|
| 857 | #define RK817_CODEC_AADC_CFG1 0x19 |
|---|
| 858 | #define RK817_CODEC_DADC_VOLL 0x1a |
|---|
| 859 | #define RK817_CODEC_DADC_VOLR 0x1b |
|---|
| 860 | #define RK817_CODEC_DADC_SR_ACL0 0x1e |
|---|
| 861 | #define RK817_CODEC_DADC_ALC1 0x1f |
|---|
| 862 | #define RK817_CODEC_DADC_ALC2 0x20 |
|---|
| 863 | #define RK817_CODEC_DADC_NG 0x21 |
|---|
| 864 | #define RK817_CODEC_DADC_HPF 0x22 |
|---|
| 865 | #define RK817_CODEC_DADC_RVOLL 0x23 |
|---|
| 866 | #define RK817_CODEC_DADC_RVOLR 0x24 |
|---|
| 867 | #define RK817_CODEC_AMIC_CFG0 0x27 |
|---|
| 868 | #define RK817_CODEC_AMIC_CFG1 0x28 |
|---|
| 869 | #define RK817_CODEC_DMIC_PGA_GAIN 0x29 |
|---|
| 870 | #define RK817_CODEC_DMIC_LMT1 0x2a |
|---|
| 871 | #define RK817_CODEC_DMIC_LMT2 0x2b |
|---|
| 872 | #define RK817_CODEC_DMIC_NG1 0x2c |
|---|
| 873 | #define RK817_CODEC_DMIC_NG2 0x2d |
|---|
| 874 | #define RK817_CODEC_ADAC_CFG0 0x2e |
|---|
| 875 | #define RK817_CODEC_ADAC_CFG1 0x2f |
|---|
| 876 | #define RK817_CODEC_DDAC_POPD_DACST 0x30 |
|---|
| 877 | #define RK817_CODEC_DDAC_VOLL 0x31 |
|---|
| 878 | #define RK817_CODEC_DDAC_VOLR 0x32 |
|---|
| 879 | #define RK817_CODEC_DDAC_SR_LMT0 0x35 |
|---|
| 880 | #define RK817_CODEC_DDAC_LMT1 0x36 |
|---|
| 881 | #define RK817_CODEC_DDAC_LMT2 0x37 |
|---|
| 882 | #define RK817_CODEC_DDAC_MUTE_MIXCTL 0x38 |
|---|
| 883 | #define RK817_CODEC_DDAC_RVOLL 0x39 |
|---|
| 884 | #define RK817_CODEC_DDAC_RVOLR 0x3a |
|---|
| 885 | #define RK817_CODEC_AHP_ANTI0 0x3b |
|---|
| 886 | #define RK817_CODEC_AHP_ANTI1 0x3c |
|---|
| 887 | #define RK817_CODEC_AHP_CFG0 0x3d |
|---|
| 888 | #define RK817_CODEC_AHP_CFG1 0x3e |
|---|
| 889 | #define RK817_CODEC_AHP_CP 0x3f |
|---|
| 890 | #define RK817_CODEC_ACLASSD_CFG1 0x40 |
|---|
| 891 | #define RK817_CODEC_ACLASSD_CFG2 0x41 |
|---|
| 892 | #define RK817_CODEC_APLL_CFG0 0x42 |
|---|
| 893 | #define RK817_CODEC_APLL_CFG1 0x43 |
|---|
| 894 | #define RK817_CODEC_APLL_CFG2 0x44 |
|---|
| 895 | #define RK817_CODEC_APLL_CFG3 0x45 |
|---|
| 896 | #define RK817_CODEC_APLL_CFG4 0x46 |
|---|
| 897 | #define RK817_CODEC_APLL_CFG5 0x47 |
|---|
| 898 | #define RK817_CODEC_DI2S_CKM 0x48 |
|---|
| 899 | #define RK817_CODEC_DI2S_RSD 0x49 |
|---|
| 900 | #define RK817_CODEC_DI2S_RXCR1 0x4a |
|---|
| 901 | #define RK817_CODEC_DI2S_RXCR2 0x4b |
|---|
| 902 | #define RK817_CODEC_DI2S_RXCMD_TSD 0x4c |
|---|
| 903 | #define RK817_CODEC_DI2S_TXCR1 0x4d |
|---|
| 904 | #define RK817_CODEC_DI2S_TXCR2 0x4e |
|---|
| 905 | #define RK817_CODEC_DI2S_TXCR3_TXCMD 0x4f |
|---|
| 906 | |
|---|
| 907 | /* RK817_CODEC_DI2S_CKM */ |
|---|
| 908 | #define RK817_I2S_MODE_MASK (0x1 << 0) |
|---|
| 909 | #define RK817_I2S_MODE_MST (0x1 << 0) |
|---|
| 910 | #define RK817_I2S_MODE_SLV (0x0 << 0) |
|---|
| 911 | |
|---|
| 912 | /* RK817_CODEC_DDAC_MUTE_MIXCTL */ |
|---|
| 913 | #define DACMT_MASK (0x1 << 0) |
|---|
| 914 | #define DACMT_ENABLE (0x1 << 0) |
|---|
| 915 | #define DACMT_DISABLE (0x0 << 0) |
|---|
| 916 | |
|---|
| 917 | /* RK817_CODEC_DI2S_RXCR2 */ |
|---|
| 918 | #define VDW_RX_24BITS (0x17) |
|---|
| 919 | #define VDW_RX_16BITS (0x0f) |
|---|
| 920 | |
|---|
| 921 | /* RK817_CODEC_DI2S_TXCR2 */ |
|---|
| 922 | #define VDW_TX_24BITS (0x17) |
|---|
| 923 | #define VDW_TX_16BITS (0x0f) |
|---|
| 924 | |
|---|
| 925 | /* RK817_CODEC_AMIC_CFG0 */ |
|---|
| 926 | #define MIC_DIFF_MASK (0x1 << 7) |
|---|
| 927 | #define MIC_DIFF_DIS (0x0 << 7) |
|---|
| 928 | #define MIC_DIFF_EN (0x1 << 7) |
|---|
| 929 | |
|---|
| 930 | /* RK817 Battery Registers */ |
|---|
| 931 | #define RK817_GAS_GAUGE_ADC_CONFIG0 0x50 |
|---|
| 932 | #define RK817_GG_EN (0x1 << 7) |
|---|
| 933 | #define RK817_SYS_VOL_ADC_EN (0x1 << 6) |
|---|
| 934 | #define RK817_TS_ADC_EN (0x1 << 5) |
|---|
| 935 | #define RK817_USB_VOL_ADC_EN (0x1 << 4) |
|---|
| 936 | #define RK817_BAT_VOL_ADC_EN (0x1 << 3) |
|---|
| 937 | #define RK817_BAT_CUR_ADC_EN (0x1 << 2) |
|---|
| 938 | |
|---|
| 939 | #define RK817_GAS_GAUGE_ADC_CONFIG1 0x55 |
|---|
| 940 | |
|---|
| 941 | #define RK817_VOL_CUR_CALIB_UPD BIT(7) |
|---|
| 942 | |
|---|
| 943 | #define RK817_GAS_GAUGE_GG_CON 0x56 |
|---|
| 944 | #define RK817_GAS_GAUGE_GG_STS 0x57 |
|---|
| 945 | |
|---|
| 946 | #define RK817_BAT_CON (0x1 << 4) |
|---|
| 947 | #define RK817_RELAX_VOL_UPD (0x3 << 2) |
|---|
| 948 | #define RK817_RELAX_STS (0x1 << 1) |
|---|
| 949 | |
|---|
| 950 | #define RK817_GAS_GAUGE_RELAX_THRE_H 0x58 |
|---|
| 951 | #define RK817_GAS_GAUGE_RELAX_THRE_L 0x59 |
|---|
| 952 | #define RK817_GAS_GAUGE_OCV_THRE_VOL 0x62 |
|---|
| 953 | #define RK817_GAS_GAUGE_OCV_VOL_H 0x63 |
|---|
| 954 | #define RK817_GAS_GAUGE_OCV_VOL_L 0x64 |
|---|
| 955 | #define RK817_GAS_GAUGE_PWRON_VOL_H 0x6b |
|---|
| 956 | #define RK817_GAS_GAUGE_PWRON_VOL_L 0x6c |
|---|
| 957 | #define RK817_GAS_GAUGE_PWRON_CUR_H 0x6d |
|---|
| 958 | #define RK817_GAS_GAUGE_PWRON_CUR_L 0x6e |
|---|
| 959 | #define RK817_GAS_GAUGE_OFF_CNT 0x6f |
|---|
| 960 | #define RK817_GAS_GAUGE_Q_INIT_H3 0x70 |
|---|
| 961 | #define RK817_GAS_GAUGE_Q_INIT_H2 0x71 |
|---|
| 962 | #define RK817_GAS_GAUGE_Q_INIT_L1 0x72 |
|---|
| 963 | #define RK817_GAS_GAUGE_Q_INIT_L0 0x73 |
|---|
| 964 | #define RK817_GAS_GAUGE_Q_PRES_H3 0x74 |
|---|
| 965 | #define RK817_GAS_GAUGE_Q_PRES_H2 0x75 |
|---|
| 966 | #define RK817_GAS_GAUGE_Q_PRES_L1 0x76 |
|---|
| 967 | #define RK817_GAS_GAUGE_Q_PRES_L0 0x77 |
|---|
| 968 | #define RK817_GAS_GAUGE_BAT_VOL_H 0x78 |
|---|
| 969 | #define RK817_GAS_GAUGE_BAT_VOL_L 0x79 |
|---|
| 970 | #define RK817_GAS_GAUGE_BAT_CUR_H 0x7a |
|---|
| 971 | #define RK817_GAS_GAUGE_BAT_CUR_L 0x7b |
|---|
| 972 | #define RK817_GAS_GAUGE_USB_VOL_H 0x7e |
|---|
| 973 | #define RK817_GAS_GAUGE_USB_VOL_L 0x7f |
|---|
| 974 | #define RK817_GAS_GAUGE_SYS_VOL_H 0x80 |
|---|
| 975 | #define RK817_GAS_GAUGE_SYS_VOL_L 0x81 |
|---|
| 976 | #define RK817_GAS_GAUGE_Q_MAX_H3 0x82 |
|---|
| 977 | #define RK817_GAS_GAUGE_Q_MAX_H2 0x83 |
|---|
| 978 | #define RK817_GAS_GAUGE_Q_MAX_L1 0x84 |
|---|
| 979 | #define RK817_GAS_GAUGE_Q_MAX_L0 0x85 |
|---|
| 980 | #define RK817_GAS_GAUGE_SLEEP_CON_SAMP_CUR_H 0x8f |
|---|
| 981 | #define RK817_GAS_GAUGE_SLEEP_CON_SAMP_CUR_L 0x90 |
|---|
| 982 | #define RK817_GAS_GAUGE_CAL_OFFSET_H 0x91 |
|---|
| 983 | #define RK817_GAS_GAUGE_CAL_OFFSET_L 0x92 |
|---|
| 984 | #define RK817_GAS_GAUGE_VCALIB0_H 0x93 |
|---|
| 985 | #define RK817_GAS_GAUGE_VCALIB0_L 0x94 |
|---|
| 986 | #define RK817_GAS_GAUGE_VCALIB1_H 0x95 |
|---|
| 987 | #define RK817_GAS_GAUGE_VCALIB1_L 0x96 |
|---|
| 988 | #define RK817_GAS_GAUGE_IOFFSET_H 0x97 |
|---|
| 989 | #define RK817_GAS_GAUGE_IOFFSET_L 0x98 |
|---|
| 990 | #define RK817_GAS_GAUGE_BAT_R1 0x9a |
|---|
| 991 | #define RK817_GAS_GAUGE_BAT_R2 0x9b |
|---|
| 992 | #define RK817_GAS_GAUGE_BAT_R3 0x9c |
|---|
| 993 | #define RK817_GAS_GAUGE_DATA0 0x9d |
|---|
| 994 | #define RK817_GAS_GAUGE_DATA1 0x9e |
|---|
| 995 | #define RK817_GAS_GAUGE_DATA2 0x9f |
|---|
| 996 | #define RK817_GAS_GAUGE_DATA3 0xa0 |
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| 997 | #define RK817_GAS_GAUGE_DATA4 0xa1 |
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| 998 | #define RK817_GAS_GAUGE_DATA5 0xa2 |
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| 999 | #define RK817_GAS_GAUGE_CUR_ADC_K0 0xb0 |
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| 1000 | |
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| 1001 | #define RK817_POWER_EN_REG(i) (0xb1 + (i)) |
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| 1002 | #define RK817_POWER_SLP_EN_REG(i) (0xb5 + (i)) |
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| 1003 | |
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| 1004 | #define RK817_POWER_CONFIG (0xb9) |
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| 1005 | |
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| 1006 | #define RK817_BUCK_CONFIG_REG(i) (0xba + (i) * 3) |
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| 1007 | |
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| 1008 | #define RK817_BUCK1_ON_VSEL_REG 0xBB |
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| 1009 | #define RK817_BUCK1_SLP_VSEL_REG 0xBC |
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| 1010 | |
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| 1011 | #define RK817_BUCK2_CONFIG_REG 0xBD |
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| 1012 | #define RK817_BUCK2_ON_VSEL_REG 0xBE |
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| 1013 | #define RK817_BUCK2_SLP_VSEL_REG 0xBF |
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| 1014 | |
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| 1015 | #define RK817_BUCK3_CONFIG_REG 0xC0 |
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| 1016 | #define RK817_BUCK3_ON_VSEL_REG 0xC1 |
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| 1017 | #define RK817_BUCK3_SLP_VSEL_REG 0xC2 |
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| 1018 | |
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| 1019 | #define RK817_BUCK4_CONFIG_REG 0xC3 |
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| 1020 | #define RK817_BUCK4_ON_VSEL_REG 0xC4 |
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| 1021 | #define RK817_BUCK4_SLP_VSEL_REG 0xC5 |
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| 1022 | |
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| 1023 | #define RK817_LDO_ON_VSEL_REG(idx) (0xcc + (idx) * 2) |
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| 1024 | #define RK817_BOOST_OTG_CFG (0xde) |
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| 1025 | |
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| 1026 | #define RK817_PMIC_CHRG_OUT 0xe4 |
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| 1027 | #define RK817_CHRG_VOL_SEL (0x07 << 4) |
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| 1028 | #define RK817_CHRG_CUR_SEL (0x07 << 0) |
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| 1029 | |
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| 1030 | #define RK817_PMIC_CHRG_IN 0xe5 |
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| 1031 | #define RK817_USB_VLIM_EN (0x01 << 7) |
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| 1032 | #define RK817_USB_VLIM_SEL (0x07 << 4) |
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| 1033 | #define RK817_USB_ILIM_EN (0x01 << 3) |
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| 1034 | #define RK817_USB_ILIM_SEL (0x07 << 0) |
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| 1035 | #define RK817_PMIC_CHRG_TERM 0xe6 |
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| 1036 | #define RK817_CHRG_TERM_ANA_DIG (0x01 << 2) |
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| 1037 | #define RK817_CHRG_TERM_ANA_SEL (0x03 << 0) |
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| 1038 | #define RK817_CHRG_EN (0x01 << 6) |
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| 1039 | |
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| 1040 | #define RK817_PMIC_CHRG_STS 0xeb |
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| 1041 | #define RK817_BAT_EXS BIT(7) |
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| 1042 | #define RK817_CHG_STS (0x07 << 4) |
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| 1043 | |
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| 1044 | #define RK817_ID_MSB 0xed |
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| 1045 | #define RK817_ID_LSB 0xee |
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| 1046 | |
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| 1047 | #define RK817_SYS_STS 0xf0 |
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| 1048 | #define RK817_PLUG_IN_STS (0x1 << 6) |
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| 1049 | |
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| 1050 | #define RK817_SYS_CFG(i) (0xf1 + (i)) |
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| 1051 | |
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| 1052 | #define RK817_ON_SOURCE_REG 0xf5 |
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| 1053 | #define RK817_OFF_SOURCE_REG 0xf6 |
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| 1054 | |
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| 1055 | /* INTERRUPT REGISTER */ |
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| 1056 | #define RK817_INT_STS_REG0 0xf8 |
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| 1057 | #define RK817_INT_STS_MSK_REG0 0xf9 |
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| 1058 | #define RK817_INT_STS_REG1 0xfa |
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| 1059 | #define RK817_INT_STS_MSK_REG1 0xfb |
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| 1060 | #define RK817_INT_STS_REG2 0xfc |
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| 1061 | #define RK817_INT_STS_MSK_REG2 0xfd |
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| 1062 | #define RK817_GPIO_INT_CFG 0xfe |
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| 1063 | |
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| 1064 | /* IRQ Definitions */ |
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| 1065 | #define RK817_IRQ_PWRON_FALL 0 |
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| 1066 | #define RK817_IRQ_PWRON_RISE 1 |
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| 1067 | #define RK817_IRQ_PWRON 2 |
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| 1068 | #define RK817_IRQ_PWMON_LP 3 |
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| 1069 | #define RK817_IRQ_HOTDIE 4 |
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| 1070 | #define RK817_IRQ_RTC_ALARM 5 |
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| 1071 | #define RK817_IRQ_RTC_PERIOD 6 |
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| 1072 | #define RK817_IRQ_VB_LO 7 |
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| 1073 | #define RK817_IRQ_PLUG_IN 8 |
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| 1074 | #define RK817_IRQ_PLUG_OUT 9 |
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| 1075 | #define RK817_IRQ_CHRG_TERM 10 |
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| 1076 | #define RK817_IRQ_CHRG_TIME 11 |
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| 1077 | #define RK817_IRQ_CHRG_TS 12 |
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| 1078 | #define RK817_IRQ_USB_OV 13 |
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| 1079 | #define RK817_IRQ_CHRG_IN_CLMP 14 |
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| 1080 | #define RK817_IRQ_BAT_DIS_ILIM 15 |
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| 1081 | #define RK817_IRQ_GATE_GPIO 16 |
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| 1082 | #define RK817_IRQ_TS_GPIO 17 |
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| 1083 | #define RK817_IRQ_CODEC_PD 18 |
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| 1084 | #define RK817_IRQ_CODEC_PO 19 |
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| 1085 | #define RK817_IRQ_CLASSD_MUTE_DONE 20 |
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| 1086 | #define RK817_IRQ_CLASSD_OCP 21 |
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| 1087 | #define RK817_IRQ_BAT_OVP 22 |
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| 1088 | #define RK817_IRQ_CHRG_BAT_HI 23 |
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| 1089 | #define RK817_IRQ_END (RK817_IRQ_CHRG_BAT_HI + 1) |
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| 1090 | |
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| 1091 | /* |
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| 1092 | * rtc_ctrl 0xd |
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| 1093 | * same as 808, except bit4 |
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| 1094 | */ |
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| 1095 | #define RK817_RTC_CTRL_RSV4 BIT(4) |
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| 1096 | |
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| 1097 | /* power config 0xb9 */ |
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| 1098 | #define RK817_BUCK3_FB_RES_MSK BIT(6) |
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| 1099 | #define RK817_BUCK3_FB_RES_INTER BIT(6) |
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| 1100 | #define RK817_BUCK3_FB_RES_EXT 0 |
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| 1101 | |
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| 1102 | /* buck config 0xba */ |
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| 1103 | #define RK817_RAMP_RATE_OFFSET 6 |
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| 1104 | #define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET) |
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| 1105 | #define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET) |
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| 1106 | #define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET) |
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| 1107 | #define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET) |
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| 1108 | #define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET) |
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| 1109 | |
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| 1110 | /* sys_cfg1 0xf2 */ |
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| 1111 | #define RK817_HOTDIE_TEMP_MSK (0x3 << 4) |
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| 1112 | #define RK817_HOTDIE_85 (0x0 << 4) |
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| 1113 | #define RK817_HOTDIE_95 (0x1 << 4) |
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| 1114 | #define RK817_HOTDIE_105 (0x2 << 4) |
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| 1115 | #define RK817_HOTDIE_115 (0x3 << 4) |
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| 1116 | |
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| 1117 | #define RK817_TSD_TEMP_MSK BIT(6) |
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| 1118 | #define RK817_TSD_140 0 |
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| 1119 | #define RK817_TSD_160 BIT(6) |
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| 1120 | |
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| 1121 | #define RK817_CLK32KOUT2_EN BIT(7) |
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| 1122 | |
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| 1123 | /* sys_cfg3 0xf4 */ |
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| 1124 | #define RK817_SLPPIN_FUNC_MSK (0x3 << 3) |
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| 1125 | #define SLPPIN_NULL_FUN (0x0 << 3) |
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| 1126 | #define SLPPIN_SLP_FUN (0x1 << 3) |
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| 1127 | #define SLPPIN_DN_FUN (0x2 << 3) |
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| 1128 | #define SLPPIN_RST_FUN (0x3 << 3) |
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| 1129 | |
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| 1130 | #define RK817_RST_FUNC_MSK (0x3 << 6) |
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| 1131 | #define RK817_RST_FUNC_SFT (6) |
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| 1132 | #define RK817_RST_FUNC_CNT (3) |
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| 1133 | #define RK817_RST_FUNC_DEV (0) /* reset the dev */ |
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| 1134 | #define RK817_RST_FUNC_REG (0x1 << 6) /* reset the reg only */ |
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| 1135 | |
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| 1136 | #define RK817_SLPPOL_MSK BIT(5) |
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| 1137 | #define RK817_SLPPOL_H BIT(5) |
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| 1138 | #define RK817_SLPPOL_L (0) |
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| 1139 | |
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| 1140 | /* gpio&int 0xfe */ |
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| 1141 | #define RK817_INT_POL_MSK BIT(1) |
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| 1142 | #define RK817_INT_POL_H BIT(1) |
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| 1143 | #define RK817_INT_POL_L 0 |
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| 1144 | #define RK809_BUCK5_CONFIG(i) (RK817_BOOST_OTG_CFG + (i) * 1) |
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| 1145 | |
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| 1146 | enum { |
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| 1147 | BUCK_ILMIN_50MA, |
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| 1148 | BUCK_ILMIN_100MA, |
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| 1149 | BUCK_ILMIN_150MA, |
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| 1150 | BUCK_ILMIN_200MA, |
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| 1151 | BUCK_ILMIN_250MA, |
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| 1152 | BUCK_ILMIN_300MA, |
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| 1153 | BUCK_ILMIN_350MA, |
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| 1154 | BUCK_ILMIN_400MA, |
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| 1155 | }; |
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| 1156 | |
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| 1157 | enum { |
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| 1158 | BOOST_ILMIN_75MA, |
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| 1159 | BOOST_ILMIN_100MA, |
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| 1160 | BOOST_ILMIN_125MA, |
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| 1161 | BOOST_ILMIN_150MA, |
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| 1162 | BOOST_ILMIN_175MA, |
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| 1163 | BOOST_ILMIN_200MA, |
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| 1164 | BOOST_ILMIN_225MA, |
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| 1165 | BOOST_ILMIN_250MA, |
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| 1166 | }; |
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| 1167 | |
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| 1168 | enum { |
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| 1169 | RK805_BUCK1_2_ILMAX_2500MA, |
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| 1170 | RK805_BUCK1_2_ILMAX_3000MA, |
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| 1171 | RK805_BUCK1_2_ILMAX_3500MA, |
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| 1172 | RK805_BUCK1_2_ILMAX_4000MA, |
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| 1173 | }; |
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| 1174 | |
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| 1175 | enum { |
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| 1176 | RK805_BUCK3_ILMAX_1500MA, |
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| 1177 | RK805_BUCK3_ILMAX_2000MA, |
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| 1178 | RK805_BUCK3_ILMAX_2500MA, |
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| 1179 | RK805_BUCK3_ILMAX_3000MA, |
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| 1180 | }; |
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| 1181 | |
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| 1182 | enum { |
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| 1183 | RK805_BUCK4_ILMAX_2000MA, |
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| 1184 | RK805_BUCK4_ILMAX_2500MA, |
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| 1185 | RK805_BUCK4_ILMAX_3000MA, |
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| 1186 | RK805_BUCK4_ILMAX_3500MA, |
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| 1187 | }; |
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| 1188 | |
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| 1189 | enum { |
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| 1190 | RK805_ID = 0x8050, |
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| 1191 | RK806_ID = 0x8060, |
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| 1192 | RK808_ID = 0x0000, |
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| 1193 | RK809_ID = 0x8090, |
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| 1194 | RK817_ID = 0x8170, |
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| 1195 | RK818_ID = 0x8180, |
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| 1196 | }; |
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| 1197 | |
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| 1198 | struct rk808 { |
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| 1199 | struct device *dev; |
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| 1200 | struct regmap_irq_chip_data *irq_data; |
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| 1201 | struct regmap *regmap; |
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| 1202 | long variant; |
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| 1203 | const struct regmap_config *regmap_cfg; |
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| 1204 | const struct regmap_irq_chip *regmap_irq_chip; |
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| 1205 | }; |
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| 1206 | |
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| 1207 | void rk8xx_shutdown(struct device *dev); |
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| 1208 | int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap *regmap); |
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| 1209 | int rk8xx_suspend(struct device *dev); |
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| 1210 | int rk8xx_resume(struct device *dev); |
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| 1211 | |
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| 1212 | #endif /* __LINUX_REGULATOR_RK808_H */ |
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| 1213 | |
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