| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * MFD core driver for Ricoh RN5T618 PMIC |
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| 4 | * |
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| 5 | * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __LINUX_MFD_RN5T618_H |
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| 9 | #define __LINUX_MFD_RN5T618_H |
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| 10 | |
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| 11 | #include <linux/regmap.h> |
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| 12 | |
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| 13 | #define RN5T618_LSIVER 0x00 |
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| 14 | #define RN5T618_OTPVER 0x01 |
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| 15 | #define RN5T618_IODAC 0x02 |
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| 16 | #define RN5T618_VINDAC 0x03 |
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| 17 | #define RN5T618_OUT32KEN 0x05 |
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| 18 | #define RN5T618_CPUCNT 0x06 |
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| 19 | #define RN5T618_PSWR 0x07 |
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| 20 | #define RN5T618_PONHIS 0x09 |
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| 21 | #define RN5T618_POFFHIS 0x0a |
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| 22 | #define RN5T618_WATCHDOG 0x0b |
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| 23 | #define RN5T618_WATCHDOGCNT 0x0c |
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| 24 | #define RN5T618_PWRFUNC 0x0d |
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| 25 | #define RN5T618_SLPCNT 0x0e |
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| 26 | #define RN5T618_REPCNT 0x0f |
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| 27 | #define RN5T618_PWRONTIMSET 0x10 |
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| 28 | #define RN5T618_NOETIMSETCNT 0x11 |
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| 29 | #define RN5T618_PWRIREN 0x12 |
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| 30 | #define RN5T618_PWRIRQ 0x13 |
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| 31 | #define RN5T618_PWRMON 0x14 |
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| 32 | #define RN5T618_PWRIRSEL 0x15 |
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| 33 | #define RN5T618_DC1_SLOT 0x16 |
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| 34 | #define RN5T618_DC2_SLOT 0x17 |
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| 35 | #define RN5T618_DC3_SLOT 0x18 |
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| 36 | #define RN5T618_DC4_SLOT 0x19 |
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| 37 | #define RN5T618_LDO1_SLOT 0x1b |
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| 38 | #define RN5T618_LDO2_SLOT 0x1c |
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| 39 | #define RN5T618_LDO3_SLOT 0x1d |
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| 40 | #define RN5T618_LDO4_SLOT 0x1e |
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| 41 | #define RN5T618_LDO5_SLOT 0x1f |
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| 42 | #define RN5T618_PSO0_SLOT 0x25 |
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| 43 | #define RN5T618_PSO1_SLOT 0x26 |
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| 44 | #define RN5T618_PSO2_SLOT 0x27 |
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| 45 | #define RN5T618_PSO3_SLOT 0x28 |
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| 46 | #define RN5T618_LDORTC1_SLOT 0x2a |
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| 47 | #define RN5T618_DC1CTL 0x2c |
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| 48 | #define RN5T618_DC1CTL2 0x2d |
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| 49 | #define RN5T618_DC2CTL 0x2e |
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| 50 | #define RN5T618_DC2CTL2 0x2f |
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| 51 | #define RN5T618_DC3CTL 0x30 |
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| 52 | #define RN5T618_DC3CTL2 0x31 |
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| 53 | #define RN5T618_DC4CTL 0x32 |
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| 54 | #define RN5T618_DC4CTL2 0x33 |
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| 55 | #define RN5T618_DC5CTL 0x34 |
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| 56 | #define RN5T618_DC5CTL2 0x35 |
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| 57 | #define RN5T618_DC1DAC 0x36 |
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| 58 | #define RN5T618_DC2DAC 0x37 |
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| 59 | #define RN5T618_DC3DAC 0x38 |
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| 60 | #define RN5T618_DC4DAC 0x39 |
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| 61 | #define RN5T618_DC5DAC 0x3a |
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| 62 | #define RN5T618_DC1DAC_SLP 0x3b |
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| 63 | #define RN5T618_DC2DAC_SLP 0x3c |
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| 64 | #define RN5T618_DC3DAC_SLP 0x3d |
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| 65 | #define RN5T618_DC4DAC_SLP 0x3e |
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| 66 | #define RN5T618_DCIREN 0x40 |
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| 67 | #define RN5T618_DCIRQ 0x41 |
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| 68 | #define RN5T618_DCIRMON 0x42 |
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| 69 | #define RN5T618_LDOEN1 0x44 |
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| 70 | #define RN5T618_LDOEN2 0x45 |
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| 71 | #define RN5T618_LDODIS 0x46 |
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| 72 | #define RN5T618_LDO1DAC 0x4c |
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| 73 | #define RN5T618_LDO2DAC 0x4d |
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| 74 | #define RN5T618_LDO3DAC 0x4e |
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| 75 | #define RN5T618_LDO4DAC 0x4f |
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| 76 | #define RN5T618_LDO5DAC 0x50 |
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| 77 | #define RN5T618_LDO6DAC 0x51 |
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| 78 | #define RN5T618_LDO7DAC 0x52 |
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| 79 | #define RN5T618_LDO8DAC 0x53 |
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| 80 | #define RN5T618_LDO9DAC 0x54 |
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| 81 | #define RN5T618_LDO10DAC 0x55 |
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| 82 | #define RN5T618_LDORTCDAC 0x56 |
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| 83 | #define RN5T618_LDORTC2DAC 0x57 |
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| 84 | #define RN5T618_LDO1DAC_SLP 0x58 |
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| 85 | #define RN5T618_LDO2DAC_SLP 0x59 |
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| 86 | #define RN5T618_LDO3DAC_SLP 0x5a |
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| 87 | #define RN5T618_LDO4DAC_SLP 0x5b |
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| 88 | #define RN5T618_LDO5DAC_SLP 0x5c |
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| 89 | #define RN5T618_ADCCNT1 0x64 |
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| 90 | #define RN5T618_ADCCNT2 0x65 |
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| 91 | #define RN5T618_ADCCNT3 0x66 |
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| 92 | #define RN5T618_ILIMDATAH 0x68 |
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| 93 | #define RN5T618_ILIMDATAL 0x69 |
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| 94 | #define RN5T618_VBATDATAH 0x6a |
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| 95 | #define RN5T618_VBATDATAL 0x6b |
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| 96 | #define RN5T618_VADPDATAH 0x6c |
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| 97 | #define RN5T618_VADPDATAL 0x6d |
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| 98 | #define RN5T618_VUSBDATAH 0x6e |
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| 99 | #define RN5T618_VUSBDATAL 0x6f |
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| 100 | #define RN5T618_VSYSDATAH 0x70 |
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| 101 | #define RN5T618_VSYSDATAL 0x71 |
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| 102 | #define RN5T618_VTHMDATAH 0x72 |
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| 103 | #define RN5T618_VTHMDATAL 0x73 |
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| 104 | #define RN5T618_AIN1DATAH 0x74 |
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| 105 | #define RN5T618_AIN1DATAL 0x75 |
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| 106 | #define RN5T618_AIN0DATAH 0x76 |
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| 107 | #define RN5T618_AIN0DATAL 0x77 |
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| 108 | #define RN5T618_ILIMTHL 0x78 |
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| 109 | #define RN5T618_ILIMTHH 0x79 |
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| 110 | #define RN5T618_VBATTHL 0x7a |
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| 111 | #define RN5T618_VBATTHH 0x7b |
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| 112 | #define RN5T618_VADPTHL 0x7c |
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| 113 | #define RN5T618_VADPTHH 0x7d |
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| 114 | #define RN5T618_VUSBTHL 0x7e |
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| 115 | #define RN5T618_VUSBTHH 0x7f |
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| 116 | #define RN5T618_VSYSTHL 0x80 |
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| 117 | #define RN5T618_VSYSTHH 0x81 |
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| 118 | #define RN5T618_VTHMTHL 0x82 |
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| 119 | #define RN5T618_VTHMTHH 0x83 |
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| 120 | #define RN5T618_AIN1THL 0x84 |
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| 121 | #define RN5T618_AIN1THH 0x85 |
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| 122 | #define RN5T618_AIN0THL 0x86 |
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| 123 | #define RN5T618_AIN0THH 0x87 |
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| 124 | #define RN5T618_EN_ADCIR1 0x88 |
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| 125 | #define RN5T618_EN_ADCIR2 0x89 |
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| 126 | #define RN5T618_EN_ADCIR3 0x8a |
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| 127 | #define RN5T618_IR_ADC1 0x8c |
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| 128 | #define RN5T618_IR_ADC2 0x8d |
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| 129 | #define RN5T618_IR_ADC3 0x8e |
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| 130 | #define RN5T618_IOSEL 0x90 |
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| 131 | #define RN5T618_IOOUT 0x91 |
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| 132 | #define RN5T618_GPEDGE1 0x92 |
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| 133 | #define RN5T618_GPEDGE2 0x93 |
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| 134 | #define RN5T618_EN_GPIR 0x94 |
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| 135 | #define RN5T618_IR_GPR 0x95 |
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| 136 | #define RN5T618_IR_GPF 0x96 |
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| 137 | #define RN5T618_MON_IOIN 0x97 |
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| 138 | #define RN5T618_GPLED_FUNC 0x98 |
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| 139 | #define RN5T618_INTPOL 0x9c |
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| 140 | #define RN5T618_INTEN 0x9d |
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| 141 | #define RN5T618_INTMON 0x9e |
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| 142 | |
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| 143 | #define RN5T618_RTC_SECONDS 0xA0 |
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| 144 | #define RN5T618_RTC_MDAY 0xA4 |
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| 145 | #define RN5T618_RTC_MONTH 0xA5 |
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| 146 | #define RN5T618_RTC_YEAR 0xA6 |
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| 147 | #define RN5T618_RTC_ADJUST 0xA7 |
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| 148 | #define RN5T618_RTC_ALARM_Y_SEC 0xA8 |
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| 149 | #define RN5T618_RTC_DAL_MONTH 0xAC |
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| 150 | #define RN5T618_RTC_CTRL1 0xAE |
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| 151 | #define RN5T618_RTC_CTRL2 0xAF |
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| 152 | |
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| 153 | #define RN5T618_PREVINDAC 0xb0 |
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| 154 | #define RN5T618_BATDAC 0xb1 |
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| 155 | #define RN5T618_CHGCTL1 0xb3 |
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| 156 | #define RN5T618_CHGCTL2 0xb4 |
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| 157 | #define RN5T618_VSYSSET 0xb5 |
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| 158 | #define RN5T618_REGISET1 0xb6 |
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| 159 | #define RN5T618_REGISET2 0xb7 |
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| 160 | #define RN5T618_CHGISET 0xb8 |
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| 161 | #define RN5T618_TIMSET 0xb9 |
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| 162 | #define RN5T618_BATSET1 0xba |
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| 163 | #define RN5T618_BATSET2 0xbb |
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| 164 | #define RN5T618_DIESET 0xbc |
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| 165 | #define RN5T618_CHGSTATE 0xbd |
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| 166 | #define RN5T618_CHGCTRL_IRFMASK 0xbe |
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| 167 | #define RN5T618_CHGSTAT_IRFMASK1 0xbf |
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| 168 | #define RN5T618_CHGSTAT_IRFMASK2 0xc0 |
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| 169 | #define RN5T618_CHGERR_IRFMASK 0xc1 |
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| 170 | #define RN5T618_CHGCTRL_IRR 0xc2 |
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| 171 | #define RN5T618_CHGSTAT_IRR1 0xc3 |
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| 172 | #define RN5T618_CHGSTAT_IRR2 0xc4 |
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| 173 | #define RN5T618_CHGERR_IRR 0xc5 |
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| 174 | #define RN5T618_CHGCTRL_MONI 0xc6 |
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| 175 | #define RN5T618_CHGSTAT_MONI1 0xc7 |
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| 176 | #define RN5T618_CHGSTAT_MONI2 0xc8 |
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| 177 | #define RN5T618_CHGERR_MONI 0xc9 |
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| 178 | #define RN5T618_CHGCTRL_DETMOD1 0xca |
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| 179 | #define RN5T618_CHGCTRL_DETMOD2 0xcb |
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| 180 | #define RN5T618_CHGSTAT_DETMOD1 0xcc |
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| 181 | #define RN5T618_CHGSTAT_DETMOD2 0xcd |
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| 182 | #define RN5T618_CHGSTAT_DETMOD3 0xce |
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| 183 | #define RN5T618_CHGERR_DETMOD1 0xcf |
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| 184 | #define RN5T618_CHGERR_DETMOD2 0xd0 |
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| 185 | #define RN5T618_CHGOSCCTL 0xd4 |
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| 186 | #define RN5T618_CHGOSCSCORESET1 0xd5 |
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| 187 | #define RN5T618_CHGOSCSCORESET2 0xd6 |
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| 188 | #define RN5T618_CHGOSCSCORESET3 0xd7 |
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| 189 | #define RN5T618_CHGOSCFREQSET1 0xd8 |
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| 190 | #define RN5T618_CHGOSCFREQSET2 0xd9 |
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| 191 | #define RN5T618_GCHGDET 0xda |
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| 192 | #define RN5T618_CONTROL 0xe0 |
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| 193 | #define RN5T618_SOC 0xe1 |
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| 194 | #define RN5T618_RE_CAP_H 0xe2 |
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| 195 | #define RN5T618_RE_CAP_L 0xe3 |
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| 196 | #define RN5T618_FA_CAP_H 0xe4 |
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| 197 | #define RN5T618_FA_CAP_L 0xe5 |
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| 198 | #define RN5T618_AGE 0xe6 |
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| 199 | #define RN5T618_TT_EMPTY_H 0xe7 |
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| 200 | #define RN5T618_TT_EMPTY_L 0xe8 |
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| 201 | #define RN5T618_TT_FULL_H 0xe9 |
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| 202 | #define RN5T618_TT_FULL_L 0xea |
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| 203 | #define RN5T618_VOLTAGE_1 0xeb |
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| 204 | #define RN5T618_VOLTAGE_0 0xec |
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| 205 | #define RN5T618_TEMP_1 0xed |
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| 206 | #define RN5T618_TEMP_0 0xee |
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| 207 | #define RN5T618_CC_CTRL 0xef |
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| 208 | #define RN5T618_CC_COUNT2 0xf0 |
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| 209 | #define RN5T618_CC_COUNT1 0xf1 |
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| 210 | #define RN5T618_CC_COUNT0 0xf2 |
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| 211 | #define RN5T618_CC_SUMREG3 0xf3 |
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| 212 | #define RN5T618_CC_SUMREG2 0xf4 |
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| 213 | #define RN5T618_CC_SUMREG1 0xf5 |
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| 214 | #define RN5T618_CC_SUMREG0 0xf6 |
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| 215 | #define RN5T618_CC_OFFREG1 0xf7 |
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| 216 | #define RN5T618_CC_OFFREG0 0xf8 |
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| 217 | #define RN5T618_CC_GAINREG1 0xf9 |
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| 218 | #define RN5T618_CC_GAINREG0 0xfa |
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| 219 | #define RN5T618_CC_AVEREG1 0xfb |
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| 220 | #define RN5T618_CC_AVEREG0 0xfc |
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| 221 | #define RN5T618_MAX_REG 0xfc |
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| 222 | |
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| 223 | #define RN5T618_REPCNT_REPWRON BIT(0) |
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| 224 | #define RN5T618_SLPCNT_SWPWROFF BIT(0) |
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| 225 | #define RN5T618_WATCHDOG_WDOGEN BIT(2) |
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| 226 | #define RN5T618_WATCHDOG_WDOGTIM_M (BIT(0) | BIT(1)) |
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| 227 | #define RN5T618_WATCHDOG_WDOGTIM_S 0 |
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| 228 | #define RN5T618_PWRIRQ_IR_WDOG BIT(6) |
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| 229 | |
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| 230 | #define RN5T618_POFFHIS_PWRON BIT(0) |
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| 231 | #define RN5T618_POFFHIS_TSHUT BIT(1) |
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| 232 | #define RN5T618_POFFHIS_VINDET BIT(2) |
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| 233 | #define RN5T618_POFFHIS_IODET BIT(3) |
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| 234 | #define RN5T618_POFFHIS_CPU BIT(4) |
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| 235 | #define RN5T618_POFFHIS_WDG BIT(5) |
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| 236 | #define RN5T618_POFFHIS_DCLIM BIT(6) |
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| 237 | #define RN5T618_POFFHIS_N_OE BIT(7) |
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| 238 | |
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| 239 | enum { |
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| 240 | RN5T618_DCDC1, |
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| 241 | RN5T618_DCDC2, |
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| 242 | RN5T618_DCDC3, |
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| 243 | RN5T618_DCDC4, |
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| 244 | RN5T618_DCDC5, |
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| 245 | RN5T618_LDO1, |
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| 246 | RN5T618_LDO2, |
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| 247 | RN5T618_LDO3, |
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| 248 | RN5T618_LDO4, |
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| 249 | RN5T618_LDO5, |
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| 250 | RN5T618_LDO6, |
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| 251 | RN5T618_LDO7, |
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| 252 | RN5T618_LDO8, |
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| 253 | RN5T618_LDO9, |
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| 254 | RN5T618_LDO10, |
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| 255 | RN5T618_LDORTC1, |
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| 256 | RN5T618_LDORTC2, |
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| 257 | RN5T618_REG_NUM, |
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| 258 | }; |
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| 259 | |
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| 260 | enum { |
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| 261 | RN5T567 = 0, |
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| 262 | RN5T618, |
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| 263 | RC5T619, |
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| 264 | }; |
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| 265 | |
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| 266 | /* RN5T618 IRQ definitions */ |
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| 267 | enum { |
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| 268 | RN5T618_IRQ_SYS = 0, |
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| 269 | RN5T618_IRQ_DCDC, |
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| 270 | RN5T618_IRQ_RTC, |
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| 271 | RN5T618_IRQ_ADC, |
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| 272 | RN5T618_IRQ_GPIO, |
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| 273 | RN5T618_IRQ_CHG, |
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| 274 | RN5T618_NR_IRQS, |
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| 275 | }; |
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| 276 | |
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| 277 | struct rn5t618 { |
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| 278 | struct regmap *regmap; |
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| 279 | struct device *dev; |
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| 280 | long variant; |
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| 281 | |
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| 282 | int irq; |
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| 283 | struct regmap_irq_chip_data *irq_data; |
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| 284 | }; |
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| 285 | |
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| 286 | #endif /* __LINUX_MFD_RN5T618_H */ |
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| 287 | |
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