1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Copyright 2021 ROHM Semiconductors. |
4 | * |
5 | * Author: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> |
6 | * |
7 | * Copyright 2014 Embest Technology Co. Ltd. Inc. |
8 | * |
9 | * Author: yanglsh@embest-tech.com |
10 | */ |
11 | |
12 | #ifndef _MFD_BD71815_H |
13 | #define _MFD_BD71815_H |
14 | |
15 | #include <linux/regmap.h> |
16 | |
17 | enum { |
18 | BD71815_BUCK1 = 0, |
19 | BD71815_BUCK2, |
20 | BD71815_BUCK3, |
21 | BD71815_BUCK4, |
22 | BD71815_BUCK5, |
23 | /* General Purpose */ |
24 | BD71815_LDO1, |
25 | BD71815_LDO2, |
26 | BD71815_LDO3, |
27 | /* LDOs for SD Card and SD Card Interface */ |
28 | BD71815_LDO4, |
29 | BD71815_LDO5, |
30 | /* LDO for DDR Reference Voltage */ |
31 | BD71815_LDODVREF, |
32 | /* LDO for Low-Power State Retention */ |
33 | BD71815_LDOLPSR, |
34 | BD71815_WLED, |
35 | BD71815_REGULATOR_CNT, |
36 | }; |
37 | |
38 | #define BD71815_SUPPLY_STATE_ENABLED 0x1 |
39 | |
40 | enum { |
41 | BD71815_REG_DEVICE = 0, |
42 | BD71815_REG_PWRCTRL, |
43 | BD71815_REG_BUCK1_MODE, |
44 | BD71815_REG_BUCK2_MODE, |
45 | BD71815_REG_BUCK3_MODE, |
46 | BD71815_REG_BUCK4_MODE, |
47 | BD71815_REG_BUCK5_MODE, |
48 | BD71815_REG_BUCK1_VOLT_H, |
49 | BD71815_REG_BUCK1_VOLT_L, |
50 | BD71815_REG_BUCK2_VOLT_H, |
51 | BD71815_REG_BUCK2_VOLT_L, |
52 | BD71815_REG_BUCK3_VOLT, |
53 | BD71815_REG_BUCK4_VOLT, |
54 | BD71815_REG_BUCK5_VOLT, |
55 | BD71815_REG_LED_CTRL, |
56 | BD71815_REG_LED_DIMM, |
57 | BD71815_REG_LDO_MODE1, |
58 | BD71815_REG_LDO_MODE2, |
59 | BD71815_REG_LDO_MODE3, |
60 | BD71815_REG_LDO_MODE4, |
61 | BD71815_REG_LDO1_VOLT, |
62 | BD71815_REG_LDO2_VOLT, |
63 | BD71815_REG_LDO3_VOLT, |
64 | BD71815_REG_LDO4_VOLT, |
65 | BD71815_REG_LDO5_VOLT_H, |
66 | BD71815_REG_LDO5_VOLT_L, |
67 | BD71815_REG_BUCK_PD_DIS, |
68 | BD71815_REG_LDO_PD_DIS, |
69 | BD71815_REG_GPO, |
70 | BD71815_REG_OUT32K, |
71 | BD71815_REG_SEC, |
72 | BD71815_REG_MIN, |
73 | BD71815_REG_HOUR, |
74 | BD71815_REG_WEEK, |
75 | BD71815_REG_DAY, |
76 | BD71815_REG_MONTH, |
77 | BD71815_REG_YEAR, |
78 | BD71815_REG_ALM0_SEC, |
79 | |
80 | BD71815_REG_ALM1_SEC = 0x2C, |
81 | |
82 | BD71815_REG_ALM0_MASK = 0x33, |
83 | BD71815_REG_ALM1_MASK, |
84 | BD71815_REG_ALM2, |
85 | BD71815_REG_TRIM, |
86 | BD71815_REG_CONF, |
87 | BD71815_REG_SYS_INIT, |
88 | BD71815_REG_CHG_STATE, |
89 | BD71815_REG_CHG_LAST_STATE, |
90 | BD71815_REG_BAT_STAT, |
91 | BD71815_REG_DCIN_STAT, |
92 | BD71815_REG_VSYS_STAT, |
93 | BD71815_REG_CHG_STAT, |
94 | BD71815_REG_CHG_WDT_STAT, |
95 | BD71815_REG_BAT_TEMP, |
96 | BD71815_REG_IGNORE_0, |
97 | BD71815_REG_INHIBIT_0, |
98 | BD71815_REG_DCIN_CLPS, |
99 | BD71815_REG_VSYS_REG, |
100 | BD71815_REG_VSYS_MAX, |
101 | BD71815_REG_VSYS_MIN, |
102 | BD71815_REG_CHG_SET1, |
103 | BD71815_REG_CHG_SET2, |
104 | BD71815_REG_CHG_WDT_PRE, |
105 | BD71815_REG_CHG_WDT_FST, |
106 | BD71815_REG_CHG_IPRE, |
107 | BD71815_REG_CHG_IFST, |
108 | BD71815_REG_CHG_IFST_TERM, |
109 | BD71815_REG_CHG_VPRE, |
110 | BD71815_REG_CHG_VBAT_1, |
111 | BD71815_REG_CHG_VBAT_2, |
112 | BD71815_REG_CHG_VBAT_3, |
113 | BD71815_REG_CHG_LED_1, |
114 | BD71815_REG_VF_TH, |
115 | BD71815_REG_BAT_SET_1, |
116 | BD71815_REG_BAT_SET_2, |
117 | BD71815_REG_BAT_SET_3, |
118 | BD71815_REG_ALM_VBAT_TH_U, |
119 | BD71815_REG_ALM_VBAT_TH_L, |
120 | BD71815_REG_ALM_DCIN_TH, |
121 | BD71815_REG_ALM_VSYS_TH, |
122 | BD71815_REG_VM_IBAT_U, |
123 | BD71815_REG_VM_IBAT_L, |
124 | BD71815_REG_VM_VBAT_U, |
125 | BD71815_REG_VM_VBAT_L, |
126 | BD71815_REG_VM_BTMP, |
127 | BD71815_REG_VM_VTH, |
128 | BD71815_REG_VM_DCIN_U, |
129 | BD71815_REG_VM_DCIN_L, |
130 | BD71815_REG_VM_VSYS, |
131 | BD71815_REG_VM_VF, |
132 | BD71815_REG_VM_OCI_PRE_U, |
133 | BD71815_REG_VM_OCI_PRE_L, |
134 | BD71815_REG_VM_OCV_PRE_U, |
135 | BD71815_REG_VM_OCV_PRE_L, |
136 | BD71815_REG_VM_OCI_PST_U, |
137 | BD71815_REG_VM_OCI_PST_L, |
138 | BD71815_REG_VM_OCV_PST_U, |
139 | BD71815_REG_VM_OCV_PST_L, |
140 | BD71815_REG_VM_SA_VBAT_U, |
141 | BD71815_REG_VM_SA_VBAT_L, |
142 | BD71815_REG_VM_SA_IBAT_U, |
143 | BD71815_REG_VM_SA_IBAT_L, |
144 | BD71815_REG_CC_CTRL, |
145 | BD71815_REG_CC_BATCAP1_TH_U, |
146 | BD71815_REG_CC_BATCAP1_TH_L, |
147 | BD71815_REG_CC_BATCAP2_TH_U, |
148 | BD71815_REG_CC_BATCAP2_TH_L, |
149 | BD71815_REG_CC_BATCAP3_TH_U, |
150 | BD71815_REG_CC_BATCAP3_TH_L, |
151 | BD71815_REG_CC_STAT, |
152 | BD71815_REG_CC_CCNTD_3, |
153 | BD71815_REG_CC_CCNTD_2, |
154 | BD71815_REG_CC_CCNTD_1, |
155 | BD71815_REG_CC_CCNTD_0, |
156 | BD71815_REG_CC_CURCD_U, |
157 | BD71815_REG_CC_CURCD_L, |
158 | BD71815_REG_VM_OCUR_THR_1, |
159 | BD71815_REG_VM_OCUR_DUR_1, |
160 | BD71815_REG_VM_OCUR_THR_2, |
161 | BD71815_REG_VM_OCUR_DUR_2, |
162 | BD71815_REG_VM_OCUR_THR_3, |
163 | BD71815_REG_VM_OCUR_DUR_3, |
164 | BD71815_REG_VM_OCUR_MON, |
165 | BD71815_REG_VM_BTMP_OV_THR, |
166 | BD71815_REG_VM_BTMP_OV_DUR, |
167 | BD71815_REG_VM_BTMP_LO_THR, |
168 | BD71815_REG_VM_BTMP_LO_DUR, |
169 | BD71815_REG_VM_BTMP_MON, |
170 | BD71815_REG_INT_EN_01, |
171 | |
172 | BD71815_REG_INT_EN_11 = 0x95, |
173 | BD71815_REG_INT_EN_12, |
174 | BD71815_REG_INT_STAT, |
175 | BD71815_REG_INT_STAT_01, |
176 | BD71815_REG_INT_STAT_02, |
177 | BD71815_REG_INT_STAT_03, |
178 | BD71815_REG_INT_STAT_04, |
179 | BD71815_REG_INT_STAT_05, |
180 | BD71815_REG_INT_STAT_06, |
181 | BD71815_REG_INT_STAT_07, |
182 | BD71815_REG_INT_STAT_08, |
183 | BD71815_REG_INT_STAT_09, |
184 | BD71815_REG_INT_STAT_10, |
185 | BD71815_REG_INT_STAT_11, |
186 | BD71815_REG_INT_STAT_12, |
187 | BD71815_REG_INT_UPDATE, |
188 | |
189 | BD71815_REG_VM_VSYS_U = 0xC0, |
190 | BD71815_REG_VM_VSYS_L, |
191 | BD71815_REG_VM_SA_VSYS_U, |
192 | BD71815_REG_VM_SA_VSYS_L, |
193 | |
194 | BD71815_REG_VM_SA_IBAT_MIN_U = 0xD0, |
195 | BD71815_REG_VM_SA_IBAT_MIN_L, |
196 | BD71815_REG_VM_SA_IBAT_MAX_U, |
197 | BD71815_REG_VM_SA_IBAT_MAX_L, |
198 | BD71815_REG_VM_SA_VBAT_MIN_U, |
199 | BD71815_REG_VM_SA_VBAT_MIN_L, |
200 | BD71815_REG_VM_SA_VBAT_MAX_U, |
201 | BD71815_REG_VM_SA_VBAT_MAX_L, |
202 | BD71815_REG_VM_SA_VSYS_MIN_U, |
203 | BD71815_REG_VM_SA_VSYS_MIN_L, |
204 | BD71815_REG_VM_SA_VSYS_MAX_U, |
205 | BD71815_REG_VM_SA_VSYS_MAX_L, |
206 | BD71815_REG_VM_SA_MINMAX_CLR, |
207 | |
208 | BD71815_REG_REX_CCNTD_3 = 0xE0, |
209 | BD71815_REG_REX_CCNTD_2, |
210 | BD71815_REG_REX_CCNTD_1, |
211 | BD71815_REG_REX_CCNTD_0, |
212 | BD71815_REG_REX_SA_VBAT_U, |
213 | BD71815_REG_REX_SA_VBAT_L, |
214 | BD71815_REG_REX_CTRL_1, |
215 | BD71815_REG_REX_CTRL_2, |
216 | BD71815_REG_FULL_CCNTD_3, |
217 | BD71815_REG_FULL_CCNTD_2, |
218 | BD71815_REG_FULL_CCNTD_1, |
219 | BD71815_REG_FULL_CCNTD_0, |
220 | BD71815_REG_FULL_CTRL, |
221 | |
222 | BD71815_REG_CCNTD_CHG_3 = 0xF0, |
223 | BD71815_REG_CCNTD_CHG_2, |
224 | |
225 | BD71815_REG_TEST_MODE = 0xFE, |
226 | BD71815_MAX_REGISTER, |
227 | }; |
228 | |
229 | /* BD71815_REG_BUCK1_MODE bits */ |
230 | #define BD71815_BUCK_RAMPRATE_MASK 0xC0 |
231 | #define BD71815_BUCK_RAMPRATE_10P00MV 0x0 |
232 | #define BD71815_BUCK_RAMPRATE_5P00MV 0x01 |
233 | #define BD71815_BUCK_RAMPRATE_2P50MV 0x02 |
234 | #define BD71815_BUCK_RAMPRATE_1P25MV 0x03 |
235 | |
236 | #define BD71815_BUCK_PWM_FIXED BIT(4) |
237 | #define BD71815_BUCK_SNVS_ON BIT(3) |
238 | #define BD71815_BUCK_RUN_ON BIT(2) |
239 | #define BD71815_BUCK_LPSR_ON BIT(1) |
240 | #define BD71815_BUCK_SUSP_ON BIT(0) |
241 | |
242 | /* BD71815_REG_BUCK1_VOLT_H bits */ |
243 | #define BD71815_BUCK_DVSSEL BIT(7) |
244 | #define BD71815_BUCK_STBY_DVS BIT(6) |
245 | #define BD71815_VOLT_MASK 0x3F |
246 | #define BD71815_BUCK1_H_DEFAULT 0x14 |
247 | #define BD71815_BUCK1_L_DEFAULT 0x14 |
248 | |
249 | /* BD71815_REG_BUCK2_VOLT_H bits */ |
250 | #define BD71815_BUCK2_H_DEFAULT 0x14 |
251 | #define BD71815_BUCK2_L_DEFAULT 0x14 |
252 | |
253 | /* WLED output */ |
254 | /* current register mask */ |
255 | #define LED_DIMM_MASK 0x3f |
256 | /* LED enable bits at LED_CTRL reg */ |
257 | #define LED_CHGDONE_EN BIT(4) |
258 | #define LED_RUN_ON BIT(2) |
259 | #define LED_LPSR_ON BIT(1) |
260 | #define LED_SUSP_ON BIT(0) |
261 | |
262 | /* BD71815_REG_LDO1_CTRL bits */ |
263 | #define LDO1_EN BIT(0) |
264 | #define LDO2_EN BIT(1) |
265 | #define LDO3_EN BIT(2) |
266 | #define DVREF_EN BIT(3) |
267 | #define VOSNVS_SW_EN BIT(4) |
268 | |
269 | /* LDO_MODE1_register */ |
270 | #define LDO1_SNVS_ON BIT(7) |
271 | #define LDO1_RUN_ON BIT(6) |
272 | #define LDO1_LPSR_ON BIT(5) |
273 | #define LDO1_SUSP_ON BIT(4) |
274 | /* set => register control, unset => GPIO control */ |
275 | #define LDO4_MODE_MASK BIT(3) |
276 | #define LDO4_MODE_I2C BIT(3) |
277 | #define LDO4_MODE_GPIO 0 |
278 | /* set => register control, unset => start when DCIN connected */ |
279 | #define LDO3_MODE_MASK BIT(2) |
280 | #define LDO3_MODE_I2C BIT(2) |
281 | #define LDO3_MODE_DCIN 0 |
282 | |
283 | /* LDO_MODE2 register */ |
284 | #define LDO3_SNVS_ON BIT(7) |
285 | #define LDO3_RUN_ON BIT(6) |
286 | #define LDO3_LPSR_ON BIT(5) |
287 | #define LDO3_SUSP_ON BIT(4) |
288 | #define LDO2_SNVS_ON BIT(3) |
289 | #define LDO2_RUN_ON BIT(2) |
290 | #define LDO2_LPSR_ON BIT(1) |
291 | #define LDO2_SUSP_ON BIT(0) |
292 | |
293 | |
294 | /* LDO_MODE3 register */ |
295 | #define LDO5_SNVS_ON BIT(7) |
296 | #define LDO5_RUN_ON BIT(6) |
297 | #define LDO5_LPSR_ON BIT(5) |
298 | #define LDO5_SUSP_ON BIT(4) |
299 | #define LDO4_SNVS_ON BIT(3) |
300 | #define LDO4_RUN_ON BIT(2) |
301 | #define LDO4_LPSR_ON BIT(1) |
302 | #define LDO4_SUSP_ON BIT(0) |
303 | |
304 | /* LDO_MODE4 register */ |
305 | #define DVREF_SNVS_ON BIT(7) |
306 | #define DVREF_RUN_ON BIT(6) |
307 | #define DVREF_LPSR_ON BIT(5) |
308 | #define DVREF_SUSP_ON BIT(4) |
309 | #define LDO_LPSR_SNVS_ON BIT(3) |
310 | #define LDO_LPSR_RUN_ON BIT(2) |
311 | #define LDO_LPSR_LPSR_ON BIT(1) |
312 | #define LDO_LPSR_SUSP_ON BIT(0) |
313 | |
314 | /* BD71815_REG_OUT32K bits */ |
315 | #define OUT32K_EN BIT(0) |
316 | #define OUT32K_MODE BIT(1) |
317 | #define OUT32K_MODE_CMOS BIT(1) |
318 | #define OUT32K_MODE_OPEN_DRAIN 0 |
319 | |
320 | /* BD71815_REG_BAT_STAT bits */ |
321 | #define BAT_DET BIT(5) |
322 | #define BAT_DET_OFFSET 5 |
323 | #define BAT_DET_DONE BIT(4) |
324 | #define VBAT_OV BIT(3) |
325 | #define DBAT_DET BIT(0) |
326 | |
327 | /* BD71815_REG_VBUS_STAT bits */ |
328 | #define VBUS_DET BIT(0) |
329 | |
330 | #define BD71815_REG_RTC_START BD71815_REG_SEC |
331 | #define BD71815_REG_RTC_ALM_START BD71815_REG_ALM0_SEC |
332 | |
333 | /* BD71815_REG_ALM0_MASK bits */ |
334 | #define A0_ONESEC BIT(7) |
335 | |
336 | /* BD71815_REG_INT_EN_00 bits */ |
337 | #define ALMALE BIT(0) |
338 | |
339 | /* BD71815_REG_INT_STAT_03 bits */ |
340 | #define DCIN_MON_DET BIT(1) |
341 | #define DCIN_MON_RES BIT(0) |
342 | #define POWERON_LONG BIT(2) |
343 | #define POWERON_MID BIT(3) |
344 | #define POWERON_SHORT BIT(4) |
345 | #define POWERON_PRESS BIT(5) |
346 | |
347 | /* BD71805_REG_INT_STAT_08 bits */ |
348 | #define VBAT_MON_DET BIT(1) |
349 | #define VBAT_MON_RES BIT(0) |
350 | |
351 | /* BD71805_REG_INT_STAT_11 bits */ |
352 | #define INT_STAT_11_VF_DET BIT(7) |
353 | #define INT_STAT_11_VF_RES BIT(6) |
354 | #define INT_STAT_11_VF125_DET BIT(5) |
355 | #define INT_STAT_11_VF125_RES BIT(4) |
356 | #define INT_STAT_11_OVTMP_DET BIT(3) |
357 | #define INT_STAT_11_OVTMP_RES BIT(2) |
358 | #define INT_STAT_11_LOTMP_DET BIT(1) |
359 | #define INT_STAT_11_LOTMP_RES BIT(0) |
360 | |
361 | #define VBAT_MON_DET BIT(1) |
362 | #define VBAT_MON_RES BIT(0) |
363 | |
364 | /* BD71815_REG_PWRCTRL bits */ |
365 | #define RESTARTEN BIT(0) |
366 | |
367 | /* BD71815_REG_GPO bits */ |
368 | #define READY_FORCE_LOW BIT(2) |
369 | #define BD71815_GPIO_DRIVE_MASK BIT(4) |
370 | #define BD71815_GPIO_OPEN_DRAIN 0 |
371 | #define BD71815_GPIO_CMOS BIT(4) |
372 | |
373 | /* BD71815 interrupt masks */ |
374 | enum { |
375 | BD71815_INT_EN_01_BUCKAST_MASK = 0x0F, |
376 | BD71815_INT_EN_02_DCINAST_MASK = 0x3E, |
377 | BD71815_INT_EN_03_DCINAST_MASK = 0x3F, |
378 | BD71815_INT_EN_04_VSYSAST_MASK = 0xCF, |
379 | BD71815_INT_EN_05_CHGAST_MASK = 0xFC, |
380 | BD71815_INT_EN_06_BATAST_MASK = 0xF3, |
381 | BD71815_INT_EN_07_BMONAST_MASK = 0xFE, |
382 | BD71815_INT_EN_08_BMONAST_MASK = 0x03, |
383 | BD71815_INT_EN_09_BMONAST_MASK = 0x07, |
384 | BD71815_INT_EN_10_BMONAST_MASK = 0x3F, |
385 | BD71815_INT_EN_11_TMPAST_MASK = 0xFF, |
386 | BD71815_INT_EN_12_ALMAST_MASK = 0x07, |
387 | }; |
388 | /* BD71815 interrupt irqs */ |
389 | enum { |
390 | /* BUCK reg interrupts */ |
391 | BD71815_INT_BUCK1_OCP, |
392 | BD71815_INT_BUCK2_OCP, |
393 | BD71815_INT_BUCK3_OCP, |
394 | BD71815_INT_BUCK4_OCP, |
395 | BD71815_INT_BUCK5_OCP, |
396 | BD71815_INT_LED_OVP, |
397 | BD71815_INT_LED_OCP, |
398 | BD71815_INT_LED_SCP, |
399 | /* DCIN1 interrupts */ |
400 | BD71815_INT_DCIN_RMV, |
401 | BD71815_INT_CLPS_OUT, |
402 | BD71815_INT_CLPS_IN, |
403 | BD71815_INT_DCIN_OVP_RES, |
404 | BD71815_INT_DCIN_OVP_DET, |
405 | /* DCIN2 interrupts */ |
406 | BD71815_INT_DCIN_MON_RES, |
407 | BD71815_INT_DCIN_MON_DET, |
408 | BD71815_INT_WDOG, |
409 | /* Vsys INT_STAT_04 */ |
410 | BD71815_INT_VSYS_UV_RES, |
411 | BD71815_INT_VSYS_UV_DET, |
412 | BD71815_INT_VSYS_LOW_RES, |
413 | BD71815_INT_VSYS_LOW_DET, |
414 | BD71815_INT_VSYS_MON_RES, |
415 | BD71815_INT_VSYS_MON_DET, |
416 | /* Charger INT_STAT_05 */ |
417 | BD71815_INT_CHG_WDG_TEMP, |
418 | BD71815_INT_CHG_WDG_TIME, |
419 | BD71815_INT_CHG_RECHARGE_RES, |
420 | BD71815_INT_CHG_RECHARGE_DET, |
421 | BD71815_INT_CHG_RANGED_TEMP_TRANSITION, |
422 | BD71815_INT_CHG_STATE_TRANSITION, |
423 | /* Battery INT_STAT_06 */ |
424 | BD71815_INT_BAT_TEMP_NORMAL, |
425 | BD71815_INT_BAT_TEMP_ERANGE, |
426 | BD71815_INT_BAT_REMOVED, |
427 | BD71815_INT_BAT_DETECTED, |
428 | BD71815_INT_THERM_REMOVED, |
429 | BD71815_INT_THERM_DETECTED, |
430 | /* Battery Mon 1 INT_STAT_07 */ |
431 | BD71815_INT_BAT_DEAD, |
432 | BD71815_INT_BAT_SHORTC_RES, |
433 | BD71815_INT_BAT_SHORTC_DET, |
434 | BD71815_INT_BAT_LOW_VOLT_RES, |
435 | BD71815_INT_BAT_LOW_VOLT_DET, |
436 | BD71815_INT_BAT_OVER_VOLT_RES, |
437 | BD71815_INT_BAT_OVER_VOLT_DET, |
438 | /* Battery Mon 2 INT_STAT_08 */ |
439 | BD71815_INT_BAT_MON_RES, |
440 | BD71815_INT_BAT_MON_DET, |
441 | /* Battery Mon 3 (Coulomb counter) INT_STAT_09 */ |
442 | BD71815_INT_BAT_CC_MON1, |
443 | BD71815_INT_BAT_CC_MON2, |
444 | BD71815_INT_BAT_CC_MON3, |
445 | /* Battery Mon 4 INT_STAT_10 */ |
446 | BD71815_INT_BAT_OVER_CURR_1_RES, |
447 | BD71815_INT_BAT_OVER_CURR_1_DET, |
448 | BD71815_INT_BAT_OVER_CURR_2_RES, |
449 | BD71815_INT_BAT_OVER_CURR_2_DET, |
450 | BD71815_INT_BAT_OVER_CURR_3_RES, |
451 | BD71815_INT_BAT_OVER_CURR_3_DET, |
452 | /* Temperature INT_STAT_11 */ |
453 | BD71815_INT_TEMP_BAT_LOW_RES, |
454 | BD71815_INT_TEMP_BAT_LOW_DET, |
455 | BD71815_INT_TEMP_BAT_HI_RES, |
456 | BD71815_INT_TEMP_BAT_HI_DET, |
457 | BD71815_INT_TEMP_CHIP_OVER_125_RES, |
458 | BD71815_INT_TEMP_CHIP_OVER_125_DET, |
459 | BD71815_INT_TEMP_CHIP_OVER_VF_RES, |
460 | BD71815_INT_TEMP_CHIP_OVER_VF_DET, |
461 | /* RTC Alarm INT_STAT_12 */ |
462 | BD71815_INT_RTC0, |
463 | BD71815_INT_RTC1, |
464 | BD71815_INT_RTC2, |
465 | }; |
466 | |
467 | #define BD71815_INT_BUCK1_OCP_MASK BIT(0) |
468 | #define BD71815_INT_BUCK2_OCP_MASK BIT(1) |
469 | #define BD71815_INT_BUCK3_OCP_MASK BIT(2) |
470 | #define BD71815_INT_BUCK4_OCP_MASK BIT(3) |
471 | #define BD71815_INT_BUCK5_OCP_MASK BIT(4) |
472 | #define BD71815_INT_LED_OVP_MASK BIT(5) |
473 | #define BD71815_INT_LED_OCP_MASK BIT(6) |
474 | #define BD71815_INT_LED_SCP_MASK BIT(7) |
475 | |
476 | #define BD71815_INT_DCIN_RMV_MASK BIT(1) |
477 | #define BD71815_INT_CLPS_OUT_MASK BIT(2) |
478 | #define BD71815_INT_CLPS_IN_MASK BIT(3) |
479 | #define BD71815_INT_DCIN_OVP_RES_MASK BIT(4) |
480 | #define BD71815_INT_DCIN_OVP_DET_MASK BIT(5) |
481 | |
482 | #define BD71815_INT_DCIN_MON_RES_MASK BIT(0) |
483 | #define BD71815_INT_DCIN_MON_DET_MASK BIT(1) |
484 | #define BD71815_INT_WDOG_MASK BIT(6) |
485 | |
486 | #define BD71815_INT_VSYS_UV_RES_MASK BIT(0) |
487 | #define BD71815_INT_VSYS_UV_DET_MASK BIT(1) |
488 | #define BD71815_INT_VSYS_LOW_RES_MASK BIT(2) |
489 | #define BD71815_INT_VSYS_LOW_DET_MASK BIT(3) |
490 | #define BD71815_INT_VSYS_MON_RES_MASK BIT(6) |
491 | #define BD71815_INT_VSYS_MON_DET_MASK BIT(7) |
492 | |
493 | #define BD71815_INT_CHG_WDG_TEMP_MASK BIT(2) |
494 | #define BD71815_INT_CHG_WDG_TIME_MASK BIT(3) |
495 | #define BD71815_INT_CHG_RECHARGE_RES_MASK BIT(4) |
496 | #define BD71815_INT_CHG_RECHARGE_DET_MASK BIT(5) |
497 | #define BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK BIT(6) |
498 | #define BD71815_INT_CHG_STATE_TRANSITION_MASK BIT(7) |
499 | |
500 | #define BD71815_INT_BAT_TEMP_NORMAL_MASK BIT(0) |
501 | #define BD71815_INT_BAT_TEMP_ERANGE_MASK BIT(1) |
502 | #define BD71815_INT_BAT_REMOVED_MASK BIT(4) |
503 | #define BD71815_INT_BAT_DETECTED_MASK BIT(5) |
504 | #define BD71815_INT_THERM_REMOVED_MASK BIT(6) |
505 | #define BD71815_INT_THERM_DETECTED_MASK BIT(7) |
506 | |
507 | #define BD71815_INT_BAT_DEAD_MASK BIT(1) |
508 | #define BD71815_INT_BAT_SHORTC_RES_MASK BIT(2) |
509 | #define BD71815_INT_BAT_SHORTC_DET_MASK BIT(3) |
510 | #define BD71815_INT_BAT_LOW_VOLT_RES_MASK BIT(4) |
511 | #define BD71815_INT_BAT_LOW_VOLT_DET_MASK BIT(5) |
512 | #define BD71815_INT_BAT_OVER_VOLT_RES_MASK BIT(6) |
513 | #define BD71815_INT_BAT_OVER_VOLT_DET_MASK BIT(7) |
514 | |
515 | #define BD71815_INT_BAT_MON_RES_MASK BIT(0) |
516 | #define BD71815_INT_BAT_MON_DET_MASK BIT(1) |
517 | |
518 | #define BD71815_INT_BAT_CC_MON1_MASK BIT(0) |
519 | #define BD71815_INT_BAT_CC_MON2_MASK BIT(1) |
520 | #define BD71815_INT_BAT_CC_MON3_MASK BIT(2) |
521 | |
522 | #define BD71815_INT_BAT_OVER_CURR_1_RES_MASK BIT(0) |
523 | #define BD71815_INT_BAT_OVER_CURR_1_DET_MASK BIT(1) |
524 | #define BD71815_INT_BAT_OVER_CURR_2_RES_MASK BIT(2) |
525 | #define BD71815_INT_BAT_OVER_CURR_2_DET_MASK BIT(3) |
526 | #define BD71815_INT_BAT_OVER_CURR_3_RES_MASK BIT(4) |
527 | #define BD71815_INT_BAT_OVER_CURR_3_DET_MASK BIT(5) |
528 | |
529 | #define BD71815_INT_TEMP_BAT_LOW_RES_MASK BIT(0) |
530 | #define BD71815_INT_TEMP_BAT_LOW_DET_MASK BIT(1) |
531 | #define BD71815_INT_TEMP_BAT_HI_RES_MASK BIT(2) |
532 | #define BD71815_INT_TEMP_BAT_HI_DET_MASK BIT(3) |
533 | #define BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK BIT(4) |
534 | #define BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK BIT(5) |
535 | #define BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK BIT(6) |
536 | #define BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK BIT(7) |
537 | |
538 | #define BD71815_INT_RTC0_MASK BIT(0) |
539 | #define BD71815_INT_RTC1_MASK BIT(1) |
540 | #define BD71815_INT_RTC2_MASK BIT(2) |
541 | |
542 | /* BD71815_REG_CC_CTRL bits */ |
543 | #define CCNTRST 0x80 |
544 | #define CCNTENB 0x40 |
545 | #define CCCALIB 0x20 |
546 | |
547 | /* BD71815_REG_CC_CURCD */ |
548 | #define CURDIR_Discharging 0x8000 |
549 | |
550 | /* BD71815_REG_VM_SA_IBAT */ |
551 | #define IBAT_SA_DIR_Discharging 0x8000 |
552 | |
553 | /* BD71815_REG_REX_CTRL_1 bits */ |
554 | #define REX_CLR BIT(4) |
555 | |
556 | /* BD71815_REG_REX_CTRL_1 bits */ |
557 | #define REX_PMU_STATE_MASK BIT(2) |
558 | |
559 | /* BD71815_REG_LED_CTRL bits */ |
560 | #define CHGDONE_LED_EN BIT(4) |
561 | |
562 | #endif /* __LINUX_MFD_BD71815_H */ |
563 | |