| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* Copyright (C) 2019 ROHM Semiconductors */ |
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| 3 | |
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| 4 | #ifndef __LINUX_MFD_BD71828_H__ |
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| 5 | #define __LINUX_MFD_BD71828_H__ |
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| 6 | |
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| 7 | #include <linux/mfd/rohm-generic.h> |
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| 8 | #include <linux/mfd/rohm-shared.h> |
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| 9 | |
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| 10 | /* Regulator IDs */ |
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| 11 | enum { |
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| 12 | BD71828_BUCK1, |
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| 13 | BD71828_BUCK2, |
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| 14 | BD71828_BUCK3, |
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| 15 | BD71828_BUCK4, |
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| 16 | BD71828_BUCK5, |
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| 17 | BD71828_BUCK6, |
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| 18 | BD71828_BUCK7, |
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| 19 | BD71828_LDO1, |
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| 20 | BD71828_LDO2, |
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| 21 | BD71828_LDO3, |
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| 22 | BD71828_LDO4, |
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| 23 | BD71828_LDO5, |
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| 24 | BD71828_LDO6, |
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| 25 | BD71828_LDO_SNVS, |
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| 26 | BD71828_REGULATOR_AMOUNT, |
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| 27 | }; |
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| 28 | |
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| 29 | #define BD71828_BUCK1267_VOLTS 0x100 |
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| 30 | #define BD71828_BUCK3_VOLTS 0x20 |
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| 31 | #define BD71828_BUCK4_VOLTS 0x40 |
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| 32 | #define BD71828_BUCK5_VOLTS 0x20 |
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| 33 | #define BD71828_LDO_VOLTS 0x40 |
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| 34 | /* LDO6 is fixed 1.8V voltage */ |
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| 35 | #define BD71828_LDO_6_VOLTAGE 1800000 |
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| 36 | |
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| 37 | /* Registers and masks*/ |
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| 38 | |
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| 39 | /* MODE control */ |
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| 40 | #define BD71828_REG_PS_CTRL_1 0x04 |
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| 41 | #define BD71828_REG_PS_CTRL_2 0x05 |
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| 42 | #define BD71828_REG_PS_CTRL_3 0x06 |
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| 43 | |
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| 44 | //#define BD71828_REG_SWRESET 0x06 |
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| 45 | #define BD71828_MASK_RUN_LVL_CTRL 0x30 |
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| 46 | |
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| 47 | /* Regulator control masks */ |
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| 48 | |
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| 49 | #define BD71828_MASK_RAMP_DELAY 0x6 |
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| 50 | |
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| 51 | #define BD71828_MASK_RUN_EN 0x08 |
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| 52 | #define BD71828_MASK_SUSP_EN 0x04 |
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| 53 | #define BD71828_MASK_IDLE_EN 0x02 |
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| 54 | #define BD71828_MASK_LPSR_EN 0x01 |
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| 55 | |
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| 56 | #define BD71828_MASK_RUN0_EN 0x01 |
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| 57 | #define BD71828_MASK_RUN1_EN 0x02 |
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| 58 | #define BD71828_MASK_RUN2_EN 0x04 |
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| 59 | #define BD71828_MASK_RUN3_EN 0x08 |
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| 60 | |
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| 61 | #define BD71828_MASK_DVS_BUCK1_CTRL 0x10 |
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| 62 | #define BD71828_DVS_BUCK1_CTRL_I2C 0 |
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| 63 | #define BD71828_DVS_BUCK1_USE_RUNLVL 0x10 |
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| 64 | |
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| 65 | #define BD71828_MASK_DVS_BUCK2_CTRL 0x20 |
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| 66 | #define BD71828_DVS_BUCK2_CTRL_I2C 0 |
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| 67 | #define BD71828_DVS_BUCK2_USE_RUNLVL 0x20 |
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| 68 | |
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| 69 | #define BD71828_MASK_DVS_BUCK6_CTRL 0x40 |
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| 70 | #define BD71828_DVS_BUCK6_CTRL_I2C 0 |
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| 71 | #define BD71828_DVS_BUCK6_USE_RUNLVL 0x40 |
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| 72 | |
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| 73 | #define BD71828_MASK_DVS_BUCK7_CTRL 0x80 |
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| 74 | #define BD71828_DVS_BUCK7_CTRL_I2C 0 |
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| 75 | #define BD71828_DVS_BUCK7_USE_RUNLVL 0x80 |
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| 76 | |
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| 77 | #define BD71828_MASK_BUCK1267_VOLT 0xff |
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| 78 | #define BD71828_MASK_BUCK3_VOLT 0x1f |
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| 79 | #define BD71828_MASK_BUCK4_VOLT 0x3f |
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| 80 | #define BD71828_MASK_BUCK5_VOLT 0x1f |
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| 81 | #define BD71828_MASK_LDO_VOLT 0x3f |
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| 82 | |
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| 83 | /* Regulator control regs */ |
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| 84 | #define BD71828_REG_BUCK1_EN 0x08 |
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| 85 | #define BD71828_REG_BUCK1_CTRL 0x09 |
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| 86 | #define BD71828_REG_BUCK1_MODE 0x0a |
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| 87 | #define BD71828_REG_BUCK1_IDLE_VOLT 0x0b |
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| 88 | #define BD71828_REG_BUCK1_SUSP_VOLT 0x0c |
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| 89 | #define BD71828_REG_BUCK1_VOLT 0x0d |
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| 90 | |
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| 91 | #define BD71828_REG_BUCK2_EN 0x12 |
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| 92 | #define BD71828_REG_BUCK2_CTRL 0x13 |
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| 93 | #define BD71828_REG_BUCK2_MODE 0x14 |
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| 94 | #define BD71828_REG_BUCK2_IDLE_VOLT 0x15 |
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| 95 | #define BD71828_REG_BUCK2_SUSP_VOLT 0x16 |
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| 96 | #define BD71828_REG_BUCK2_VOLT 0x17 |
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| 97 | |
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| 98 | #define BD71828_REG_BUCK3_EN 0x1c |
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| 99 | #define BD71828_REG_BUCK3_MODE 0x1d |
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| 100 | #define BD71828_REG_BUCK3_VOLT 0x1e |
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| 101 | |
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| 102 | #define BD71828_REG_BUCK4_EN 0x1f |
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| 103 | #define BD71828_REG_BUCK4_MODE 0x20 |
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| 104 | #define BD71828_REG_BUCK4_VOLT 0x21 |
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| 105 | |
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| 106 | #define BD71828_REG_BUCK5_EN 0x22 |
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| 107 | #define BD71828_REG_BUCK5_MODE 0x23 |
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| 108 | #define BD71828_REG_BUCK5_VOLT 0x24 |
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| 109 | |
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| 110 | #define BD71828_REG_BUCK6_EN 0x25 |
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| 111 | #define BD71828_REG_BUCK6_CTRL 0x26 |
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| 112 | #define BD71828_REG_BUCK6_MODE 0x27 |
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| 113 | #define BD71828_REG_BUCK6_IDLE_VOLT 0x28 |
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| 114 | #define BD71828_REG_BUCK6_SUSP_VOLT 0x29 |
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| 115 | #define BD71828_REG_BUCK6_VOLT 0x2a |
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| 116 | |
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| 117 | #define BD71828_REG_BUCK7_EN 0x2f |
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| 118 | #define BD71828_REG_BUCK7_CTRL 0x30 |
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| 119 | #define BD71828_REG_BUCK7_MODE 0x31 |
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| 120 | #define BD71828_REG_BUCK7_IDLE_VOLT 0x32 |
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| 121 | #define BD71828_REG_BUCK7_SUSP_VOLT 0x33 |
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| 122 | #define BD71828_REG_BUCK7_VOLT 0x34 |
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| 123 | |
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| 124 | #define BD71828_REG_LDO1_EN 0x39 |
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| 125 | #define BD71828_REG_LDO1_VOLT 0x3a |
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| 126 | #define BD71828_REG_LDO2_EN 0x3b |
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| 127 | #define BD71828_REG_LDO2_VOLT 0x3c |
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| 128 | #define BD71828_REG_LDO3_EN 0x3d |
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| 129 | #define BD71828_REG_LDO3_VOLT 0x3e |
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| 130 | #define BD71828_REG_LDO4_EN 0x3f |
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| 131 | #define BD71828_REG_LDO4_VOLT 0x40 |
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| 132 | #define BD71828_REG_LDO5_EN 0x41 |
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| 133 | #define BD71828_REG_LDO5_VOLT 0x43 |
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| 134 | #define BD71828_REG_LDO5_VOLT_OPT 0x42 |
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| 135 | #define BD71828_REG_LDO6_EN 0x44 |
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| 136 | //#define BD71828_REG_LDO6_VOLT 0x4 |
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| 137 | #define BD71828_REG_LDO7_EN 0x45 |
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| 138 | #define BD71828_REG_LDO7_VOLT 0x46 |
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| 139 | |
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| 140 | /* GPIO */ |
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| 141 | |
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| 142 | #define BD71828_GPIO_DRIVE_MASK 0x2 |
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| 143 | #define BD71828_GPIO_OPEN_DRAIN 0x0 |
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| 144 | #define BD71828_GPIO_PUSH_PULL 0x2 |
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| 145 | #define BD71828_GPIO_OUT_HI 0x1 |
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| 146 | #define BD71828_GPIO_OUT_LO 0x0 |
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| 147 | #define BD71828_GPIO_OUT_MASK 0x1 |
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| 148 | |
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| 149 | #define BD71828_REG_GPIO_CTRL1 0x47 |
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| 150 | #define BD71828_REG_GPIO_CTRL2 0x48 |
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| 151 | #define BD71828_REG_GPIO_CTRL3 0x49 |
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| 152 | #define BD71828_REG_IO_STAT 0xed |
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| 153 | |
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| 154 | /* clk */ |
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| 155 | #define BD71828_REG_OUT32K 0x4b |
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| 156 | |
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| 157 | /* RTC */ |
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| 158 | #define BD71828_REG_RTC_SEC 0x4c |
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| 159 | #define BD71828_REG_RTC_MINUTE 0x4d |
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| 160 | #define BD71828_REG_RTC_HOUR 0x4e |
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| 161 | #define BD71828_REG_RTC_WEEK 0x4f |
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| 162 | #define BD71828_REG_RTC_DAY 0x50 |
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| 163 | #define BD71828_REG_RTC_MONTH 0x51 |
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| 164 | #define BD71828_REG_RTC_YEAR 0x52 |
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| 165 | |
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| 166 | #define BD71828_REG_RTC_ALM0_SEC 0x53 |
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| 167 | #define BD71828_REG_RTC_ALM_START BD71828_REG_RTC_ALM0_SEC |
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| 168 | #define BD71828_REG_RTC_ALM0_MINUTE 0x54 |
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| 169 | #define BD71828_REG_RTC_ALM0_HOUR 0x55 |
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| 170 | #define BD71828_REG_RTC_ALM0_WEEK 0x56 |
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| 171 | #define BD71828_REG_RTC_ALM0_DAY 0x57 |
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| 172 | #define BD71828_REG_RTC_ALM0_MONTH 0x58 |
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| 173 | #define BD71828_REG_RTC_ALM0_YEAR 0x59 |
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| 174 | #define BD71828_REG_RTC_ALM0_MASK 0x61 |
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| 175 | |
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| 176 | #define BD71828_REG_RTC_ALM1_SEC 0x5a |
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| 177 | #define BD71828_REG_RTC_ALM1_MINUTE 0x5b |
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| 178 | #define BD71828_REG_RTC_ALM1_HOUR 0x5c |
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| 179 | #define BD71828_REG_RTC_ALM1_WEEK 0x5d |
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| 180 | #define BD71828_REG_RTC_ALM1_DAY 0x5e |
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| 181 | #define BD71828_REG_RTC_ALM1_MONTH 0x5f |
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| 182 | #define BD71828_REG_RTC_ALM1_YEAR 0x60 |
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| 183 | #define BD71828_REG_RTC_ALM1_MASK 0x62 |
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| 184 | |
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| 185 | #define BD71828_REG_RTC_ALM2 0x63 |
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| 186 | #define BD71828_REG_RTC_START BD71828_REG_RTC_SEC |
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| 187 | |
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| 188 | /* Charger/Battey */ |
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| 189 | #define BD71828_REG_CHG_STATE 0x65 |
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| 190 | #define BD71828_REG_CHG_FULL 0xd2 |
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| 191 | |
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| 192 | /* LEDs */ |
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| 193 | #define BD71828_REG_LED_CTRL 0x4A |
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| 194 | #define BD71828_MASK_LED_AMBER 0x80 |
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| 195 | #define BD71828_MASK_LED_GREEN 0x40 |
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| 196 | #define BD71828_LED_ON 0xff |
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| 197 | #define BD71828_LED_OFF 0x0 |
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| 198 | |
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| 199 | /* IRQ registers */ |
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| 200 | #define BD71828_REG_INT_MASK_BUCK 0xd3 |
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| 201 | #define BD71828_REG_INT_MASK_DCIN1 0xd4 |
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| 202 | #define BD71828_REG_INT_MASK_DCIN2 0xd5 |
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| 203 | #define BD71828_REG_INT_MASK_VSYS 0xd6 |
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| 204 | #define BD71828_REG_INT_MASK_CHG 0xd7 |
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| 205 | #define BD71828_REG_INT_MASK_BAT 0xd8 |
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| 206 | #define BD71828_REG_INT_MASK_BAT_MON1 0xd9 |
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| 207 | #define BD71828_REG_INT_MASK_BAT_MON2 0xda |
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| 208 | #define BD71828_REG_INT_MASK_BAT_MON3 0xdb |
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| 209 | #define BD71828_REG_INT_MASK_BAT_MON4 0xdc |
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| 210 | #define BD71828_REG_INT_MASK_TEMP 0xdd |
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| 211 | #define BD71828_REG_INT_MASK_RTC 0xde |
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| 212 | |
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| 213 | #define BD71828_REG_INT_MAIN 0xdf |
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| 214 | #define BD71828_REG_INT_BUCK 0xe0 |
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| 215 | #define BD71828_REG_INT_DCIN1 0xe1 |
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| 216 | #define BD71828_REG_INT_DCIN2 0xe2 |
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| 217 | #define BD71828_REG_INT_VSYS 0xe3 |
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| 218 | #define BD71828_REG_INT_CHG 0xe4 |
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| 219 | #define BD71828_REG_INT_BAT 0xe5 |
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| 220 | #define BD71828_REG_INT_BAT_MON1 0xe6 |
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| 221 | #define BD71828_REG_INT_BAT_MON2 0xe7 |
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| 222 | #define BD71828_REG_INT_BAT_MON3 0xe8 |
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| 223 | #define BD71828_REG_INT_BAT_MON4 0xe9 |
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| 224 | #define BD71828_REG_INT_TEMP 0xea |
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| 225 | #define BD71828_REG_INT_RTC 0xeb |
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| 226 | #define BD71828_REG_INT_UPDATE 0xec |
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| 227 | |
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| 228 | #define BD71828_MAX_REGISTER BD71828_REG_IO_STAT |
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| 229 | |
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| 230 | /* Masks for main IRQ register bits */ |
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| 231 | enum { |
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| 232 | BD71828_INT_BUCK, |
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| 233 | #define BD71828_INT_BUCK_MASK BIT(BD71828_INT_BUCK) |
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| 234 | BD71828_INT_DCIN, |
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| 235 | #define BD71828_INT_DCIN_MASK BIT(BD71828_INT_DCIN) |
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| 236 | BD71828_INT_VSYS, |
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| 237 | #define BD71828_INT_VSYS_MASK BIT(BD71828_INT_VSYS) |
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| 238 | BD71828_INT_CHG, |
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| 239 | #define BD71828_INT_CHG_MASK BIT(BD71828_INT_CHG) |
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| 240 | BD71828_INT_BAT, |
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| 241 | #define BD71828_INT_BAT_MASK BIT(BD71828_INT_BAT) |
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| 242 | BD71828_INT_BAT_MON, |
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| 243 | #define BD71828_INT_BAT_MON_MASK BIT(BD71828_INT_BAT_MON) |
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| 244 | BD71828_INT_TEMP, |
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| 245 | #define BD71828_INT_TEMP_MASK BIT(BD71828_INT_TEMP) |
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| 246 | BD71828_INT_RTC, |
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| 247 | #define BD71828_INT_RTC_MASK BIT(BD71828_INT_RTC) |
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| 248 | }; |
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| 249 | |
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| 250 | /* Interrupts */ |
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| 251 | enum { |
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| 252 | /* BUCK reg interrupts */ |
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| 253 | BD71828_INT_BUCK1_OCP, |
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| 254 | BD71828_INT_BUCK2_OCP, |
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| 255 | BD71828_INT_BUCK3_OCP, |
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| 256 | BD71828_INT_BUCK4_OCP, |
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| 257 | BD71828_INT_BUCK5_OCP, |
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| 258 | BD71828_INT_BUCK6_OCP, |
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| 259 | BD71828_INT_BUCK7_OCP, |
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| 260 | BD71828_INT_PGFAULT, |
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| 261 | /* DCIN1 interrupts */ |
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| 262 | BD71828_INT_DCIN_DET, |
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| 263 | BD71828_INT_DCIN_RMV, |
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| 264 | BD71828_INT_CLPS_OUT, |
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| 265 | BD71828_INT_CLPS_IN, |
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| 266 | /* DCIN2 interrupts */ |
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| 267 | BD71828_INT_DCIN_MON_RES, |
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| 268 | BD71828_INT_DCIN_MON_DET, |
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| 269 | BD71828_INT_LONGPUSH, |
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| 270 | BD71828_INT_MIDPUSH, |
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| 271 | BD71828_INT_SHORTPUSH, |
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| 272 | BD71828_INT_PUSH, |
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| 273 | BD71828_INT_WDOG, |
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| 274 | BD71828_INT_SWRESET, |
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| 275 | /* Vsys */ |
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| 276 | BD71828_INT_VSYS_UV_RES, |
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| 277 | BD71828_INT_VSYS_UV_DET, |
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| 278 | BD71828_INT_VSYS_LOW_RES, |
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| 279 | BD71828_INT_VSYS_LOW_DET, |
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| 280 | BD71828_INT_VSYS_HALL_IN, |
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| 281 | BD71828_INT_VSYS_HALL_TOGGLE, |
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| 282 | BD71828_INT_VSYS_MON_RES, |
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| 283 | BD71828_INT_VSYS_MON_DET, |
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| 284 | /* Charger */ |
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| 285 | BD71828_INT_CHG_DCIN_ILIM, |
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| 286 | BD71828_INT_CHG_TOPOFF_TO_DONE, |
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| 287 | BD71828_INT_CHG_WDG_TEMP, |
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| 288 | BD71828_INT_CHG_WDG_TIME, |
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| 289 | BD71828_INT_CHG_RECHARGE_RES, |
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| 290 | BD71828_INT_CHG_RECHARGE_DET, |
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| 291 | BD71828_INT_CHG_RANGED_TEMP_TRANSITION, |
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| 292 | BD71828_INT_CHG_STATE_TRANSITION, |
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| 293 | /* Battery */ |
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| 294 | BD71828_INT_BAT_TEMP_NORMAL, |
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| 295 | BD71828_INT_BAT_TEMP_ERANGE, |
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| 296 | BD71828_INT_BAT_TEMP_WARN, |
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| 297 | BD71828_INT_BAT_REMOVED, |
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| 298 | BD71828_INT_BAT_DETECTED, |
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| 299 | BD71828_INT_THERM_REMOVED, |
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| 300 | BD71828_INT_THERM_DETECTED, |
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| 301 | /* Battery Mon 1 */ |
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| 302 | BD71828_INT_BAT_DEAD, |
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| 303 | BD71828_INT_BAT_SHORTC_RES, |
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| 304 | BD71828_INT_BAT_SHORTC_DET, |
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| 305 | BD71828_INT_BAT_LOW_VOLT_RES, |
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| 306 | BD71828_INT_BAT_LOW_VOLT_DET, |
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| 307 | BD71828_INT_BAT_OVER_VOLT_RES, |
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| 308 | BD71828_INT_BAT_OVER_VOLT_DET, |
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| 309 | /* Battery Mon 2 */ |
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| 310 | BD71828_INT_BAT_MON_RES, |
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| 311 | BD71828_INT_BAT_MON_DET, |
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| 312 | /* Battery Mon 3 (Coulomb counter) */ |
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| 313 | BD71828_INT_BAT_CC_MON1, |
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| 314 | BD71828_INT_BAT_CC_MON2, |
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| 315 | BD71828_INT_BAT_CC_MON3, |
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| 316 | /* Battery Mon 4 */ |
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| 317 | BD71828_INT_BAT_OVER_CURR_1_RES, |
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| 318 | BD71828_INT_BAT_OVER_CURR_1_DET, |
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| 319 | BD71828_INT_BAT_OVER_CURR_2_RES, |
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| 320 | BD71828_INT_BAT_OVER_CURR_2_DET, |
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| 321 | BD71828_INT_BAT_OVER_CURR_3_RES, |
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| 322 | BD71828_INT_BAT_OVER_CURR_3_DET, |
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| 323 | /* Temperature */ |
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| 324 | BD71828_INT_TEMP_BAT_LOW_RES, |
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| 325 | BD71828_INT_TEMP_BAT_LOW_DET, |
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| 326 | BD71828_INT_TEMP_BAT_HI_RES, |
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| 327 | BD71828_INT_TEMP_BAT_HI_DET, |
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| 328 | BD71828_INT_TEMP_CHIP_OVER_125_RES, |
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| 329 | BD71828_INT_TEMP_CHIP_OVER_125_DET, |
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| 330 | BD71828_INT_TEMP_CHIP_OVER_VF_DET, |
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| 331 | BD71828_INT_TEMP_CHIP_OVER_VF_RES, |
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| 332 | /* RTC Alarm */ |
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| 333 | BD71828_INT_RTC0, |
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| 334 | BD71828_INT_RTC1, |
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| 335 | BD71828_INT_RTC2, |
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| 336 | }; |
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| 337 | |
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| 338 | #define BD71828_INT_BUCK1_OCP_MASK 0x1 |
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| 339 | #define BD71828_INT_BUCK2_OCP_MASK 0x2 |
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| 340 | #define BD71828_INT_BUCK3_OCP_MASK 0x4 |
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| 341 | #define BD71828_INT_BUCK4_OCP_MASK 0x8 |
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| 342 | #define BD71828_INT_BUCK5_OCP_MASK 0x10 |
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| 343 | #define BD71828_INT_BUCK6_OCP_MASK 0x20 |
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| 344 | #define BD71828_INT_BUCK7_OCP_MASK 0x40 |
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| 345 | #define BD71828_INT_PGFAULT_MASK 0x80 |
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| 346 | |
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| 347 | #define BD71828_INT_DCIN_DET_MASK 0x1 |
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| 348 | #define BD71828_INT_DCIN_RMV_MASK 0x2 |
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| 349 | #define BD71828_INT_CLPS_OUT_MASK 0x4 |
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| 350 | #define BD71828_INT_CLPS_IN_MASK 0x8 |
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| 351 | /* DCIN2 interrupts */ |
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| 352 | #define BD71828_INT_DCIN_MON_RES_MASK 0x1 |
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| 353 | #define BD71828_INT_DCIN_MON_DET_MASK 0x2 |
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| 354 | #define BD71828_INT_LONGPUSH_MASK 0x4 |
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| 355 | #define BD71828_INT_MIDPUSH_MASK 0x8 |
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| 356 | #define BD71828_INT_SHORTPUSH_MASK 0x10 |
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| 357 | #define BD71828_INT_PUSH_MASK 0x20 |
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| 358 | #define BD71828_INT_WDOG_MASK 0x40 |
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| 359 | #define BD71828_INT_SWRESET_MASK 0x80 |
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| 360 | /* Vsys */ |
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| 361 | #define BD71828_INT_VSYS_UV_RES_MASK 0x1 |
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| 362 | #define BD71828_INT_VSYS_UV_DET_MASK 0x2 |
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| 363 | #define BD71828_INT_VSYS_LOW_RES_MASK 0x4 |
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| 364 | #define BD71828_INT_VSYS_LOW_DET_MASK 0x8 |
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| 365 | #define BD71828_INT_VSYS_HALL_IN_MASK 0x10 |
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| 366 | #define BD71828_INT_VSYS_HALL_TOGGLE_MASK 0x20 |
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| 367 | #define BD71828_INT_VSYS_MON_RES_MASK 0x40 |
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| 368 | #define BD71828_INT_VSYS_MON_DET_MASK 0x80 |
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| 369 | /* Charger */ |
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| 370 | #define BD71828_INT_CHG_DCIN_ILIM_MASK 0x1 |
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| 371 | #define BD71828_INT_CHG_TOPOFF_TO_DONE_MASK 0x2 |
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| 372 | #define BD71828_INT_CHG_WDG_TEMP_MASK 0x4 |
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| 373 | #define BD71828_INT_CHG_WDG_TIME_MASK 0x8 |
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| 374 | #define BD71828_INT_CHG_RECHARGE_RES_MASK 0x10 |
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| 375 | #define BD71828_INT_CHG_RECHARGE_DET_MASK 0x20 |
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| 376 | #define BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK 0x40 |
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| 377 | #define BD71828_INT_CHG_STATE_TRANSITION_MASK 0x80 |
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| 378 | /* Battery */ |
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| 379 | #define BD71828_INT_BAT_TEMP_NORMAL_MASK 0x1 |
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| 380 | #define BD71828_INT_BAT_TEMP_ERANGE_MASK 0x2 |
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| 381 | #define BD71828_INT_BAT_TEMP_WARN_MASK 0x4 |
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| 382 | #define BD71828_INT_BAT_REMOVED_MASK 0x10 |
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| 383 | #define BD71828_INT_BAT_DETECTED_MASK 0x20 |
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| 384 | #define BD71828_INT_THERM_REMOVED_MASK 0x40 |
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| 385 | #define BD71828_INT_THERM_DETECTED_MASK 0x80 |
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| 386 | /* Battery Mon 1 */ |
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| 387 | #define BD71828_INT_BAT_DEAD_MASK 0x2 |
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| 388 | #define BD71828_INT_BAT_SHORTC_RES_MASK 0x4 |
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| 389 | #define BD71828_INT_BAT_SHORTC_DET_MASK 0x8 |
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| 390 | #define BD71828_INT_BAT_LOW_VOLT_RES_MASK 0x10 |
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| 391 | #define BD71828_INT_BAT_LOW_VOLT_DET_MASK 0x20 |
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| 392 | #define BD71828_INT_BAT_OVER_VOLT_RES_MASK 0x40 |
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| 393 | #define BD71828_INT_BAT_OVER_VOLT_DET_MASK 0x80 |
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| 394 | /* Battery Mon 2 */ |
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| 395 | #define BD71828_INT_BAT_MON_RES_MASK 0x1 |
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| 396 | #define BD71828_INT_BAT_MON_DET_MASK 0x2 |
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| 397 | /* Battery Mon 3 (Coulomb counter) */ |
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| 398 | #define BD71828_INT_BAT_CC_MON1_MASK 0x1 |
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| 399 | #define BD71828_INT_BAT_CC_MON2_MASK 0x2 |
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| 400 | #define BD71828_INT_BAT_CC_MON3_MASK 0x4 |
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| 401 | /* Battery Mon 4 */ |
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| 402 | #define BD71828_INT_BAT_OVER_CURR_1_RES_MASK 0x1 |
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| 403 | #define BD71828_INT_BAT_OVER_CURR_1_DET_MASK 0x2 |
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| 404 | #define BD71828_INT_BAT_OVER_CURR_2_RES_MASK 0x4 |
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| 405 | #define BD71828_INT_BAT_OVER_CURR_2_DET_MASK 0x8 |
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| 406 | #define BD71828_INT_BAT_OVER_CURR_3_RES_MASK 0x10 |
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| 407 | #define BD71828_INT_BAT_OVER_CURR_3_DET_MASK 0x20 |
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| 408 | /* Temperature */ |
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| 409 | #define BD71828_INT_TEMP_BAT_LOW_RES_MASK 0x1 |
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| 410 | #define BD71828_INT_TEMP_BAT_LOW_DET_MASK 0x2 |
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| 411 | #define BD71828_INT_TEMP_BAT_HI_RES_MASK 0x4 |
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| 412 | #define BD71828_INT_TEMP_BAT_HI_DET_MASK 0x8 |
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| 413 | #define BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK 0x10 |
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| 414 | #define BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK 0x20 |
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| 415 | #define BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK 0x40 |
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| 416 | #define BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK 0x80 |
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| 417 | /* RTC Alarm */ |
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| 418 | #define BD71828_INT_RTC0_MASK 0x1 |
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| 419 | #define BD71828_INT_RTC1_MASK 0x2 |
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| 420 | #define BD71828_INT_RTC2_MASK 0x4 |
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| 421 | |
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| 422 | #define BD71828_OUT_TYPE_MASK 0x2 |
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| 423 | #define BD71828_OUT_TYPE_OPEN_DRAIN 0x0 |
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| 424 | #define BD71828_OUT_TYPE_CMOS 0x2 |
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| 425 | |
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| 426 | #endif /* __LINUX_MFD_BD71828_H__ */ |
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| 427 | |
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