1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Functions to access TPS65219 Power Management IC. |
4 | * |
5 | * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ |
6 | */ |
7 | |
8 | #ifndef MFD_TPS65219_H |
9 | #define MFD_TPS65219_H |
10 | |
11 | #include <linux/bitops.h> |
12 | #include <linux/notifier.h> |
13 | #include <linux/regulator/driver.h> |
14 | |
15 | struct regmap; |
16 | struct regmap_irq_chip_data; |
17 | |
18 | #define TPS65219_1V35 1350000 |
19 | #define TPS65219_1V8 1800000 |
20 | |
21 | /* TPS chip id list */ |
22 | #define TPS65219 0xF0 |
23 | |
24 | /* I2C ID for TPS65219 part */ |
25 | #define TPS65219_I2C_ID 0x24 |
26 | |
27 | /* All register addresses */ |
28 | #define TPS65219_REG_TI_DEV_ID 0x00 |
29 | #define TPS65219_REG_NVM_ID 0x01 |
30 | #define TPS65219_REG_ENABLE_CTRL 0x02 |
31 | #define TPS65219_REG_BUCKS_CONFIG 0x03 |
32 | #define TPS65219_REG_LDO4_VOUT 0x04 |
33 | #define TPS65219_REG_LDO3_VOUT 0x05 |
34 | #define TPS65219_REG_LDO2_VOUT 0x06 |
35 | #define TPS65219_REG_LDO1_VOUT 0x07 |
36 | #define TPS65219_REG_BUCK3_VOUT 0x8 |
37 | #define TPS65219_REG_BUCK2_VOUT 0x9 |
38 | #define TPS65219_REG_BUCK1_VOUT 0xA |
39 | #define TPS65219_REG_LDO4_SEQUENCE_SLOT 0xB |
40 | #define TPS65219_REG_LDO3_SEQUENCE_SLOT 0xC |
41 | #define TPS65219_REG_LDO2_SEQUENCE_SLOT 0xD |
42 | #define TPS65219_REG_LDO1_SEQUENCE_SLOT 0xE |
43 | #define TPS65219_REG_BUCK3_SEQUENCE_SLOT 0xF |
44 | #define TPS65219_REG_BUCK2_SEQUENCE_SLOT 0x10 |
45 | #define TPS65219_REG_BUCK1_SEQUENCE_SLOT 0x11 |
46 | #define TPS65219_REG_nRST_SEQUENCE_SLOT 0x12 |
47 | #define TPS65219_REG_GPIO_SEQUENCE_SLOT 0x13 |
48 | #define TPS65219_REG_GPO2_SEQUENCE_SLOT 0x14 |
49 | #define TPS65219_REG_GPO1_SEQUENCE_SLOT 0x15 |
50 | #define TPS65219_REG_POWER_UP_SLOT_DURATION_1 0x16 |
51 | #define TPS65219_REG_POWER_UP_SLOT_DURATION_2 0x17 |
52 | #define TPS65219_REG_POWER_UP_SLOT_DURATION_3 0x18 |
53 | #define TPS65219_REG_POWER_UP_SLOT_DURATION_4 0x19 |
54 | #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_1 0x1A |
55 | #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_2 0x1B |
56 | #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_3 0x1C |
57 | #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_4 0x1D |
58 | #define TPS65219_REG_GENERAL_CONFIG 0x1E |
59 | #define TPS65219_REG_MFP_1_CONFIG 0x1F |
60 | #define TPS65219_REG_MFP_2_CONFIG 0x20 |
61 | #define TPS65219_REG_STBY_1_CONFIG 0x21 |
62 | #define TPS65219_REG_STBY_2_CONFIG 0x22 |
63 | #define TPS65219_REG_OC_DEGL_CONFIG 0x23 |
64 | /* 'sub irq' MASK registers */ |
65 | #define TPS65219_REG_INT_MASK_UV 0x24 |
66 | #define TPS65219_REG_MASK_CONFIG 0x25 |
67 | |
68 | #define TPS65219_REG_I2C_ADDRESS_REG 0x26 |
69 | #define TPS65219_REG_USER_GENERAL_NVM_STORAGE 0x27 |
70 | #define TPS65219_REG_MANUFACTURING_VER 0x28 |
71 | #define TPS65219_REG_MFP_CTRL 0x29 |
72 | #define TPS65219_REG_DISCHARGE_CONFIG 0x2A |
73 | /* main irq registers */ |
74 | #define TPS65219_REG_INT_SOURCE 0x2B |
75 | /* 'sub irq' registers */ |
76 | #define TPS65219_REG_INT_LDO_3_4 0x2C |
77 | #define TPS65219_REG_INT_LDO_1_2 0x2D |
78 | #define TPS65219_REG_INT_BUCK_3 0x2E |
79 | #define TPS65219_REG_INT_BUCK_1_2 0x2F |
80 | #define TPS65219_REG_INT_SYSTEM 0x30 |
81 | #define TPS65219_REG_INT_RV 0x31 |
82 | #define TPS65219_REG_INT_TIMEOUT_RV_SD 0x32 |
83 | #define TPS65219_REG_INT_PB 0x33 |
84 | |
85 | #define TPS65219_REG_INT_LDO_3_4_POS 0 |
86 | #define TPS65219_REG_INT_LDO_1_2_POS 1 |
87 | #define TPS65219_REG_INT_BUCK_3_POS 2 |
88 | #define TPS65219_REG_INT_BUCK_1_2_POS 3 |
89 | #define TPS65219_REG_INT_SYS_POS 4 |
90 | #define TPS65219_REG_INT_RV_POS 5 |
91 | #define TPS65219_REG_INT_TO_RV_POS 6 |
92 | #define TPS65219_REG_INT_PB_POS 7 |
93 | |
94 | #define TPS65219_REG_USER_NVM_CMD 0x34 |
95 | #define TPS65219_REG_POWER_UP_STATUS 0x35 |
96 | #define TPS65219_REG_SPARE_2 0x36 |
97 | #define TPS65219_REG_SPARE_3 0x37 |
98 | #define TPS65219_REG_FACTORY_CONFIG_2 0x41 |
99 | |
100 | /* Register field definitions */ |
101 | #define TPS65219_DEVID_REV_MASK GENMASK(7, 0) |
102 | #define TPS65219_BUCKS_LDOS_VOUT_VSET_MASK GENMASK(5, 0) |
103 | #define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6) |
104 | #define TPS65219_BUCKS_BW_SEL_MASK BIT(7) |
105 | #define LDO_BYP_SHIFT 6 |
106 | #define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT) |
107 | #define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7) |
108 | /* Regulators enable control */ |
109 | #define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0) |
110 | #define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1) |
111 | #define TPS65219_ENABLE_BUCK3_EN_MASK BIT(2) |
112 | #define TPS65219_ENABLE_LDO1_EN_MASK BIT(3) |
113 | #define TPS65219_ENABLE_LDO2_EN_MASK BIT(4) |
114 | #define TPS65219_ENABLE_LDO3_EN_MASK BIT(5) |
115 | #define TPS65219_ENABLE_LDO4_EN_MASK BIT(6) |
116 | /* power ON-OFF sequence slot */ |
117 | #define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0) |
118 | #define TPS65219_BUCKS_LDOS_SEQUENCE_ON_SLOT_MASK GENMASK(7, 4) |
119 | /* TODO: Not needed, same mapping as TPS65219_ENABLE_REGNAME_EN, factorize */ |
120 | #define TPS65219_STBY1_BUCK1_STBY_EN_MASK BIT(0) |
121 | #define TPS65219_STBY1_BUCK2_STBY_EN_MASK BIT(1) |
122 | #define TPS65219_STBY1_BUCK3_STBY_EN_MASK BIT(2) |
123 | #define TPS65219_STBY1_LDO1_STBY_EN_MASK BIT(3) |
124 | #define TPS65219_STBY1_LDO2_STBY_EN_MASK BIT(4) |
125 | #define TPS65219_STBY1_LDO3_STBY_EN_MASK BIT(5) |
126 | #define TPS65219_STBY1_LDO4_STBY_EN_MASK BIT(6) |
127 | /* STBY_2 config */ |
128 | #define TPS65219_STBY2_GPO1_STBY_EN_MASK BIT(0) |
129 | #define TPS65219_STBY2_GPO2_STBY_EN_MASK BIT(1) |
130 | #define TPS65219_STBY2_GPIO_STBY_EN_MASK BIT(2) |
131 | /* MFP Control */ |
132 | #define TPS65219_MFP_I2C_OFF_REQ_MASK BIT(0) |
133 | #define TPS65219_MFP_STBY_I2C_CTRL_MASK BIT(1) |
134 | #define TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK BIT(2) |
135 | #define TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK BIT(3) |
136 | #define TPS65219_MFP_GPIO_STATUS_MASK BIT(4) |
137 | /* MFP_1 Config */ |
138 | #define TPS65219_MFP_1_VSEL_DDR_SEL_MASK BIT(0) |
139 | #define TPS65219_MFP_1_VSEL_SD_POL_MASK BIT(1) |
140 | #define TPS65219_MFP_1_VSEL_RAIL_MASK BIT(2) |
141 | /* MFP_2 Config */ |
142 | #define TPS65219_MFP_2_MODE_STBY_MASK GENMASK(1, 0) |
143 | #define TPS65219_MFP_2_MODE_RESET_MASK BIT(2) |
144 | #define TPS65219_MFP_2_EN_PB_VSENSE_DEGL_MASK BIT(3) |
145 | #define TPS65219_MFP_2_EN_PB_VSENSE_MASK GENMASK(5, 4) |
146 | #define TPS65219_MFP_2_WARM_COLD_RESET_MASK BIT(6) |
147 | #define TPS65219_MFP_2_PU_ON_FSD_MASK BIT(7) |
148 | #define TPS65219_MFP_2_EN 0 |
149 | #define TPS65219_MFP_2_PB BIT(4) |
150 | #define TPS65219_MFP_2_VSENSE BIT(5) |
151 | /* MASK_UV Config */ |
152 | #define TPS65219_REG_MASK_UV_LDO1_UV_MASK BIT(0) |
153 | #define TPS65219_REG_MASK_UV_LDO2_UV_MASK BIT(1) |
154 | #define TPS65219_REG_MASK_UV_LDO3_UV_MASK BIT(2) |
155 | #define TPS65219_REG_MASK_UV_LDO4_UV_MASK BIT(3) |
156 | #define TPS65219_REG_MASK_UV_BUCK1_UV_MASK BIT(4) |
157 | #define TPS65219_REG_MASK_UV_BUCK2_UV_MASK BIT(5) |
158 | #define TPS65219_REG_MASK_UV_BUCK3_UV_MASK BIT(6) |
159 | #define TPS65219_REG_MASK_UV_RETRY_MASK BIT(7) |
160 | /* MASK Config */ |
161 | // SENSOR_N_WARM_MASK already defined in Thermal |
162 | #define TPS65219_REG_MASK_INT_FOR_RV_MASK BIT(4) |
163 | #define TPS65219_REG_MASK_EFFECT_MASK GENMASK(2, 1) |
164 | #define TPS65219_REG_MASK_INT_FOR_PB_MASK BIT(7) |
165 | /* UnderVoltage - Short to GND - OverCurrent*/ |
166 | /* LDO3-4 */ |
167 | #define TPS65219_INT_LDO3_SCG_MASK BIT(0) |
168 | #define TPS65219_INT_LDO3_OC_MASK BIT(1) |
169 | #define TPS65219_INT_LDO3_UV_MASK BIT(2) |
170 | #define TPS65219_INT_LDO4_SCG_MASK BIT(3) |
171 | #define TPS65219_INT_LDO4_OC_MASK BIT(4) |
172 | #define TPS65219_INT_LDO4_UV_MASK BIT(5) |
173 | /* LDO1-2 */ |
174 | #define TPS65219_INT_LDO1_SCG_MASK BIT(0) |
175 | #define TPS65219_INT_LDO1_OC_MASK BIT(1) |
176 | #define TPS65219_INT_LDO1_UV_MASK BIT(2) |
177 | #define TPS65219_INT_LDO2_SCG_MASK BIT(3) |
178 | #define TPS65219_INT_LDO2_OC_MASK BIT(4) |
179 | #define TPS65219_INT_LDO2_UV_MASK BIT(5) |
180 | /* BUCK3 */ |
181 | #define TPS65219_INT_BUCK3_SCG_MASK BIT(0) |
182 | #define TPS65219_INT_BUCK3_OC_MASK BIT(1) |
183 | #define TPS65219_INT_BUCK3_NEG_OC_MASK BIT(2) |
184 | #define TPS65219_INT_BUCK3_UV_MASK BIT(3) |
185 | /* BUCK1-2 */ |
186 | #define TPS65219_INT_BUCK1_SCG_MASK BIT(0) |
187 | #define TPS65219_INT_BUCK1_OC_MASK BIT(1) |
188 | #define TPS65219_INT_BUCK1_NEG_OC_MASK BIT(2) |
189 | #define TPS65219_INT_BUCK1_UV_MASK BIT(3) |
190 | #define TPS65219_INT_BUCK2_SCG_MASK BIT(4) |
191 | #define TPS65219_INT_BUCK2_OC_MASK BIT(5) |
192 | #define TPS65219_INT_BUCK2_NEG_OC_MASK BIT(6) |
193 | #define TPS65219_INT_BUCK2_UV_MASK BIT(7) |
194 | /* Thermal Sensor */ |
195 | #define TPS65219_INT_SENSOR_3_WARM_MASK BIT(0) |
196 | #define TPS65219_INT_SENSOR_2_WARM_MASK BIT(1) |
197 | #define TPS65219_INT_SENSOR_1_WARM_MASK BIT(2) |
198 | #define TPS65219_INT_SENSOR_0_WARM_MASK BIT(3) |
199 | #define TPS65219_INT_SENSOR_3_HOT_MASK BIT(4) |
200 | #define TPS65219_INT_SENSOR_2_HOT_MASK BIT(5) |
201 | #define TPS65219_INT_SENSOR_1_HOT_MASK BIT(6) |
202 | #define TPS65219_INT_SENSOR_0_HOT_MASK BIT(7) |
203 | /* Residual Voltage */ |
204 | #define TPS65219_INT_BUCK1_RV_MASK BIT(0) |
205 | #define TPS65219_INT_BUCK2_RV_MASK BIT(1) |
206 | #define TPS65219_INT_BUCK3_RV_MASK BIT(2) |
207 | #define TPS65219_INT_LDO1_RV_MASK BIT(3) |
208 | #define TPS65219_INT_LDO2_RV_MASK BIT(4) |
209 | #define TPS65219_INT_LDO3_RV_MASK BIT(5) |
210 | #define TPS65219_INT_LDO4_RV_MASK BIT(6) |
211 | /* Residual Voltage ShutDown */ |
212 | #define TPS65219_INT_BUCK1_RV_SD_MASK BIT(0) |
213 | #define TPS65219_INT_BUCK2_RV_SD_MASK BIT(1) |
214 | #define TPS65219_INT_BUCK3_RV_SD_MASK BIT(2) |
215 | #define TPS65219_INT_LDO1_RV_SD_MASK BIT(3) |
216 | #define TPS65219_INT_LDO2_RV_SD_MASK BIT(4) |
217 | #define TPS65219_INT_LDO3_RV_SD_MASK BIT(5) |
218 | #define TPS65219_INT_LDO4_RV_SD_MASK BIT(6) |
219 | #define TPS65219_INT_TIMEOUT_MASK BIT(7) |
220 | /* Power Button */ |
221 | #define TPS65219_INT_PB_FALLING_EDGE_DETECT_MASK BIT(0) |
222 | #define TPS65219_INT_PB_RISING_EDGE_DETECT_MASK BIT(1) |
223 | #define TPS65219_INT_PB_REAL_TIME_STATUS_MASK BIT(2) |
224 | |
225 | #define TPS65219_PB_POS 7 |
226 | #define TPS65219_TO_RV_POS 6 |
227 | #define TPS65219_RV_POS 5 |
228 | #define TPS65219_SYS_POS 4 |
229 | #define TPS65219_BUCK_1_2_POS 3 |
230 | #define TPS65219_BUCK_3_POS 2 |
231 | #define TPS65219_LDO_1_2_POS 1 |
232 | #define TPS65219_LDO_3_4_POS 0 |
233 | |
234 | /* IRQs */ |
235 | enum { |
236 | /* LDO3-4 register IRQs */ |
237 | TPS65219_INT_LDO3_SCG, |
238 | TPS65219_INT_LDO3_OC, |
239 | TPS65219_INT_LDO3_UV, |
240 | TPS65219_INT_LDO4_SCG, |
241 | TPS65219_INT_LDO4_OC, |
242 | TPS65219_INT_LDO4_UV, |
243 | /* LDO1-2 */ |
244 | TPS65219_INT_LDO1_SCG, |
245 | TPS65219_INT_LDO1_OC, |
246 | TPS65219_INT_LDO1_UV, |
247 | TPS65219_INT_LDO2_SCG, |
248 | TPS65219_INT_LDO2_OC, |
249 | TPS65219_INT_LDO2_UV, |
250 | /* BUCK3 */ |
251 | TPS65219_INT_BUCK3_SCG, |
252 | TPS65219_INT_BUCK3_OC, |
253 | TPS65219_INT_BUCK3_NEG_OC, |
254 | TPS65219_INT_BUCK3_UV, |
255 | /* BUCK1-2 */ |
256 | TPS65219_INT_BUCK1_SCG, |
257 | TPS65219_INT_BUCK1_OC, |
258 | TPS65219_INT_BUCK1_NEG_OC, |
259 | TPS65219_INT_BUCK1_UV, |
260 | TPS65219_INT_BUCK2_SCG, |
261 | TPS65219_INT_BUCK2_OC, |
262 | TPS65219_INT_BUCK2_NEG_OC, |
263 | TPS65219_INT_BUCK2_UV, |
264 | /* Thermal Sensor */ |
265 | TPS65219_INT_SENSOR_3_WARM, |
266 | TPS65219_INT_SENSOR_2_WARM, |
267 | TPS65219_INT_SENSOR_1_WARM, |
268 | TPS65219_INT_SENSOR_0_WARM, |
269 | TPS65219_INT_SENSOR_3_HOT, |
270 | TPS65219_INT_SENSOR_2_HOT, |
271 | TPS65219_INT_SENSOR_1_HOT, |
272 | TPS65219_INT_SENSOR_0_HOT, |
273 | /* Residual Voltage */ |
274 | TPS65219_INT_BUCK1_RV, |
275 | TPS65219_INT_BUCK2_RV, |
276 | TPS65219_INT_BUCK3_RV, |
277 | TPS65219_INT_LDO1_RV, |
278 | TPS65219_INT_LDO2_RV, |
279 | TPS65219_INT_LDO3_RV, |
280 | TPS65219_INT_LDO4_RV, |
281 | /* Residual Voltage ShutDown */ |
282 | TPS65219_INT_BUCK1_RV_SD, |
283 | TPS65219_INT_BUCK2_RV_SD, |
284 | TPS65219_INT_BUCK3_RV_SD, |
285 | TPS65219_INT_LDO1_RV_SD, |
286 | TPS65219_INT_LDO2_RV_SD, |
287 | TPS65219_INT_LDO3_RV_SD, |
288 | TPS65219_INT_LDO4_RV_SD, |
289 | TPS65219_INT_TIMEOUT, |
290 | /* Power Button */ |
291 | TPS65219_INT_PB_FALLING_EDGE_DETECT, |
292 | TPS65219_INT_PB_RISING_EDGE_DETECT, |
293 | }; |
294 | |
295 | enum tps65219_regulator_id { |
296 | /* DCDC's */ |
297 | TPS65219_BUCK_1, |
298 | TPS65219_BUCK_2, |
299 | TPS65219_BUCK_3, |
300 | /* LDOs */ |
301 | TPS65219_LDO_1, |
302 | TPS65219_LDO_2, |
303 | TPS65219_LDO_3, |
304 | TPS65219_LDO_4, |
305 | }; |
306 | |
307 | /* Number of step-down converters available */ |
308 | #define TPS65219_NUM_DCDC 3 |
309 | /* Number of LDO voltage regulators available */ |
310 | #define TPS65219_NUM_LDO 4 |
311 | /* Number of total regulators available */ |
312 | #define TPS65219_NUM_REGULATOR (TPS65219_NUM_DCDC + TPS65219_NUM_LDO) |
313 | |
314 | /* Define the TPS65219 IRQ numbers */ |
315 | enum tps65219_irqs { |
316 | /* INT source registers */ |
317 | TPS65219_TO_RV_SD_SET_IRQ, |
318 | TPS65219_RV_SET_IRQ, |
319 | TPS65219_SYS_SET_IRQ, |
320 | TPS65219_BUCK_1_2_SET_IRQ, |
321 | TPS65219_BUCK_3_SET_IRQ, |
322 | TPS65219_LDO_1_2_SET_IRQ, |
323 | TPS65219_LDO_3_4_SET_IRQ, |
324 | TPS65219_PB_SET_IRQ, |
325 | }; |
326 | |
327 | /** |
328 | * struct tps65219 - tps65219 sub-driver chip access routines |
329 | * |
330 | * Device data may be used to access the TPS65219 chip |
331 | * |
332 | * @dev: MFD device |
333 | * @regmap: Regmap for accessing the device registers |
334 | * @irq_data: Regmap irq data used for the irq chip |
335 | * @nb: notifier block for the restart handler |
336 | */ |
337 | struct tps65219 { |
338 | struct device *dev; |
339 | struct regmap *regmap; |
340 | |
341 | struct regmap_irq_chip_data *irq_data; |
342 | struct notifier_block nb; |
343 | }; |
344 | |
345 | #endif /* MFD_TPS65219_H */ |
346 | |