1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Functions to access TPS6594 Power Management IC
4 *
5 * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
6 */
7
8#ifndef __LINUX_MFD_TPS6594_H
9#define __LINUX_MFD_TPS6594_H
10
11#include <linux/device.h>
12#include <linux/regmap.h>
13
14struct regmap_irq_chip_data;
15
16/* Chip id list */
17enum pmic_id {
18 TPS6594,
19 TPS6593,
20 LP8764,
21};
22
23/* Macro to get page index from register address */
24#define TPS6594_REG_TO_PAGE(reg) ((reg) >> 8)
25
26/* Registers for page 0 of TPS6594 */
27#define TPS6594_REG_DEV_REV 0x01
28
29#define TPS6594_REG_NVM_CODE_1 0x02
30#define TPS6594_REG_NVM_CODE_2 0x03
31
32#define TPS6594_REG_BUCKX_CTRL(buck_inst) (0x04 + ((buck_inst) << 1))
33#define TPS6594_REG_BUCKX_CONF(buck_inst) (0x05 + ((buck_inst) << 1))
34#define TPS6594_REG_BUCKX_VOUT_1(buck_inst) (0x0e + ((buck_inst) << 1))
35#define TPS6594_REG_BUCKX_VOUT_2(buck_inst) (0x0f + ((buck_inst) << 1))
36#define TPS6594_REG_BUCKX_PG_WINDOW(buck_inst) (0x18 + (buck_inst))
37
38#define TPS6594_REG_LDOX_CTRL(ldo_inst) (0x1d + (ldo_inst))
39#define TPS6594_REG_LDORTC_CTRL 0x22
40#define TPS6594_REG_LDOX_VOUT(ldo_inst) (0x23 + (ldo_inst))
41#define TPS6594_REG_LDOX_PG_WINDOW(ldo_inst) (0x27 + (ldo_inst))
42
43#define TPS6594_REG_VCCA_VMON_CTRL 0x2b
44#define TPS6594_REG_VCCA_PG_WINDOW 0x2c
45#define TPS6594_REG_VMON1_PG_WINDOW 0x2d
46#define TPS6594_REG_VMON1_PG_LEVEL 0x2e
47#define TPS6594_REG_VMON2_PG_WINDOW 0x2f
48#define TPS6594_REG_VMON2_PG_LEVEL 0x30
49
50#define TPS6594_REG_GPIOX_CONF(gpio_inst) (0x31 + (gpio_inst))
51#define TPS6594_REG_NPWRON_CONF 0x3c
52#define TPS6594_REG_GPIO_OUT_1 0x3d
53#define TPS6594_REG_GPIO_OUT_2 0x3e
54#define TPS6594_REG_GPIO_IN_1 0x3f
55#define TPS6594_REG_GPIO_IN_2 0x40
56#define TPS6594_REG_GPIOX_OUT(gpio_inst) (TPS6594_REG_GPIO_OUT_1 + (gpio_inst) / 8)
57#define TPS6594_REG_GPIOX_IN(gpio_inst) (TPS6594_REG_GPIO_IN_1 + (gpio_inst) / 8)
58
59#define TPS6594_REG_GPIO_IN_1 0x3f
60#define TPS6594_REG_GPIO_IN_2 0x40
61
62#define TPS6594_REG_RAIL_SEL_1 0x41
63#define TPS6594_REG_RAIL_SEL_2 0x42
64#define TPS6594_REG_RAIL_SEL_3 0x43
65
66#define TPS6594_REG_FSM_TRIG_SEL_1 0x44
67#define TPS6594_REG_FSM_TRIG_SEL_2 0x45
68#define TPS6594_REG_FSM_TRIG_MASK_1 0x46
69#define TPS6594_REG_FSM_TRIG_MASK_2 0x47
70#define TPS6594_REG_FSM_TRIG_MASK_3 0x48
71
72#define TPS6594_REG_MASK_BUCK1_2 0x49
73#define TPS6594_REG_MASK_BUCK3_4 0x4a
74#define TPS6594_REG_MASK_BUCK5 0x4b
75#define TPS6594_REG_MASK_LDO1_2 0x4c
76#define TPS6594_REG_MASK_LDO3_4 0x4d
77#define TPS6594_REG_MASK_VMON 0x4e
78#define TPS6594_REG_MASK_GPIO1_8_FALL 0x4f
79#define TPS6594_REG_MASK_GPIO1_8_RISE 0x50
80#define TPS6594_REG_MASK_GPIO9_11 0x51
81#define TPS6594_REG_MASK_STARTUP 0x52
82#define TPS6594_REG_MASK_MISC 0x53
83#define TPS6594_REG_MASK_MODERATE_ERR 0x54
84#define TPS6594_REG_MASK_FSM_ERR 0x56
85#define TPS6594_REG_MASK_COMM_ERR 0x57
86#define TPS6594_REG_MASK_READBACK_ERR 0x58
87#define TPS6594_REG_MASK_ESM 0x59
88
89#define TPS6594_REG_INT_TOP 0x5a
90#define TPS6594_REG_INT_BUCK 0x5b
91#define TPS6594_REG_INT_BUCK1_2 0x5c
92#define TPS6594_REG_INT_BUCK3_4 0x5d
93#define TPS6594_REG_INT_BUCK5 0x5e
94#define TPS6594_REG_INT_LDO_VMON 0x5f
95#define TPS6594_REG_INT_LDO1_2 0x60
96#define TPS6594_REG_INT_LDO3_4 0x61
97#define TPS6594_REG_INT_VMON 0x62
98#define TPS6594_REG_INT_GPIO 0x63
99#define TPS6594_REG_INT_GPIO1_8 0x64
100#define TPS6594_REG_INT_STARTUP 0x65
101#define TPS6594_REG_INT_MISC 0x66
102#define TPS6594_REG_INT_MODERATE_ERR 0x67
103#define TPS6594_REG_INT_SEVERE_ERR 0x68
104#define TPS6594_REG_INT_FSM_ERR 0x69
105#define TPS6594_REG_INT_COMM_ERR 0x6a
106#define TPS6594_REG_INT_READBACK_ERR 0x6b
107#define TPS6594_REG_INT_ESM 0x6c
108
109#define TPS6594_REG_STAT_BUCK1_2 0x6d
110#define TPS6594_REG_STAT_BUCK3_4 0x6e
111#define TPS6594_REG_STAT_BUCK5 0x6f
112#define TPS6594_REG_STAT_LDO1_2 0x70
113#define TPS6594_REG_STAT_LDO3_4 0x71
114#define TPS6594_REG_STAT_VMON 0x72
115#define TPS6594_REG_STAT_STARTUP 0x73
116#define TPS6594_REG_STAT_MISC 0x74
117#define TPS6594_REG_STAT_MODERATE_ERR 0x75
118#define TPS6594_REG_STAT_SEVERE_ERR 0x76
119#define TPS6594_REG_STAT_READBACK_ERR 0x77
120
121#define TPS6594_REG_PGOOD_SEL_1 0x78
122#define TPS6594_REG_PGOOD_SEL_2 0x79
123#define TPS6594_REG_PGOOD_SEL_3 0x7a
124#define TPS6594_REG_PGOOD_SEL_4 0x7b
125
126#define TPS6594_REG_PLL_CTRL 0x7c
127
128#define TPS6594_REG_CONFIG_1 0x7d
129#define TPS6594_REG_CONFIG_2 0x7e
130
131#define TPS6594_REG_ENABLE_DRV_REG 0x80
132
133#define TPS6594_REG_MISC_CTRL 0x81
134
135#define TPS6594_REG_ENABLE_DRV_STAT 0x82
136
137#define TPS6594_REG_RECOV_CNT_REG_1 0x83
138#define TPS6594_REG_RECOV_CNT_REG_2 0x84
139
140#define TPS6594_REG_FSM_I2C_TRIGGERS 0x85
141#define TPS6594_REG_FSM_NSLEEP_TRIGGERS 0x86
142
143#define TPS6594_REG_BUCK_RESET_REG 0x87
144
145#define TPS6594_REG_SPREAD_SPECTRUM_1 0x88
146
147#define TPS6594_REG_FREQ_SEL 0x8a
148
149#define TPS6594_REG_FSM_STEP_SIZE 0x8b
150
151#define TPS6594_REG_LDO_RV_TIMEOUT_REG_1 0x8c
152#define TPS6594_REG_LDO_RV_TIMEOUT_REG_2 0x8d
153
154#define TPS6594_REG_USER_SPARE_REGS 0x8e
155
156#define TPS6594_REG_ESM_MCU_START_REG 0x8f
157#define TPS6594_REG_ESM_MCU_DELAY1_REG 0x90
158#define TPS6594_REG_ESM_MCU_DELAY2_REG 0x91
159#define TPS6594_REG_ESM_MCU_MODE_CFG 0x92
160#define TPS6594_REG_ESM_MCU_HMAX_REG 0x93
161#define TPS6594_REG_ESM_MCU_HMIN_REG 0x94
162#define TPS6594_REG_ESM_MCU_LMAX_REG 0x95
163#define TPS6594_REG_ESM_MCU_LMIN_REG 0x96
164#define TPS6594_REG_ESM_MCU_ERR_CNT_REG 0x97
165#define TPS6594_REG_ESM_SOC_START_REG 0x98
166#define TPS6594_REG_ESM_SOC_DELAY1_REG 0x99
167#define TPS6594_REG_ESM_SOC_DELAY2_REG 0x9a
168#define TPS6594_REG_ESM_SOC_MODE_CFG 0x9b
169#define TPS6594_REG_ESM_SOC_HMAX_REG 0x9c
170#define TPS6594_REG_ESM_SOC_HMIN_REG 0x9d
171#define TPS6594_REG_ESM_SOC_LMAX_REG 0x9e
172#define TPS6594_REG_ESM_SOC_LMIN_REG 0x9f
173#define TPS6594_REG_ESM_SOC_ERR_CNT_REG 0xa0
174
175#define TPS6594_REG_REGISTER_LOCK 0xa1
176
177#define TPS6594_REG_MANUFACTURING_VER 0xa6
178
179#define TPS6594_REG_CUSTOMER_NVM_ID_REG 0xa7
180
181#define TPS6594_REG_VMON_CONF_REG 0xa8
182
183#define TPS6594_REG_SOFT_REBOOT_REG 0xab
184
185#define TPS6594_REG_RTC_SECONDS 0xb5
186#define TPS6594_REG_RTC_MINUTES 0xb6
187#define TPS6594_REG_RTC_HOURS 0xb7
188#define TPS6594_REG_RTC_DAYS 0xb8
189#define TPS6594_REG_RTC_MONTHS 0xb9
190#define TPS6594_REG_RTC_YEARS 0xba
191#define TPS6594_REG_RTC_WEEKS 0xbb
192
193#define TPS6594_REG_ALARM_SECONDS 0xbc
194#define TPS6594_REG_ALARM_MINUTES 0xbd
195#define TPS6594_REG_ALARM_HOURS 0xbe
196#define TPS6594_REG_ALARM_DAYS 0xbf
197#define TPS6594_REG_ALARM_MONTHS 0xc0
198#define TPS6594_REG_ALARM_YEARS 0xc1
199
200#define TPS6594_REG_RTC_CTRL_1 0xc2
201#define TPS6594_REG_RTC_CTRL_2 0xc3
202#define TPS6594_REG_RTC_STATUS 0xc4
203#define TPS6594_REG_RTC_INTERRUPTS 0xc5
204#define TPS6594_REG_RTC_COMP_LSB 0xc6
205#define TPS6594_REG_RTC_COMP_MSB 0xc7
206#define TPS6594_REG_RTC_RESET_STATUS 0xc8
207
208#define TPS6594_REG_SCRATCH_PAD_REG_1 0xc9
209#define TPS6594_REG_SCRATCH_PAD_REG_2 0xca
210#define TPS6594_REG_SCRATCH_PAD_REG_3 0xcb
211#define TPS6594_REG_SCRATCH_PAD_REG_4 0xcc
212
213#define TPS6594_REG_PFSM_DELAY_REG_1 0xcd
214#define TPS6594_REG_PFSM_DELAY_REG_2 0xce
215#define TPS6594_REG_PFSM_DELAY_REG_3 0xcf
216#define TPS6594_REG_PFSM_DELAY_REG_4 0xd0
217
218/* Registers for page 1 of TPS6594 */
219#define TPS6594_REG_SERIAL_IF_CONFIG 0x11a
220#define TPS6594_REG_I2C1_ID 0x122
221#define TPS6594_REG_I2C2_ID 0x123
222
223/* Registers for page 4 of TPS6594 */
224#define TPS6594_REG_WD_ANSWER_REG 0x401
225#define TPS6594_REG_WD_QUESTION_ANSW_CNT 0x402
226#define TPS6594_REG_WD_WIN1_CFG 0x403
227#define TPS6594_REG_WD_WIN2_CFG 0x404
228#define TPS6594_REG_WD_LONGWIN_CFG 0x405
229#define TPS6594_REG_WD_MODE_REG 0x406
230#define TPS6594_REG_WD_QA_CFG 0x407
231#define TPS6594_REG_WD_ERR_STATUS 0x408
232#define TPS6594_REG_WD_THR_CFG 0x409
233#define TPS6594_REG_DWD_FAIL_CNT_REG 0x40a
234
235/* BUCKX_CTRL register field definition */
236#define TPS6594_BIT_BUCK_EN BIT(0)
237#define TPS6594_BIT_BUCK_FPWM BIT(1)
238#define TPS6594_BIT_BUCK_FPWM_MP BIT(2)
239#define TPS6594_BIT_BUCK_VSEL BIT(3)
240#define TPS6594_BIT_BUCK_VMON_EN BIT(4)
241#define TPS6594_BIT_BUCK_PLDN BIT(5)
242#define TPS6594_BIT_BUCK_RV_SEL BIT(7)
243
244/* BUCKX_CONF register field definition */
245#define TPS6594_MASK_BUCK_SLEW_RATE GENMASK(2, 0)
246#define TPS6594_MASK_BUCK_ILIM GENMASK(5, 3)
247
248/* BUCKX_PG_WINDOW register field definition */
249#define TPS6594_MASK_BUCK_OV_THR GENMASK(2, 0)
250#define TPS6594_MASK_BUCK_UV_THR GENMASK(5, 3)
251
252/* BUCKX VSET */
253#define TPS6594_MASK_BUCKS_VSET GENMASK(7, 0)
254
255/* LDOX_CTRL register field definition */
256#define TPS6594_BIT_LDO_EN BIT(0)
257#define TPS6594_BIT_LDO_SLOW_RAMP BIT(1)
258#define TPS6594_BIT_LDO_VMON_EN BIT(4)
259#define TPS6594_MASK_LDO_PLDN GENMASK(6, 5)
260#define TPS6594_BIT_LDO_RV_SEL BIT(7)
261
262/* LDORTC_CTRL register field definition */
263#define TPS6594_BIT_LDORTC_DIS BIT(0)
264
265/* LDOX_VOUT register field definition */
266#define TPS6594_MASK_LDO123_VSET GENMASK(6, 1)
267#define TPS6594_MASK_LDO4_VSET GENMASK(6, 0)
268#define TPS6594_BIT_LDO_BYPASS BIT(7)
269
270/* LDOX_PG_WINDOW register field definition */
271#define TPS6594_MASK_LDO_OV_THR GENMASK(2, 0)
272#define TPS6594_MASK_LDO_UV_THR GENMASK(5, 3)
273
274/* VCCA_VMON_CTRL register field definition */
275#define TPS6594_BIT_VMON_EN BIT(0)
276#define TPS6594_BIT_VMON1_EN BIT(1)
277#define TPS6594_BIT_VMON1_RV_SEL BIT(2)
278#define TPS6594_BIT_VMON2_EN BIT(3)
279#define TPS6594_BIT_VMON2_RV_SEL BIT(4)
280#define TPS6594_BIT_VMON_DEGLITCH_SEL BIT(5)
281
282/* VCCA_PG_WINDOW register field definition */
283#define TPS6594_MASK_VCCA_OV_THR GENMASK(2, 0)
284#define TPS6594_MASK_VCCA_UV_THR GENMASK(5, 3)
285#define TPS6594_BIT_VCCA_PG_SET BIT(6)
286
287/* VMONX_PG_WINDOW register field definition */
288#define TPS6594_MASK_VMONX_OV_THR GENMASK(2, 0)
289#define TPS6594_MASK_VMONX_UV_THR GENMASK(5, 3)
290#define TPS6594_BIT_VMONX_RANGE BIT(6)
291
292/* GPIOX_CONF register field definition */
293#define TPS6594_BIT_GPIO_DIR BIT(0)
294#define TPS6594_BIT_GPIO_OD BIT(1)
295#define TPS6594_BIT_GPIO_PU_SEL BIT(2)
296#define TPS6594_BIT_GPIO_PU_PD_EN BIT(3)
297#define TPS6594_BIT_GPIO_DEGLITCH_EN BIT(4)
298#define TPS6594_MASK_GPIO_SEL GENMASK(7, 5)
299
300/* NPWRON_CONF register field definition */
301#define TPS6594_BIT_NRSTOUT_OD BIT(0)
302#define TPS6594_BIT_ENABLE_PU_SEL BIT(2)
303#define TPS6594_BIT_ENABLE_PU_PD_EN BIT(3)
304#define TPS6594_BIT_ENABLE_DEGLITCH_EN BIT(4)
305#define TPS6594_BIT_ENABLE_POL BIT(5)
306#define TPS6594_MASK_NPWRON_SEL GENMASK(7, 6)
307
308/* GPIO_OUT_X register field definition */
309#define TPS6594_BIT_GPIOX_OUT(gpio_inst) BIT((gpio_inst) % 8)
310
311/* GPIO_IN_X register field definition */
312#define TPS6594_BIT_GPIOX_IN(gpio_inst) BIT((gpio_inst) % 8)
313#define TPS6594_BIT_NPWRON_IN BIT(3)
314
315/* RAIL_SEL_1 register field definition */
316#define TPS6594_MASK_BUCK1_GRP_SEL GENMASK(1, 0)
317#define TPS6594_MASK_BUCK2_GRP_SEL GENMASK(3, 2)
318#define TPS6594_MASK_BUCK3_GRP_SEL GENMASK(5, 4)
319#define TPS6594_MASK_BUCK4_GRP_SEL GENMASK(7, 6)
320
321/* RAIL_SEL_2 register field definition */
322#define TPS6594_MASK_BUCK5_GRP_SEL GENMASK(1, 0)
323#define TPS6594_MASK_LDO1_GRP_SEL GENMASK(3, 2)
324#define TPS6594_MASK_LDO2_GRP_SEL GENMASK(5, 4)
325#define TPS6594_MASK_LDO3_GRP_SEL GENMASK(7, 6)
326
327/* RAIL_SEL_3 register field definition */
328#define TPS6594_MASK_LDO4_GRP_SEL GENMASK(1, 0)
329#define TPS6594_MASK_VCCA_GRP_SEL GENMASK(3, 2)
330#define TPS6594_MASK_VMON1_GRP_SEL GENMASK(5, 4)
331#define TPS6594_MASK_VMON2_GRP_SEL GENMASK(7, 6)
332
333/* FSM_TRIG_SEL_1 register field definition */
334#define TPS6594_MASK_MCU_RAIL_TRIG GENMASK(1, 0)
335#define TPS6594_MASK_SOC_RAIL_TRIG GENMASK(3, 2)
336#define TPS6594_MASK_OTHER_RAIL_TRIG GENMASK(5, 4)
337#define TPS6594_MASK_SEVERE_ERR_TRIG GENMASK(7, 6)
338
339/* FSM_TRIG_SEL_2 register field definition */
340#define TPS6594_MASK_MODERATE_ERR_TRIG GENMASK(1, 0)
341
342/* FSM_TRIG_MASK_X register field definition */
343#define TPS6594_BIT_GPIOX_FSM_MASK(gpio_inst) BIT(((gpio_inst) << 1) % 8)
344#define TPS6594_BIT_GPIOX_FSM_MASK_POL(gpio_inst) BIT(((gpio_inst) << 1) % 8 + 1)
345
346/* MASK_BUCKX register field definition */
347#define TPS6594_BIT_BUCKX_OV_MASK(buck_inst) BIT(((buck_inst) << 2) % 8)
348#define TPS6594_BIT_BUCKX_UV_MASK(buck_inst) BIT(((buck_inst) << 2) % 8 + 1)
349#define TPS6594_BIT_BUCKX_ILIM_MASK(buck_inst) BIT(((buck_inst) << 2) % 8 + 3)
350
351/* MASK_LDOX register field definition */
352#define TPS6594_BIT_LDOX_OV_MASK(ldo_inst) BIT(((ldo_inst) << 2) % 8)
353#define TPS6594_BIT_LDOX_UV_MASK(ldo_inst) BIT(((ldo_inst) << 2) % 8 + 1)
354#define TPS6594_BIT_LDOX_ILIM_MASK(ldo_inst) BIT(((ldo_inst) << 2) % 8 + 3)
355
356/* MASK_VMON register field definition */
357#define TPS6594_BIT_VCCA_OV_MASK BIT(0)
358#define TPS6594_BIT_VCCA_UV_MASK BIT(1)
359#define TPS6594_BIT_VMON1_OV_MASK BIT(2)
360#define TPS6594_BIT_VMON1_UV_MASK BIT(3)
361#define TPS6594_BIT_VMON2_OV_MASK BIT(5)
362#define TPS6594_BIT_VMON2_UV_MASK BIT(6)
363
364/* MASK_GPIOX register field definition */
365#define TPS6594_BIT_GPIOX_FALL_MASK(gpio_inst) BIT((gpio_inst) < 8 ? \
366 (gpio_inst) : (gpio_inst) % 8)
367#define TPS6594_BIT_GPIOX_RISE_MASK(gpio_inst) BIT((gpio_inst) < 8 ? \
368 (gpio_inst) : (gpio_inst) % 8 + 3)
369
370/* MASK_STARTUP register field definition */
371#define TPS6594_BIT_NPWRON_START_MASK BIT(0)
372#define TPS6594_BIT_ENABLE_MASK BIT(1)
373#define TPS6594_BIT_FSD_MASK BIT(4)
374#define TPS6594_BIT_SOFT_REBOOT_MASK BIT(5)
375
376/* MASK_MISC register field definition */
377#define TPS6594_BIT_BIST_PASS_MASK BIT(0)
378#define TPS6594_BIT_EXT_CLK_MASK BIT(1)
379#define TPS6594_BIT_TWARN_MASK BIT(3)
380
381/* MASK_MODERATE_ERR register field definition */
382#define TPS6594_BIT_BIST_FAIL_MASK BIT(1)
383#define TPS6594_BIT_REG_CRC_ERR_MASK BIT(2)
384#define TPS6594_BIT_SPMI_ERR_MASK BIT(4)
385#define TPS6594_BIT_NPWRON_LONG_MASK BIT(5)
386#define TPS6594_BIT_NINT_READBACK_MASK BIT(6)
387#define TPS6594_BIT_NRSTOUT_READBACK_MASK BIT(7)
388
389/* MASK_FSM_ERR register field definition */
390#define TPS6594_BIT_IMM_SHUTDOWN_MASK BIT(0)
391#define TPS6594_BIT_ORD_SHUTDOWN_MASK BIT(1)
392#define TPS6594_BIT_MCU_PWR_ERR_MASK BIT(2)
393#define TPS6594_BIT_SOC_PWR_ERR_MASK BIT(3)
394
395/* MASK_COMM_ERR register field definition */
396#define TPS6594_BIT_COMM_FRM_ERR_MASK BIT(0)
397#define TPS6594_BIT_COMM_CRC_ERR_MASK BIT(1)
398#define TPS6594_BIT_COMM_ADR_ERR_MASK BIT(3)
399#define TPS6594_BIT_I2C2_CRC_ERR_MASK BIT(5)
400#define TPS6594_BIT_I2C2_ADR_ERR_MASK BIT(7)
401
402/* MASK_READBACK_ERR register field definition */
403#define TPS6594_BIT_EN_DRV_READBACK_MASK BIT(0)
404#define TPS6594_BIT_NRSTOUT_SOC_READBACK_MASK BIT(3)
405
406/* MASK_ESM register field definition */
407#define TPS6594_BIT_ESM_SOC_PIN_MASK BIT(0)
408#define TPS6594_BIT_ESM_SOC_FAIL_MASK BIT(1)
409#define TPS6594_BIT_ESM_SOC_RST_MASK BIT(2)
410#define TPS6594_BIT_ESM_MCU_PIN_MASK BIT(3)
411#define TPS6594_BIT_ESM_MCU_FAIL_MASK BIT(4)
412#define TPS6594_BIT_ESM_MCU_RST_MASK BIT(5)
413
414/* INT_TOP register field definition */
415#define TPS6594_BIT_BUCK_INT BIT(0)
416#define TPS6594_BIT_LDO_VMON_INT BIT(1)
417#define TPS6594_BIT_GPIO_INT BIT(2)
418#define TPS6594_BIT_STARTUP_INT BIT(3)
419#define TPS6594_BIT_MISC_INT BIT(4)
420#define TPS6594_BIT_MODERATE_ERR_INT BIT(5)
421#define TPS6594_BIT_SEVERE_ERR_INT BIT(6)
422#define TPS6594_BIT_FSM_ERR_INT BIT(7)
423
424/* INT_BUCK register field definition */
425#define TPS6594_BIT_BUCK1_2_INT BIT(0)
426#define TPS6594_BIT_BUCK3_4_INT BIT(1)
427#define TPS6594_BIT_BUCK5_INT BIT(2)
428
429/* INT_BUCKX register field definition */
430#define TPS6594_BIT_BUCKX_OV_INT(buck_inst) BIT(((buck_inst) << 2) % 8)
431#define TPS6594_BIT_BUCKX_UV_INT(buck_inst) BIT(((buck_inst) << 2) % 8 + 1)
432#define TPS6594_BIT_BUCKX_SC_INT(buck_inst) BIT(((buck_inst) << 2) % 8 + 2)
433#define TPS6594_BIT_BUCKX_ILIM_INT(buck_inst) BIT(((buck_inst) << 2) % 8 + 3)
434
435/* INT_LDO_VMON register field definition */
436#define TPS6594_BIT_LDO1_2_INT BIT(0)
437#define TPS6594_BIT_LDO3_4_INT BIT(1)
438#define TPS6594_BIT_VCCA_INT BIT(4)
439
440/* INT_LDOX register field definition */
441#define TPS6594_BIT_LDOX_OV_INT(ldo_inst) BIT(((ldo_inst) << 2) % 8)
442#define TPS6594_BIT_LDOX_UV_INT(ldo_inst) BIT(((ldo_inst) << 2) % 8 + 1)
443#define TPS6594_BIT_LDOX_SC_INT(ldo_inst) BIT(((ldo_inst) << 2) % 8 + 2)
444#define TPS6594_BIT_LDOX_ILIM_INT(ldo_inst) BIT(((ldo_inst) << 2) % 8 + 3)
445
446/* INT_VMON register field definition */
447#define TPS6594_BIT_VCCA_OV_INT BIT(0)
448#define TPS6594_BIT_VCCA_UV_INT BIT(1)
449#define TPS6594_BIT_VMON1_OV_INT BIT(2)
450#define TPS6594_BIT_VMON1_UV_INT BIT(3)
451#define TPS6594_BIT_VMON1_RV_INT BIT(4)
452#define TPS6594_BIT_VMON2_OV_INT BIT(5)
453#define TPS6594_BIT_VMON2_UV_INT BIT(6)
454#define TPS6594_BIT_VMON2_RV_INT BIT(7)
455
456/* INT_GPIO register field definition */
457#define TPS6594_BIT_GPIO9_INT BIT(0)
458#define TPS6594_BIT_GPIO10_INT BIT(1)
459#define TPS6594_BIT_GPIO11_INT BIT(2)
460#define TPS6594_BIT_GPIO1_8_INT BIT(3)
461
462/* INT_GPIOX register field definition */
463#define TPS6594_BIT_GPIOX_INT(gpio_inst) BIT(gpio_inst)
464
465/* INT_STARTUP register field definition */
466#define TPS6594_BIT_NPWRON_START_INT BIT(0)
467#define TPS6594_BIT_ENABLE_INT BIT(1)
468#define TPS6594_BIT_RTC_INT BIT(2)
469#define TPS6594_BIT_FSD_INT BIT(4)
470#define TPS6594_BIT_SOFT_REBOOT_INT BIT(5)
471
472/* INT_MISC register field definition */
473#define TPS6594_BIT_BIST_PASS_INT BIT(0)
474#define TPS6594_BIT_EXT_CLK_INT BIT(1)
475#define TPS6594_BIT_TWARN_INT BIT(3)
476
477/* INT_MODERATE_ERR register field definition */
478#define TPS6594_BIT_TSD_ORD_INT BIT(0)
479#define TPS6594_BIT_BIST_FAIL_INT BIT(1)
480#define TPS6594_BIT_REG_CRC_ERR_INT BIT(2)
481#define TPS6594_BIT_RECOV_CNT_INT BIT(3)
482#define TPS6594_BIT_SPMI_ERR_INT BIT(4)
483#define TPS6594_BIT_NPWRON_LONG_INT BIT(5)
484#define TPS6594_BIT_NINT_READBACK_INT BIT(6)
485#define TPS6594_BIT_NRSTOUT_READBACK_INT BIT(7)
486
487/* INT_SEVERE_ERR register field definition */
488#define TPS6594_BIT_TSD_IMM_INT BIT(0)
489#define TPS6594_BIT_VCCA_OVP_INT BIT(1)
490#define TPS6594_BIT_PFSM_ERR_INT BIT(2)
491
492/* INT_FSM_ERR register field definition */
493#define TPS6594_BIT_IMM_SHUTDOWN_INT BIT(0)
494#define TPS6594_BIT_ORD_SHUTDOWN_INT BIT(1)
495#define TPS6594_BIT_MCU_PWR_ERR_INT BIT(2)
496#define TPS6594_BIT_SOC_PWR_ERR_INT BIT(3)
497#define TPS6594_BIT_COMM_ERR_INT BIT(4)
498#define TPS6594_BIT_READBACK_ERR_INT BIT(5)
499#define TPS6594_BIT_ESM_INT BIT(6)
500#define TPS6594_BIT_WD_INT BIT(7)
501
502/* INT_COMM_ERR register field definition */
503#define TPS6594_BIT_COMM_FRM_ERR_INT BIT(0)
504#define TPS6594_BIT_COMM_CRC_ERR_INT BIT(1)
505#define TPS6594_BIT_COMM_ADR_ERR_INT BIT(3)
506#define TPS6594_BIT_I2C2_CRC_ERR_INT BIT(5)
507#define TPS6594_BIT_I2C2_ADR_ERR_INT BIT(7)
508
509/* INT_READBACK_ERR register field definition */
510#define TPS6594_BIT_EN_DRV_READBACK_INT BIT(0)
511#define TPS6594_BIT_NRSTOUT_SOC_READBACK_INT BIT(3)
512
513/* INT_ESM register field definition */
514#define TPS6594_BIT_ESM_SOC_PIN_INT BIT(0)
515#define TPS6594_BIT_ESM_SOC_FAIL_INT BIT(1)
516#define TPS6594_BIT_ESM_SOC_RST_INT BIT(2)
517#define TPS6594_BIT_ESM_MCU_PIN_INT BIT(3)
518#define TPS6594_BIT_ESM_MCU_FAIL_INT BIT(4)
519#define TPS6594_BIT_ESM_MCU_RST_INT BIT(5)
520
521/* STAT_BUCKX register field definition */
522#define TPS6594_BIT_BUCKX_OV_STAT(buck_inst) BIT(((buck_inst) << 2) % 8)
523#define TPS6594_BIT_BUCKX_UV_STAT(buck_inst) BIT(((buck_inst) << 2) % 8 + 1)
524#define TPS6594_BIT_BUCKX_ILIM_STAT(buck_inst) BIT(((buck_inst) << 2) % 8 + 3)
525
526/* STAT_LDOX register field definition */
527#define TPS6594_BIT_LDOX_OV_STAT(ldo_inst) BIT(((ldo_inst) << 2) % 8)
528#define TPS6594_BIT_LDOX_UV_STAT(ldo_inst) BIT(((ldo_inst) << 2) % 8 + 1)
529#define TPS6594_BIT_LDOX_ILIM_STAT(ldo_inst) BIT(((ldo_inst) << 2) % 8 + 3)
530
531/* STAT_VMON register field definition */
532#define TPS6594_BIT_VCCA_OV_STAT BIT(0)
533#define TPS6594_BIT_VCCA_UV_STAT BIT(1)
534#define TPS6594_BIT_VMON1_OV_STAT BIT(2)
535#define TPS6594_BIT_VMON1_UV_STAT BIT(3)
536#define TPS6594_BIT_VMON2_OV_STAT BIT(5)
537#define TPS6594_BIT_VMON2_UV_STAT BIT(6)
538
539/* STAT_STARTUP register field definition */
540#define TPS6594_BIT_ENABLE_STAT BIT(1)
541
542/* STAT_MISC register field definition */
543#define TPS6594_BIT_EXT_CLK_STAT BIT(1)
544#define TPS6594_BIT_TWARN_STAT BIT(3)
545
546/* STAT_MODERATE_ERR register field definition */
547#define TPS6594_BIT_TSD_ORD_STAT BIT(0)
548
549/* STAT_SEVERE_ERR register field definition */
550#define TPS6594_BIT_TSD_IMM_STAT BIT(0)
551#define TPS6594_BIT_VCCA_OVP_STAT BIT(1)
552
553/* STAT_READBACK_ERR register field definition */
554#define TPS6594_BIT_EN_DRV_READBACK_STAT BIT(0)
555#define TPS6594_BIT_NINT_READBACK_STAT BIT(1)
556#define TPS6594_BIT_NRSTOUT_READBACK_STAT BIT(2)
557#define TPS6594_BIT_NRSTOUT_SOC_READBACK_STAT BIT(3)
558
559/* PGOOD_SEL_1 register field definition */
560#define TPS6594_MASK_PGOOD_SEL_BUCK1 GENMASK(1, 0)
561#define TPS6594_MASK_PGOOD_SEL_BUCK2 GENMASK(3, 2)
562#define TPS6594_MASK_PGOOD_SEL_BUCK3 GENMASK(5, 4)
563#define TPS6594_MASK_PGOOD_SEL_BUCK4 GENMASK(7, 6)
564
565/* PGOOD_SEL_2 register field definition */
566#define TPS6594_MASK_PGOOD_SEL_BUCK5 GENMASK(1, 0)
567
568/* PGOOD_SEL_3 register field definition */
569#define TPS6594_MASK_PGOOD_SEL_LDO1 GENMASK(1, 0)
570#define TPS6594_MASK_PGOOD_SEL_LDO2 GENMASK(3, 2)
571#define TPS6594_MASK_PGOOD_SEL_LDO3 GENMASK(5, 4)
572#define TPS6594_MASK_PGOOD_SEL_LDO4 GENMASK(7, 6)
573
574/* PGOOD_SEL_4 register field definition */
575#define TPS6594_BIT_PGOOD_SEL_VCCA BIT(0)
576#define TPS6594_BIT_PGOOD_SEL_VMON1 BIT(1)
577#define TPS6594_BIT_PGOOD_SEL_VMON2 BIT(2)
578#define TPS6594_BIT_PGOOD_SEL_TDIE_WARN BIT(3)
579#define TPS6594_BIT_PGOOD_SEL_NRSTOUT BIT(4)
580#define TPS6594_BIT_PGOOD_SEL_NRSTOUT_SOC BIT(5)
581#define TPS6594_BIT_PGOOD_POL BIT(6)
582#define TPS6594_BIT_PGOOD_WINDOW BIT(7)
583
584/* PLL_CTRL register field definition */
585#define TPS6594_MASK_EXT_CLK_FREQ GENMASK(1, 0)
586
587/* CONFIG_1 register field definition */
588#define TPS6594_BIT_TWARN_LEVEL BIT(0)
589#define TPS6594_BIT_TSD_ORD_LEVEL BIT(1)
590#define TPS6594_BIT_I2C1_HS BIT(3)
591#define TPS6594_BIT_I2C2_HS BIT(4)
592#define TPS6594_BIT_EN_ILIM_FSM_CTRL BIT(5)
593#define TPS6594_BIT_NSLEEP1_MASK BIT(6)
594#define TPS6594_BIT_NSLEEP2_MASK BIT(7)
595
596/* CONFIG_2 register field definition */
597#define TPS6594_BIT_BB_CHARGER_EN BIT(0)
598#define TPS6594_BIT_BB_ICHR BIT(1)
599#define TPS6594_MASK_BB_VEOC GENMASK(3, 2)
600#define TPS6594_BB_EOC_RDY BIT(7)
601
602/* ENABLE_DRV_REG register field definition */
603#define TPS6594_BIT_ENABLE_DRV BIT(0)
604
605/* MISC_CTRL register field definition */
606#define TPS6594_BIT_NRSTOUT BIT(0)
607#define TPS6594_BIT_NRSTOUT_SOC BIT(1)
608#define TPS6594_BIT_LPM_EN BIT(2)
609#define TPS6594_BIT_CLKMON_EN BIT(3)
610#define TPS6594_BIT_AMUXOUT_EN BIT(4)
611#define TPS6594_BIT_SEL_EXT_CLK BIT(5)
612#define TPS6594_MASK_SYNCCLKOUT_FREQ_SEL GENMASK(7, 6)
613
614/* ENABLE_DRV_STAT register field definition */
615#define TPS6594_BIT_EN_DRV_IN BIT(0)
616#define TPS6594_BIT_NRSTOUT_IN BIT(1)
617#define TPS6594_BIT_NRSTOUT_SOC_IN BIT(2)
618#define TPS6594_BIT_FORCE_EN_DRV_LOW BIT(3)
619#define TPS6594_BIT_SPMI_LPM_EN BIT(4)
620
621/* RECOV_CNT_REG_1 register field definition */
622#define TPS6594_MASK_RECOV_CNT GENMASK(3, 0)
623
624/* RECOV_CNT_REG_2 register field definition */
625#define TPS6594_MASK_RECOV_CNT_THR GENMASK(3, 0)
626#define TPS6594_BIT_RECOV_CNT_CLR BIT(4)
627
628/* FSM_I2C_TRIGGERS register field definition */
629#define TPS6594_BIT_TRIGGER_I2C(bit) BIT(bit)
630
631/* FSM_NSLEEP_TRIGGERS register field definition */
632#define TPS6594_BIT_NSLEEP1B BIT(0)
633#define TPS6594_BIT_NSLEEP2B BIT(1)
634
635/* BUCK_RESET_REG register field definition */
636#define TPS6594_BIT_BUCKX_RESET(buck_inst) BIT(buck_inst)
637
638/* SPREAD_SPECTRUM_1 register field definition */
639#define TPS6594_MASK_SS_DEPTH GENMASK(1, 0)
640#define TPS6594_BIT_SS_EN BIT(2)
641
642/* FREQ_SEL register field definition */
643#define TPS6594_BIT_BUCKX_FREQ_SEL(buck_inst) BIT(buck_inst)
644
645/* FSM_STEP_SIZE register field definition */
646#define TPS6594_MASK_PFSM_DELAY_STEP GENMASK(4, 0)
647
648/* LDO_RV_TIMEOUT_REG_1 register field definition */
649#define TPS6594_MASK_LDO1_RV_TIMEOUT GENMASK(3, 0)
650#define TPS6594_MASK_LDO2_RV_TIMEOUT GENMASK(7, 4)
651
652/* LDO_RV_TIMEOUT_REG_2 register field definition */
653#define TPS6594_MASK_LDO3_RV_TIMEOUT GENMASK(3, 0)
654#define TPS6594_MASK_LDO4_RV_TIMEOUT GENMASK(7, 4)
655
656/* USER_SPARE_REGS register field definition */
657#define TPS6594_BIT_USER_SPARE(bit) BIT(bit)
658
659/* ESM_MCU_START_REG register field definition */
660#define TPS6594_BIT_ESM_MCU_START BIT(0)
661
662/* ESM_MCU_MODE_CFG register field definition */
663#define TPS6594_MASK_ESM_MCU_ERR_CNT_TH GENMASK(3, 0)
664#define TPS6594_BIT_ESM_MCU_ENDRV BIT(5)
665#define TPS6594_BIT_ESM_MCU_EN BIT(6)
666#define TPS6594_BIT_ESM_MCU_MODE BIT(7)
667
668/* ESM_MCU_ERR_CNT_REG register field definition */
669#define TPS6594_MASK_ESM_MCU_ERR_CNT GENMASK(4, 0)
670
671/* ESM_SOC_START_REG register field definition */
672#define TPS6594_BIT_ESM_SOC_START BIT(0)
673
674/* ESM_SOC_MODE_CFG register field definition */
675#define TPS6594_MASK_ESM_SOC_ERR_CNT_TH GENMASK(3, 0)
676#define TPS6594_BIT_ESM_SOC_ENDRV BIT(5)
677#define TPS6594_BIT_ESM_SOC_EN BIT(6)
678#define TPS6594_BIT_ESM_SOC_MODE BIT(7)
679
680/* ESM_SOC_ERR_CNT_REG register field definition */
681#define TPS6594_MASK_ESM_SOC_ERR_CNT GENMASK(4, 0)
682
683/* REGISTER_LOCK register field definition */
684#define TPS6594_BIT_REGISTER_LOCK_STATUS BIT(0)
685
686/* VMON_CONF register field definition */
687#define TPS6594_MASK_VMON1_SLEW_RATE GENMASK(2, 0)
688#define TPS6594_MASK_VMON2_SLEW_RATE GENMASK(5, 3)
689
690/* SOFT_REBOOT_REG register field definition */
691#define TPS6594_BIT_SOFT_REBOOT BIT(0)
692
693/* RTC_SECONDS & ALARM_SECONDS register field definition */
694#define TPS6594_MASK_SECOND_0 GENMASK(3, 0)
695#define TPS6594_MASK_SECOND_1 GENMASK(6, 4)
696
697/* RTC_MINUTES & ALARM_MINUTES register field definition */
698#define TPS6594_MASK_MINUTE_0 GENMASK(3, 0)
699#define TPS6594_MASK_MINUTE_1 GENMASK(6, 4)
700
701/* RTC_HOURS & ALARM_HOURS register field definition */
702#define TPS6594_MASK_HOUR_0 GENMASK(3, 0)
703#define TPS6594_MASK_HOUR_1 GENMASK(5, 4)
704#define TPS6594_BIT_PM_NAM BIT(7)
705
706/* RTC_DAYS & ALARM_DAYS register field definition */
707#define TPS6594_MASK_DAY_0 GENMASK(3, 0)
708#define TPS6594_MASK_DAY_1 GENMASK(5, 4)
709
710/* RTC_MONTHS & ALARM_MONTHS register field definition */
711#define TPS6594_MASK_MONTH_0 GENMASK(3, 0)
712#define TPS6594_BIT_MONTH_1 BIT(4)
713
714/* RTC_YEARS & ALARM_YEARS register field definition */
715#define TPS6594_MASK_YEAR_0 GENMASK(3, 0)
716#define TPS6594_MASK_YEAR_1 GENMASK(7, 4)
717
718/* RTC_WEEKS register field definition */
719#define TPS6594_MASK_WEEK GENMASK(2, 0)
720
721/* RTC_CTRL_1 register field definition */
722#define TPS6594_BIT_STOP_RTC BIT(0)
723#define TPS6594_BIT_ROUND_30S BIT(1)
724#define TPS6594_BIT_AUTO_COMP BIT(2)
725#define TPS6594_BIT_MODE_12_24 BIT(3)
726#define TPS6594_BIT_SET_32_COUNTER BIT(5)
727#define TPS6594_BIT_GET_TIME BIT(6)
728#define TPS6594_BIT_RTC_V_OPT BIT(7)
729
730/* RTC_CTRL_2 register field definition */
731#define TPS6594_BIT_XTAL_EN BIT(0)
732#define TPS6594_MASK_XTAL_SEL GENMASK(2, 1)
733#define TPS6594_BIT_LP_STANDBY_SEL BIT(3)
734#define TPS6594_BIT_FAST_BIST BIT(4)
735#define TPS6594_MASK_STARTUP_DEST GENMASK(6, 5)
736#define TPS6594_BIT_FIRST_STARTUP_DONE BIT(7)
737
738/* RTC_STATUS register field definition */
739#define TPS6594_BIT_RUN BIT(1)
740#define TPS6594_BIT_TIMER BIT(5)
741#define TPS6594_BIT_ALARM BIT(6)
742#define TPS6594_BIT_POWER_UP BIT(7)
743
744/* RTC_INTERRUPTS register field definition */
745#define TPS6594_MASK_EVERY GENMASK(1, 0)
746#define TPS6594_BIT_IT_TIMER BIT(2)
747#define TPS6594_BIT_IT_ALARM BIT(3)
748
749/* RTC_RESET_STATUS register field definition */
750#define TPS6594_BIT_RESET_STATUS_RTC BIT(0)
751
752/* SERIAL_IF_CONFIG register field definition */
753#define TPS6594_BIT_I2C_SPI_SEL BIT(0)
754#define TPS6594_BIT_I2C1_SPI_CRC_EN BIT(1)
755#define TPS6594_BIT_I2C2_CRC_EN BIT(2)
756#define TPS6594_MASK_T_CRC GENMASK(7, 3)
757
758/* WD_QUESTION_ANSW_CNT register field definition */
759#define TPS6594_MASK_WD_QUESTION GENMASK(3, 0)
760#define TPS6594_MASK_WD_ANSW_CNT GENMASK(5, 4)
761
762/* WD_MODE_REG register field definition */
763#define TPS6594_BIT_WD_RETURN_LONGWIN BIT(0)
764#define TPS6594_BIT_WD_MODE_SELECT BIT(1)
765#define TPS6594_BIT_WD_PWRHOLD BIT(2)
766
767/* WD_QA_CFG register field definition */
768#define TPS6594_MASK_WD_QUESTION_SEED GENMASK(3, 0)
769#define TPS6594_MASK_WD_QA_LFSR GENMASK(5, 4)
770#define TPS6594_MASK_WD_QA_FDBK GENMASK(7, 6)
771
772/* WD_ERR_STATUS register field definition */
773#define TPS6594_BIT_WD_LONGWIN_TIMEOUT_INT BIT(0)
774#define TPS6594_BIT_WD_TIMEOUT BIT(1)
775#define TPS6594_BIT_WD_TRIG_EARLY BIT(2)
776#define TPS6594_BIT_WD_ANSW_EARLY BIT(3)
777#define TPS6594_BIT_WD_SEQ_ERR BIT(4)
778#define TPS6594_BIT_WD_ANSW_ERR BIT(5)
779#define TPS6594_BIT_WD_FAIL_INT BIT(6)
780#define TPS6594_BIT_WD_RST_INT BIT(7)
781
782/* WD_THR_CFG register field definition */
783#define TPS6594_MASK_WD_RST_TH GENMASK(2, 0)
784#define TPS6594_MASK_WD_FAIL_TH GENMASK(5, 3)
785#define TPS6594_BIT_WD_EN BIT(6)
786#define TPS6594_BIT_WD_RST_EN BIT(7)
787
788/* WD_FAIL_CNT_REG register field definition */
789#define TPS6594_MASK_WD_FAIL_CNT GENMASK(3, 0)
790#define TPS6594_BIT_WD_FIRST_OK BIT(5)
791#define TPS6594_BIT_WD_BAD_EVENT BIT(6)
792
793/* CRC8 polynomial for I2C & SPI protocols */
794#define TPS6594_CRC8_POLYNOMIAL 0x07
795
796/* IRQs */
797enum tps6594_irqs {
798 /* INT_BUCK1_2 register */
799 TPS6594_IRQ_BUCK1_OV,
800 TPS6594_IRQ_BUCK1_UV,
801 TPS6594_IRQ_BUCK1_SC,
802 TPS6594_IRQ_BUCK1_ILIM,
803 TPS6594_IRQ_BUCK2_OV,
804 TPS6594_IRQ_BUCK2_UV,
805 TPS6594_IRQ_BUCK2_SC,
806 TPS6594_IRQ_BUCK2_ILIM,
807 /* INT_BUCK3_4 register */
808 TPS6594_IRQ_BUCK3_OV,
809 TPS6594_IRQ_BUCK3_UV,
810 TPS6594_IRQ_BUCK3_SC,
811 TPS6594_IRQ_BUCK3_ILIM,
812 TPS6594_IRQ_BUCK4_OV,
813 TPS6594_IRQ_BUCK4_UV,
814 TPS6594_IRQ_BUCK4_SC,
815 TPS6594_IRQ_BUCK4_ILIM,
816 /* INT_BUCK5 register */
817 TPS6594_IRQ_BUCK5_OV,
818 TPS6594_IRQ_BUCK5_UV,
819 TPS6594_IRQ_BUCK5_SC,
820 TPS6594_IRQ_BUCK5_ILIM,
821 /* INT_LDO1_2 register */
822 TPS6594_IRQ_LDO1_OV,
823 TPS6594_IRQ_LDO1_UV,
824 TPS6594_IRQ_LDO1_SC,
825 TPS6594_IRQ_LDO1_ILIM,
826 TPS6594_IRQ_LDO2_OV,
827 TPS6594_IRQ_LDO2_UV,
828 TPS6594_IRQ_LDO2_SC,
829 TPS6594_IRQ_LDO2_ILIM,
830 /* INT_LDO3_4 register */
831 TPS6594_IRQ_LDO3_OV,
832 TPS6594_IRQ_LDO3_UV,
833 TPS6594_IRQ_LDO3_SC,
834 TPS6594_IRQ_LDO3_ILIM,
835 TPS6594_IRQ_LDO4_OV,
836 TPS6594_IRQ_LDO4_UV,
837 TPS6594_IRQ_LDO4_SC,
838 TPS6594_IRQ_LDO4_ILIM,
839 /* INT_VMON register */
840 TPS6594_IRQ_VCCA_OV,
841 TPS6594_IRQ_VCCA_UV,
842 TPS6594_IRQ_VMON1_OV,
843 TPS6594_IRQ_VMON1_UV,
844 TPS6594_IRQ_VMON1_RV,
845 TPS6594_IRQ_VMON2_OV,
846 TPS6594_IRQ_VMON2_UV,
847 TPS6594_IRQ_VMON2_RV,
848 /* INT_GPIO register */
849 TPS6594_IRQ_GPIO9,
850 TPS6594_IRQ_GPIO10,
851 TPS6594_IRQ_GPIO11,
852 /* INT_GPIO1_8 register */
853 TPS6594_IRQ_GPIO1,
854 TPS6594_IRQ_GPIO2,
855 TPS6594_IRQ_GPIO3,
856 TPS6594_IRQ_GPIO4,
857 TPS6594_IRQ_GPIO5,
858 TPS6594_IRQ_GPIO6,
859 TPS6594_IRQ_GPIO7,
860 TPS6594_IRQ_GPIO8,
861 /* INT_STARTUP register */
862 TPS6594_IRQ_NPWRON_START,
863 TPS6594_IRQ_ENABLE,
864 TPS6594_IRQ_FSD,
865 TPS6594_IRQ_SOFT_REBOOT,
866 /* INT_MISC register */
867 TPS6594_IRQ_BIST_PASS,
868 TPS6594_IRQ_EXT_CLK,
869 TPS6594_IRQ_TWARN,
870 /* INT_MODERATE_ERR register */
871 TPS6594_IRQ_TSD_ORD,
872 TPS6594_IRQ_BIST_FAIL,
873 TPS6594_IRQ_REG_CRC_ERR,
874 TPS6594_IRQ_RECOV_CNT,
875 TPS6594_IRQ_SPMI_ERR,
876 TPS6594_IRQ_NPWRON_LONG,
877 TPS6594_IRQ_NINT_READBACK,
878 TPS6594_IRQ_NRSTOUT_READBACK,
879 /* INT_SEVERE_ERR register */
880 TPS6594_IRQ_TSD_IMM,
881 TPS6594_IRQ_VCCA_OVP,
882 TPS6594_IRQ_PFSM_ERR,
883 /* INT_FSM_ERR register */
884 TPS6594_IRQ_IMM_SHUTDOWN,
885 TPS6594_IRQ_ORD_SHUTDOWN,
886 TPS6594_IRQ_MCU_PWR_ERR,
887 TPS6594_IRQ_SOC_PWR_ERR,
888 /* INT_COMM_ERR register */
889 TPS6594_IRQ_COMM_FRM_ERR,
890 TPS6594_IRQ_COMM_CRC_ERR,
891 TPS6594_IRQ_COMM_ADR_ERR,
892 TPS6594_IRQ_I2C2_CRC_ERR,
893 TPS6594_IRQ_I2C2_ADR_ERR,
894 /* INT_READBACK_ERR register */
895 TPS6594_IRQ_EN_DRV_READBACK,
896 TPS6594_IRQ_NRSTOUT_SOC_READBACK,
897 /* INT_ESM register */
898 TPS6594_IRQ_ESM_SOC_PIN,
899 TPS6594_IRQ_ESM_SOC_FAIL,
900 TPS6594_IRQ_ESM_SOC_RST,
901 /* RTC_STATUS register */
902 TPS6594_IRQ_TIMER,
903 TPS6594_IRQ_ALARM,
904 TPS6594_IRQ_POWER_UP,
905};
906
907#define TPS6594_IRQ_NAME_BUCK1_OV "buck1_ov"
908#define TPS6594_IRQ_NAME_BUCK1_UV "buck1_uv"
909#define TPS6594_IRQ_NAME_BUCK1_SC "buck1_sc"
910#define TPS6594_IRQ_NAME_BUCK1_ILIM "buck1_ilim"
911#define TPS6594_IRQ_NAME_BUCK2_OV "buck2_ov"
912#define TPS6594_IRQ_NAME_BUCK2_UV "buck2_uv"
913#define TPS6594_IRQ_NAME_BUCK2_SC "buck2_sc"
914#define TPS6594_IRQ_NAME_BUCK2_ILIM "buck2_ilim"
915#define TPS6594_IRQ_NAME_BUCK3_OV "buck3_ov"
916#define TPS6594_IRQ_NAME_BUCK3_UV "buck3_uv"
917#define TPS6594_IRQ_NAME_BUCK3_SC "buck3_sc"
918#define TPS6594_IRQ_NAME_BUCK3_ILIM "buck3_ilim"
919#define TPS6594_IRQ_NAME_BUCK4_OV "buck4_ov"
920#define TPS6594_IRQ_NAME_BUCK4_UV "buck4_uv"
921#define TPS6594_IRQ_NAME_BUCK4_SC "buck4_sc"
922#define TPS6594_IRQ_NAME_BUCK4_ILIM "buck4_ilim"
923#define TPS6594_IRQ_NAME_BUCK5_OV "buck5_ov"
924#define TPS6594_IRQ_NAME_BUCK5_UV "buck5_uv"
925#define TPS6594_IRQ_NAME_BUCK5_SC "buck5_sc"
926#define TPS6594_IRQ_NAME_BUCK5_ILIM "buck5_ilim"
927#define TPS6594_IRQ_NAME_LDO1_OV "ldo1_ov"
928#define TPS6594_IRQ_NAME_LDO1_UV "ldo1_uv"
929#define TPS6594_IRQ_NAME_LDO1_SC "ldo1_sc"
930#define TPS6594_IRQ_NAME_LDO1_ILIM "ldo1_ilim"
931#define TPS6594_IRQ_NAME_LDO2_OV "ldo2_ov"
932#define TPS6594_IRQ_NAME_LDO2_UV "ldo2_uv"
933#define TPS6594_IRQ_NAME_LDO2_SC "ldo2_sc"
934#define TPS6594_IRQ_NAME_LDO2_ILIM "ldo2_ilim"
935#define TPS6594_IRQ_NAME_LDO3_OV "ldo3_ov"
936#define TPS6594_IRQ_NAME_LDO3_UV "ldo3_uv"
937#define TPS6594_IRQ_NAME_LDO3_SC "ldo3_sc"
938#define TPS6594_IRQ_NAME_LDO3_ILIM "ldo3_ilim"
939#define TPS6594_IRQ_NAME_LDO4_OV "ldo4_ov"
940#define TPS6594_IRQ_NAME_LDO4_UV "ldo4_uv"
941#define TPS6594_IRQ_NAME_LDO4_SC "ldo4_sc"
942#define TPS6594_IRQ_NAME_LDO4_ILIM "ldo4_ilim"
943#define TPS6594_IRQ_NAME_VCCA_OV "vcca_ov"
944#define TPS6594_IRQ_NAME_VCCA_UV "vcca_uv"
945#define TPS6594_IRQ_NAME_VMON1_OV "vmon1_ov"
946#define TPS6594_IRQ_NAME_VMON1_UV "vmon1_uv"
947#define TPS6594_IRQ_NAME_VMON1_RV "vmon1_rv"
948#define TPS6594_IRQ_NAME_VMON2_OV "vmon2_ov"
949#define TPS6594_IRQ_NAME_VMON2_UV "vmon2_uv"
950#define TPS6594_IRQ_NAME_VMON2_RV "vmon2_rv"
951#define TPS6594_IRQ_NAME_GPIO9 "gpio9"
952#define TPS6594_IRQ_NAME_GPIO10 "gpio10"
953#define TPS6594_IRQ_NAME_GPIO11 "gpio11"
954#define TPS6594_IRQ_NAME_GPIO1 "gpio1"
955#define TPS6594_IRQ_NAME_GPIO2 "gpio2"
956#define TPS6594_IRQ_NAME_GPIO3 "gpio3"
957#define TPS6594_IRQ_NAME_GPIO4 "gpio4"
958#define TPS6594_IRQ_NAME_GPIO5 "gpio5"
959#define TPS6594_IRQ_NAME_GPIO6 "gpio6"
960#define TPS6594_IRQ_NAME_GPIO7 "gpio7"
961#define TPS6594_IRQ_NAME_GPIO8 "gpio8"
962#define TPS6594_IRQ_NAME_NPWRON_START "npwron_start"
963#define TPS6594_IRQ_NAME_ENABLE "enable"
964#define TPS6594_IRQ_NAME_FSD "fsd"
965#define TPS6594_IRQ_NAME_SOFT_REBOOT "soft_reboot"
966#define TPS6594_IRQ_NAME_BIST_PASS "bist_pass"
967#define TPS6594_IRQ_NAME_EXT_CLK "ext_clk"
968#define TPS6594_IRQ_NAME_TWARN "twarn"
969#define TPS6594_IRQ_NAME_TSD_ORD "tsd_ord"
970#define TPS6594_IRQ_NAME_BIST_FAIL "bist_fail"
971#define TPS6594_IRQ_NAME_REG_CRC_ERR "reg_crc_err"
972#define TPS6594_IRQ_NAME_RECOV_CNT "recov_cnt"
973#define TPS6594_IRQ_NAME_SPMI_ERR "spmi_err"
974#define TPS6594_IRQ_NAME_NPWRON_LONG "npwron_long"
975#define TPS6594_IRQ_NAME_NINT_READBACK "nint_readback"
976#define TPS6594_IRQ_NAME_NRSTOUT_READBACK "nrstout_readback"
977#define TPS6594_IRQ_NAME_TSD_IMM "tsd_imm"
978#define TPS6594_IRQ_NAME_VCCA_OVP "vcca_ovp"
979#define TPS6594_IRQ_NAME_PFSM_ERR "pfsm_err"
980#define TPS6594_IRQ_NAME_IMM_SHUTDOWN "imm_shutdown"
981#define TPS6594_IRQ_NAME_ORD_SHUTDOWN "ord_shutdown"
982#define TPS6594_IRQ_NAME_MCU_PWR_ERR "mcu_pwr_err"
983#define TPS6594_IRQ_NAME_SOC_PWR_ERR "soc_pwr_err"
984#define TPS6594_IRQ_NAME_COMM_FRM_ERR "comm_frm_err"
985#define TPS6594_IRQ_NAME_COMM_CRC_ERR "comm_crc_err"
986#define TPS6594_IRQ_NAME_COMM_ADR_ERR "comm_adr_err"
987#define TPS6594_IRQ_NAME_EN_DRV_READBACK "en_drv_readback"
988#define TPS6594_IRQ_NAME_NRSTOUT_SOC_READBACK "nrstout_soc_readback"
989#define TPS6594_IRQ_NAME_ESM_SOC_PIN "esm_soc_pin"
990#define TPS6594_IRQ_NAME_ESM_SOC_FAIL "esm_soc_fail"
991#define TPS6594_IRQ_NAME_ESM_SOC_RST "esm_soc_rst"
992#define TPS6594_IRQ_NAME_TIMER "timer"
993#define TPS6594_IRQ_NAME_ALARM "alarm"
994#define TPS6594_IRQ_NAME_POWERUP "powerup"
995
996/**
997 * struct tps6594 - device private data structure
998 *
999 * @dev: MFD parent device
1000 * @chip_id: chip ID
1001 * @reg: I2C slave address or SPI chip select number
1002 * @use_crc: if true, use CRC for I2C and SPI interface protocols
1003 * @regmap: regmap for accessing the device registers
1004 * @irq: irq generated by the device
1005 * @irq_data: regmap irq data used for the irq chip
1006 */
1007struct tps6594 {
1008 struct device *dev;
1009 unsigned long chip_id;
1010 unsigned short reg;
1011 bool use_crc;
1012 struct regmap *regmap;
1013 int irq;
1014 struct regmap_irq_chip_data *irq_data;
1015};
1016
1017bool tps6594_is_volatile_reg(struct device *dev, unsigned int reg);
1018int tps6594_device_init(struct tps6594 *tps, bool enable_crc);
1019
1020#endif /* __LINUX_MFD_TPS6594_H */
1021

source code of linux/include/linux/mfd/tps6594.h