| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | |
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| 3 | #ifndef _WCD934X_REGISTERS_H |
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| 4 | #define _WCD934X_REGISTERS_H |
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| 5 | |
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| 6 | #define WCD934X_CODEC_RPM_CLK_GATE 0x0002 |
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| 7 | #define WCD934X_CODEC_RPM_CLK_GATE_MASK GENMASK(1, 0) |
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| 8 | #define WCD934X_CODEC_RPM_CLK_MCLK_CFG 0x0003 |
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| 9 | #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ BIT(0) |
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| 10 | #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ BIT(1) |
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| 11 | #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK GENMASK(1, 0) |
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| 12 | #define WCD934X_CODEC_RPM_RST_CTL 0x0009 |
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| 13 | #define WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL 0x0011 |
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| 14 | #define WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0 0x0021 |
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| 15 | #define WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE2 0x0023 |
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| 16 | #define WCD934X_CHIP_TIER_CTRL_EFUSE_CTL 0x0025 |
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| 17 | #define WCD934X_EFUSE_SENSE_STATE_MASK GENMASK(4, 1) |
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| 18 | #define WCD934X_EFUSE_SENSE_STATE_DEF 0x10 |
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| 19 | #define WCD934X_EFUSE_SENSE_EN_MASK BIT(0) |
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| 20 | #define WCD934X_EFUSE_SENSE_ENABLE BIT(0) |
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| 21 | #define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 0x002a |
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| 22 | #define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 0x002b |
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| 23 | #define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14 0x0037 |
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| 24 | #define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15 0x0038 |
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| 25 | #define WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS 0x0039 |
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| 26 | #define WCD934X_DATA_HUB_SB_TX10_INP_CFG 0x006b |
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| 27 | #define WCD934X_DATA_HUB_SB_TX11_INP_CFG 0x006c |
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| 28 | #define WCD934X_DATA_HUB_SB_TX13_INP_CFG 0x006e |
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| 29 | #define WCD934X_CPE_FLL_CONFIG_CTL_2 0x0111 |
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| 30 | #define WCD934X_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD 0x0213 |
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| 31 | #define WCD934X_CPE_SS_SVA_CFG 0x0214 |
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| 32 | #define WCD934X_CPE_SS_DMIC0_CTL 0x0218 |
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| 33 | #define WCD934X_CPE_SS_DMIC1_CTL 0x0219 |
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| 34 | #define WCD934X_DMIC_RATE_MASK GENMASK(3, 1) |
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| 35 | #define WCD934X_CPE_SS_DMIC2_CTL 0x021a |
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| 36 | #define WCD934X_CPE_SS_DMIC_CFG 0x021b |
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| 37 | #define WCD934X_CPE_SS_DMIC_CFG 0x021b |
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| 38 | #define WCD934X_CPE_SS_CPAR_CFG 0x021c |
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| 39 | #define WCD934X_INTR_PIN1_MASK0 0x0409 |
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| 40 | #define WCD934X_INTR_PIN1_STATUS0 0x0411 |
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| 41 | #define WCD934X_INTR_PIN1_CLEAR0 0x0419 |
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| 42 | #define WCD934X_INTR_PIN2_CLEAR3 0x0434 |
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| 43 | #define WCD934X_INTR_LEVEL0 0x0461 |
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| 44 | /* INTR_REG 0 */ |
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| 45 | #define WCD934X_IRQ_SLIMBUS 0 |
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| 46 | #define WCD934X_IRQ_MISC 1 |
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| 47 | #define WCD934X_IRQ_HPH_PA_OCPL_FAULT 2 |
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| 48 | #define WCD934X_IRQ_HPH_PA_OCPR_FAULT 3 |
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| 49 | #define WCD934X_IRQ_EAR_PA_OCP_FAULT 4 |
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| 50 | #define WCD934X_IRQ_HPH_PA_CNPL_COMPLETE 5 |
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| 51 | #define WCD934X_IRQ_HPH_PA_CNPR_COMPLETE 6 |
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| 52 | #define WCD934X_IRQ_EAR_PA_CNP_COMPLETE 7 |
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| 53 | /* INTR_REG 1 */ |
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| 54 | #define WCD934X_IRQ_MBHC_SW_DET 8 |
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| 55 | #define WCD934X_IRQ_MBHC_ELECT_INS_REM_DET 9 |
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| 56 | #define WCD934X_IRQ_MBHC_BUTTON_PRESS_DET 10 |
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| 57 | #define WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET 11 |
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| 58 | #define WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET 12 |
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| 59 | #define WCD934X_IRQ_RESERVED_0 13 |
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| 60 | #define WCD934X_IRQ_RESERVED_1 14 |
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| 61 | #define WCD934X_IRQ_RESERVED_2 15 |
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| 62 | /* INTR_REG 2 */ |
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| 63 | #define WCD934X_IRQ_LINE_PA1_CNP_COMPLETE 16 |
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| 64 | #define WCD934X_IRQ_LINE_PA2_CNP_COMPLETE 17 |
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| 65 | #define WCD934X_IRQ_SLNQ_ANALOG_ERROR 18 |
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| 66 | #define WCD934X_IRQ_RESERVED_3 19 |
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| 67 | #define WCD934X_IRQ_SOUNDWIRE 20 |
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| 68 | #define WCD934X_IRQ_VDD_DIG_RAMP_COMPLETE 21 |
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| 69 | #define WCD934X_IRQ_RCO_ERROR 22 |
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| 70 | #define WCD934X_IRQ_CPE_ERROR 23 |
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| 71 | /* INTR_REG 3 */ |
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| 72 | #define WCD934X_IRQ_MAD_AUDIO 24 |
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| 73 | #define WCD934X_IRQ_MAD_BEACON 25 |
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| 74 | #define WCD934X_IRQ_MAD_ULTRASOUND 26 |
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| 75 | #define WCD934X_IRQ_VBAT_ATTACK 27 |
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| 76 | #define WCD934X_IRQ_VBAT_RESTORE 28 |
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| 77 | #define WCD934X_IRQ_CPE1_INTR 29 |
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| 78 | #define WCD934X_IRQ_RESERVED_4 30 |
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| 79 | #define WCD934X_IRQ_SLNQ_DIGITAL 31 |
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| 80 | #define WCD934X_NUM_IRQS 32 |
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| 81 | #define WCD934X_ANA_BIAS 0x0601 |
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| 82 | #define WCD934X_ANA_BIAS_EN_MASK BIT(7) |
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| 83 | #define WCD934X_ANA_BIAS_EN BIT(7) |
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| 84 | #define WCD934X_ANA_PRECHRG_EN_MASK BIT(6) |
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| 85 | #define WCD934X_ANA_PRECHRG_EN BIT(6) |
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| 86 | #define WCD934X_ANA_PRECHRG_MODE_MASK BIT(5) |
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| 87 | #define WCD934X_ANA_PRECHRG_MODE_AUTO BIT(5) |
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| 88 | #define WCD934X_ANA_RCO 0x0603 |
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| 89 | #define WCD934X_ANA_RCO_BG_EN_MASK BIT(7) |
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| 90 | #define WCD934X_ANA_RCO_BG_ENABLE BIT(7) |
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| 91 | #define WCD934X_ANA_BUCK_CTL 0x0606 |
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| 92 | #define WCD934X_ANA_BUCK_HI_ACCU_PRE_ENX_MASK GENMASK(1, 0) |
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| 93 | #define WCD934X_ANA_BUCK_PRE_EN2_MASK BIT(0) |
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| 94 | #define WCD934X_ANA_BUCK_PRE_EN2_ENABLE BIT(0) |
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| 95 | #define WCD934X_ANA_BUCK_PRE_EN1_MASK BIT(1) |
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| 96 | #define WCD934X_ANA_BUCK_PRE_EN1_ENABLE BIT(1) |
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| 97 | #define WCD934X_ANA_BUCK_HI_ACCU_EN_MASK BIT(2) |
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| 98 | #define WCD934X_ANA_BUCK_HI_ACCU_ENABLE BIT(2) |
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| 99 | #define WCD934X_ANA_RX_SUPPLIES 0x0608 |
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| 100 | #define WCD934X_ANA_HPH 0x0609 |
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| 101 | #define WCD934X_ANA_EAR 0x060a |
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| 102 | #define WCD934X_ANA_LO_1_2 0x060b |
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| 103 | #define WCD934X_ANA_AMIC1 0x060e |
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| 104 | #define WCD934X_ANA_AMIC2 0x060f |
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| 105 | #define WCD934X_ANA_AMIC3 0x0610 |
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| 106 | #define WCD934X_ANA_AMIC4 0x0611 |
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| 107 | #define WCD934X_ANA_MBHC_MECH 0x0614 |
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| 108 | #define WCD934X_MBHC_L_DET_EN_MASK BIT(7) |
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| 109 | #define WCD934X_MBHC_L_DET_EN BIT(7) |
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| 110 | #define WCD934X_MBHC_GND_DET_EN_MASK BIT(6) |
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| 111 | #define WCD934X_MBHC_MECH_DETECT_TYPE_MASK BIT(5) |
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| 112 | #define WCD934X_MBHC_MECH_DETECT_TYPE_INS 1 |
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| 113 | #define WCD934X_MBHC_HPHL_PLUG_TYPE_MASK BIT(4) |
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| 114 | #define WCD934X_MBHC_HPHL_PLUG_TYPE_NO 1 |
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| 115 | #define WCD934X_MBHC_GND_PLUG_TYPE_MASK BIT(3) |
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| 116 | #define WCD934X_MBHC_GND_PLUG_TYPE_NO 1 |
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| 117 | #define WCD934X_MBHC_HSL_PULLUP_COMP_EN BIT(2) |
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| 118 | #define WCD934X_MBHC_HSG_PULLUP_COMP_EN BIT(1) |
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| 119 | #define WCD934X_MBHC_HPHL_100K_TO_GND_EN BIT(0) |
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| 120 | #define WCD934X_ANA_MBHC_ELECT 0x0615 |
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| 121 | #define WCD934X_ANA_MBHC_BIAS_EN_MASK BIT(0) |
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| 122 | #define WCD934X_ANA_MBHC_BIAS_EN BIT(0) |
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| 123 | #define WCD934X_ANA_MBHC_ZDET 0x0616 |
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| 124 | #define WCD934X_ANA_MBHC_RESULT_1 0x0617 |
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| 125 | #define WCD934X_ANA_MBHC_RESULT_2 0x0618 |
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| 126 | #define WCD934X_ANA_MBHC_RESULT_3 0x0619 |
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| 127 | #define WCD934X_ANA_MBHC_BTN0 0x061a |
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| 128 | #define WCD934X_VTH_MASK GENMASK(7, 2) |
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| 129 | #define WCD934X_ANA_MBHC_BTN1 0x061b |
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| 130 | #define WCD934X_ANA_MBHC_BTN2 0x061c |
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| 131 | #define WCD934X_ANA_MBHC_BTN3 0x061d |
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| 132 | #define WCD934X_ANA_MBHC_BTN4 0x061e |
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| 133 | #define WCD934X_ANA_MBHC_BTN5 0x061f |
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| 134 | #define WCD934X_ANA_MBHC_BTN6 0x0620 |
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| 135 | #define WCD934X_ANA_MBHC_BTN7 0x0621 |
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| 136 | #define WCD934X_MBHC_BTN_VTH_MASK GENMASK(7, 2) |
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| 137 | #define WCD934X_ANA_MICB1 0x0622 |
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| 138 | #define WCD934X_MICB_VAL_MASK GENMASK(5, 0) |
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| 139 | #define WCD934X_ANA_MICB_EN_MASK GENMASK(7, 6) |
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| 140 | #define WCD934X_MICB_DISABLE 0 |
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| 141 | #define WCD934X_MICB_ENABLE 1 |
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| 142 | #define WCD934X_MICB_PULL_UP 2 |
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| 143 | #define WCD934X_MICB_PULL_DOWN 3 |
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| 144 | #define WCD934X_ANA_MICB_PULL_UP 0x80 |
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| 145 | #define WCD934X_ANA_MICB_ENABLE 0x40 |
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| 146 | #define WCD934X_ANA_MICB_DISABLE 0x0 |
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| 147 | #define WCD934X_ANA_MICB2 0x0623 |
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| 148 | #define WCD934X_ANA_MICB2_ENABLE BIT(6) |
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| 149 | #define WCD934X_ANA_MICB2_ENABLE_MASK GENMASK(7, 6) |
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| 150 | #define WCD934X_ANA_MICB2_VOUT_MASK GENMASK(5, 0) |
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| 151 | #define WCD934X_ANA_MICB2_RAMP 0x0624 |
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| 152 | #define WCD934X_RAMP_EN_MASK BIT(7) |
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| 153 | #define WCD934X_RAMP_SHIFT_CTRL_MASK GENMASK(4, 2) |
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| 154 | #define WCD934X_ANA_MICB3 0x0625 |
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| 155 | #define WCD934X_ANA_MICB4 0x0626 |
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| 156 | #define WCD934X_BIAS_VBG_FINE_ADJ 0x0629 |
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| 157 | #define WCD934X_MBHC_CTL_CLK 0x0656 |
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| 158 | #define WCD934X_MBHC_CTL_BCS 0x065a |
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| 159 | #define WCD934X_MBHC_STATUS_SPARE_1 0x065b |
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| 160 | #define WCD934X_MICB1_TEST_CTL_1 0x066b |
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| 161 | #define WCD934X_MICB1_TEST_CTL_2 0x066c |
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| 162 | #define WCD934X_MICB2_TEST_CTL_1 0x066e |
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| 163 | #define WCD934X_MICB3_TEST_CTL_1 0x0671 |
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| 164 | #define WCD934X_MICB4_TEST_CTL_1 0x0674 |
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| 165 | #define WCD934X_CLASSH_MODE_1 0x0697 |
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| 166 | #define WCD934X_CLASSH_MODE_2 0x0698 |
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| 167 | #define WCD934X_CLASSH_MODE_3 0x0699 |
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| 168 | #define WCD934X_CLASSH_CTRL_VCL_1 0x069a |
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| 169 | #define WCD934X_CLASSH_CTRL_VCL_2 0x069b |
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| 170 | #define WCD934X_CLASSH_CTRL_CCL_1 0x069c |
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| 171 | #define WCD934X_CLASSH_CTRL_CCL_2 0x069d |
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| 172 | #define WCD934X_CLASSH_CTRL_CCL_3 0x069e |
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| 173 | #define WCD934X_CLASSH_CTRL_CCL_4 0x069f |
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| 174 | #define WCD934X_CLASSH_CTRL_CCL_5 0x06a0 |
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| 175 | #define WCD934X_CLASSH_BUCK_TMUX_A_D 0x06a1 |
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| 176 | #define WCD934X_CLASSH_BUCK_SW_DRV_CNTL 0x06a2 |
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| 177 | #define WCD934X_RX_OCP_CTL 0x06b6 |
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| 178 | #define WCD934X_RX_OCP_COUNT 0x06b7 |
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| 179 | #define WCD934X_HPH_CNP_EN 0x06cb |
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| 180 | #define WCD934X_HPH_CNP_WG_CTL 0x06cc |
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| 181 | #define WCD934X_HPH_GM3_BOOST_EN_MASK BIT(7) |
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| 182 | #define WCD934X_HPH_GM3_BOOST_ENABLE BIT(7) |
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| 183 | #define WCD934X_HPH_CNP_WG_TIME 0x06cd |
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| 184 | #define WCD934X_HPH_OCP_CTL 0x06ce |
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| 185 | #define WCD934X_HPH_PA_CTL2 0x06d2 |
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| 186 | #define WCD934X_HPHPA_GND_R_MASK BIT(6) |
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| 187 | #define WCD934X_HPHPA_GND_L_MASK BIT(4) |
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| 188 | #define WCD934X_HPH_L_EN 0x06d3 |
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| 189 | #define WCD934X_HPH_GAIN_SRC_SEL_MASK BIT(5) |
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| 190 | #define WCD934X_HPH_GAIN_SRC_SEL_COMPANDER 0 |
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| 191 | #define WCD934X_HPH_GAIN_SRC_SEL_REGISTER BIT(5) |
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| 192 | #define WCD934X_HPH_L_TEST 0x06d4 |
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| 193 | #define WCD934X_HPH_R_EN 0x06d6 |
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| 194 | #define WCD934X_HPH_R_TEST 0x06d7 |
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| 195 | #define WCD934X_HPH_OCP_DET_MASK BIT(0) |
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| 196 | #define WCD934X_HPH_OCP_DET_ENABLE BIT(0) |
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| 197 | #define WCD934X_HPH_OCP_DET_DISABLE 0 |
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| 198 | #define WCD934X_HPH_R_ATEST 0x06d8 |
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| 199 | #define WCD934X_HPHPA_GND_OVR_MASK BIT(1) |
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| 200 | #define WCD934X_DIFF_LO_LO2_COMPANDER 0x06ea |
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| 201 | #define WCD934X_DIFF_LO_LO1_COMPANDER 0x06eb |
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| 202 | #define WCD934X_CLK_SYS_MCLK_PRG 0x0711 |
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| 203 | #define WCD934X_EXT_CLK_BUF_EN_MASK BIT(7) |
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| 204 | #define WCD934X_EXT_CLK_BUF_EN BIT(7) |
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| 205 | #define WCD934X_EXT_CLK_DIV_RATIO_MASK GENMASK(5, 4) |
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| 206 | #define WCD934X_EXT_CLK_DIV_BY_2 0x10 |
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| 207 | #define WCD934X_MCLK_SRC_MASK BIT(1) |
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| 208 | #define WCD934X_MCLK_SRC_EXT_CLK 0 |
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| 209 | #define WCD934X_MCLK_SRC_MASK BIT(1) |
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| 210 | #define WCD934X_MCLK_EN_MASK BIT(0) |
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| 211 | #define WCD934X_MCLK_EN BIT(0) |
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| 212 | #define WCD934X_CLK_SYS_MCLK2_PRG1 0x0712 |
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| 213 | #define WCD934X_CLK_SYS_MCLK2_PRG2 0x0713 |
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| 214 | #define WCD934X_SIDO_NEW_VOUT_A_STARTUP 0x071b |
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| 215 | #define WCD934X_SIDO_NEW_VOUT_D_STARTUP 0x071c |
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| 216 | #define WCD934X_SIDO_NEW_VOUT_D_FREQ1 0x071d |
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| 217 | #define WCD934X_SIDO_NEW_VOUT_D_FREQ2 0x071e |
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| 218 | #define WCD934X_SIDO_RIPPLE_FREQ_EN_MASK BIT(0) |
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| 219 | #define WCD934X_SIDO_RIPPLE_FREQ_ENABLE BIT(0) |
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| 220 | #define WCD934X_MBHC_NEW_CTL_1 0x0720 |
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| 221 | #define WCD934X_MBHC_CTL_RCO_EN_MASK BIT(7) |
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| 222 | #define WCD935X_MBHC_CTL_RCO_EN BIT(7) |
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| 223 | #define WCD934X_MBHC_NEW_CTL_2 0x0721 |
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| 224 | #define WCD934X_M_RTH_CTL_MASK GENMASK(3, 2) |
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| 225 | #define WCD934X_MBHC_NEW_PLUG_DETECT_CTL 0x0722 |
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| 226 | #define WCD934X_HSDET_PULLUP_C_MASK GENMASK(7, 6) |
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| 227 | #define WCD934X_MBHC_NEW_ZDET_ANA_CTL 0x0723 |
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| 228 | #define WCD934X_ZDET_RANGE_CTL_MASK GENMASK(3, 0) |
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| 229 | #define WCD934X_ZDET_MAXV_CTL_MASK GENMASK(6, 4) |
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| 230 | #define WCD934X_MBHC_NEW_ZDET_RAMP_CTL 0x0724 |
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| 231 | #define WCD934X_MBHC_NEW_FSM_STATUS 0x0725 |
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| 232 | #define WCD934X_MBHC_NEW_ADC_RESULT 0x0726 |
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| 233 | #define WCD934X_TX_NEW_AMIC_4_5_SEL 0x0727 |
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| 234 | #define WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_L 0x0733 |
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| 235 | #define WCD934X_HPH_NEW_INT_RDAC_OVERRIDE_CTL 0x0735 |
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| 236 | #define WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_R 0x0736 |
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| 237 | #define WCD934X_HPH_NEW_INT_HPH_TIMER1 0x073a |
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| 238 | #define WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK BIT(1) |
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| 239 | #define WCD934X_HPH_AUTOCHOP_TIMER_ENABLE BIT(1) |
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| 240 | #define WCD934X_CDC_TX0_TX_PATH_CTL 0x0a31 |
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| 241 | #define WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK GENMASK(3, 0) |
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| 242 | #define WCD934X_CDC_TX_PATH_CTL(dec) (0xa31 + dec * 0x10) |
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| 243 | #define WCD934X_CDC_TX0_TX_PATH_CFG0 0x0a32 |
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| 244 | #define WCD934X_CDC_TX0_TX_PATH_CFG1 0x0a33 |
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| 245 | #define WCD934X_CDC_TX0_TX_VOL_CTL 0x0a34 |
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| 246 | #define WCD934X_CDC_TX0_TX_PATH_192_CTL 0x0a35 |
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| 247 | #define WCD934X_CDC_TX0_TX_PATH_192_CFG 0x0a36 |
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| 248 | #define WCD934X_CDC_TX0_TX_PATH_SEC2 0x0a39 |
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| 249 | #define WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK BIT(1) |
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| 250 | #define WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ BIT(1) |
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| 251 | #define WCD934X_CDC_TX1_TX_PATH_CTL 0x0a41 |
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| 252 | #define WCD934X_CDC_TX1_TX_PATH_CFG0 0x0a42 |
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| 253 | #define WCD934X_CDC_TX1_TX_PATH_CFG1 0x0a43 |
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| 254 | #define WCD934X_CDC_TX1_TX_VOL_CTL 0x0a44 |
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| 255 | #define WCD934X_CDC_TX2_TX_PATH_CTL 0x0a51 |
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| 256 | #define WCD934X_CDC_TX2_TX_PATH_CFG0 0x0a52 |
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| 257 | #define WCD934X_CDC_TX2_TX_PATH_CFG1 0x0a53 |
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| 258 | #define WCD934X_CDC_TX2_TX_VOL_CTL 0x0a54 |
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| 259 | #define WCD934X_CDC_TX3_TX_PATH_CTL 0x0a61 |
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| 260 | #define WCD934X_CDC_TX3_TX_PATH_CFG0 0x0a62 |
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| 261 | #define WCD934X_CDC_TX3_TX_PATH_CFG1 0x0a63 |
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| 262 | #define WCD934X_CDC_TX3_TX_VOL_CTL 0x0a64 |
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| 263 | #define WCD934X_CDC_TX3_TX_PATH_192_CTL 0x0a65 |
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| 264 | #define WCD934X_CDC_TX3_TX_PATH_192_CFG 0x0a66 |
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| 265 | #define WCD934X_CDC_TX4_TX_PATH_CTL 0x0a71 |
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| 266 | #define WCD934X_CDC_TX4_TX_PATH_CFG0 0x0a72 |
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| 267 | #define WCD934X_CDC_TX4_TX_PATH_CFG1 0x0a73 |
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| 268 | #define WCD934X_CDC_TX4_TX_VOL_CTL 0x0a74 |
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| 269 | #define WCD934X_CDC_TX4_TX_PATH_192_CTL 0x0a75 |
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| 270 | #define WCD934X_CDC_TX4_TX_PATH_192_CFG 0x0a76 |
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| 271 | #define WCD934X_CDC_TX5_TX_PATH_CTL 0x0a81 |
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| 272 | #define WCD934X_CDC_TX5_TX_PATH_CFG0 0x0a82 |
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| 273 | #define WCD934X_CDC_TX5_TX_PATH_CFG1 0x0a83 |
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| 274 | #define WCD934X_CDC_TX5_TX_VOL_CTL 0x0a84 |
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| 275 | #define WCD934X_CDC_TX5_TX_PATH_192_CTL 0x0a85 |
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| 276 | #define WCD934X_CDC_TX5_TX_PATH_192_CFG 0x0a86 |
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| 277 | #define WCD934X_CDC_TX6_TX_PATH_CTL 0x0a91 |
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| 278 | #define WCD934X_CDC_TX6_TX_PATH_CFG0 0x0a92 |
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| 279 | #define WCD934X_CDC_TX6_TX_PATH_CFG1 0x0a93 |
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| 280 | #define WCD934X_CDC_TX6_TX_VOL_CTL 0x0a94 |
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| 281 | #define WCD934X_CDC_TX6_TX_PATH_192_CTL 0x0a95 |
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| 282 | #define WCD934X_CDC_TX6_TX_PATH_192_CFG 0x0a96 |
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| 283 | #define WCD934X_CDC_TX7_TX_PATH_CTL 0x0aa1 |
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| 284 | #define WCD934X_CDC_TX7_TX_PATH_CFG0 0x0aa2 |
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| 285 | #define WCD934X_CDC_TX7_TX_PATH_CFG1 0x0aa3 |
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| 286 | #define WCD934X_CDC_TX7_TX_VOL_CTL 0x0aa4 |
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| 287 | #define WCD934X_CDC_TX7_TX_PATH_192_CTL 0x0aa5 |
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| 288 | #define WCD934X_CDC_TX7_TX_PATH_192_CFG 0x0aa6 |
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| 289 | #define WCD934X_CDC_TX8_TX_PATH_CTL 0x0ab1 |
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| 290 | #define WCD934X_CDC_TX8_TX_PATH_CFG0 0x0ab2 |
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| 291 | #define WCD934X_CDC_TX8_TX_PATH_CFG1 0x0ab3 |
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| 292 | #define WCD934X_CDC_TX8_TX_VOL_CTL 0x0ab4 |
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| 293 | #define WCD934X_CDC_TX8_TX_PATH_192_CTL 0x0ab5 |
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| 294 | #define WCD934X_CDC_TX8_TX_PATH_192_CFG 0x0ab6 |
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| 295 | #define WCD934X_CDC_TX9_SPKR_PROT_PATH_CFG0 0x0ac3 |
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| 296 | #define WCD934X_CDC_TX10_SPKR_PROT_PATH_CFG0 0x0ac7 |
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| 297 | #define WCD934X_CDC_TX11_SPKR_PROT_PATH_CFG0 0x0acb |
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| 298 | #define WCD934X_CDC_TX12_SPKR_PROT_PATH_CFG0 0x0acf |
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| 299 | #define WCD934X_CDC_COMPANDER1_CTL0 0x0b01 |
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| 300 | #define WCD934X_COMP_CLK_EN_MASK BIT(0) |
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| 301 | #define WCD934X_COMP_CLK_ENABLE BIT(0) |
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| 302 | #define WCD934X_COMP_SOFT_RST_MASK BIT(1) |
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| 303 | #define WCD934X_COMP_SOFT_RST_ENABLE BIT(1) |
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| 304 | #define WCD934X_COMP_HALT_MASK BIT(2) |
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| 305 | #define WCD934X_COMP_HALT BIT(2) |
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| 306 | #define WCD934X_COMP_SOFT_RST_DISABLE 0 |
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| 307 | #define WCD934X_CDC_COMPANDER1_CTL7 0x0b08 |
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| 308 | #define WCD934X_HPH_LOW_PWR_MODE_EN_MASK BIT(5) |
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| 309 | #define WCD934X_CDC_COMPANDER2_CTL7 0x0b10 |
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| 310 | #define WCD934X_CDC_COMPANDER7_CTL3 0x0b34 |
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| 311 | #define WCD934X_CDC_COMPANDER7_CTL7 0x0b38 |
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| 312 | #define WCD934X_CDC_COMPANDER8_CTL3 0x0b3c |
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| 313 | #define WCD934X_CDC_COMPANDER8_CTL7 0x0b40 |
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| 314 | #define WCD934X_CDC_RX0_RX_PATH_CTL 0x0b41 |
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| 315 | #define WCD934X_CDC_RX_PGA_MUTE_EN_MASK BIT(4) |
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| 316 | #define WCD934X_CDC_RX_PGA_MUTE_ENABLE BIT(4) |
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| 317 | #define WCD934X_CDC_RX_PGA_MUTE_DISABLE 0 |
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| 318 | #define WCD934X_RX_CLK_EN_MASK BIT(5) |
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| 319 | #define WCD934X_RX_CLK_ENABLE BIT(5) |
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| 320 | #define WCD934X_RX_RESET_MASK BIT(6) |
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| 321 | #define WCD934X_RX_RESET_ENABLE BIT(6) |
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| 322 | #define WCD934X_RX_RESET_DISABLE 0 |
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| 323 | #define WCD934X_RX_PCM_RATE_MASK GENMASK(3, 0) |
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| 324 | #define WCD934X_RX_PCM_RATE_F_48K 0x04 |
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| 325 | #define WCD934X_CDC_RX_PATH_CTL(rx) (0xb41 + rx * 0x14) |
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| 326 | #define WCD934X_CDC_MIX_PCM_RATE_MASK GENMASK(3, 0) |
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| 327 | #define WCD934X_CDC_RX0_RX_PATH_CFG0 0x0b42 |
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| 328 | #define WCD934X_RX_DLY_ZN_EN_MASK BIT(3) |
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| 329 | #define WCD934X_RX_DLY_ZN_ENABLE BIT(3) |
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| 330 | #define WCD934X_RX_DLY_ZN_DISABLE 0 |
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| 331 | #define WCD934X_CDC_RX0_RX_PATH_CFG1 0x0b43 |
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| 332 | #define WCD934X_CDC_RX0_RX_PATH_CFG2 0x0b44 |
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| 333 | #define WCD934X_CDC_RX0_RX_VOL_CTL 0x0b45 |
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| 334 | #define WCD934X_CDC_RX0_RX_PATH_MIX_CTL 0x0b46 |
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| 335 | #define WCD934X_CDC_RX_MIX_CLK_EN_MASK BIT(5) |
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| 336 | #define WCD934X_CDC_RX_MIX_CLK_ENABLE BIT(5) |
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| 337 | #define WCD934X_CDC_RX_PATH_MIX_CTL(rx) (0xb46 + rx * 0x14) |
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| 338 | #define WCD934X_CDC_RX0_RX_PATH_MIX_CFG 0x0b47 |
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| 339 | #define WCD934X_CDC_RX0_RX_VOL_MIX_CTL 0x0b48 |
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| 340 | #define WCD934X_CDC_RX0_RX_PATH_SEC0 0x0b49 |
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| 341 | #define WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL 0x0b53 |
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| 342 | #define WCD934X_CDC_RX1_RX_PATH_CTL 0x0b55 |
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| 343 | #define WCD934X_RX_PATH_PGA_MUTE_EN_MASK BIT(4) |
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| 344 | #define WCD934X_RX_PATH_PGA_MUTE_ENABLE BIT(4) |
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| 345 | #define WCD934X_CDC_RX_PATH_PGA_MUTE_DISABLE 0 |
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| 346 | #define WCD934X_CDC_RX_PATH_CLK_EN_MASK BIT(5) |
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| 347 | #define WCD934X_CDC_RX_PATH_CLK_ENABLE BIT(5) |
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| 348 | #define WCD934X_CDC_RX_PATH_CLK_DISABLE 0 |
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| 349 | #define WCD934X_CDC_RX1_RX_PATH_CFG0 0x0b56 |
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| 350 | #define WCD934X_HPH_CMP_EN_MASK BIT(1) |
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| 351 | #define WCD934X_HPH_CMP_ENABLE BIT(1) |
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| 352 | #define WCD934X_HPH_CMP_DISABLE 0 |
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| 353 | #define WCD934X_CDC_RX1_RX_PATH_CFG2 0x0b58 |
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| 354 | #define WCD934X_CDC_RX1_RX_VOL_CTL 0x0b59 |
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| 355 | #define WCD934X_CDC_RX1_RX_PATH_MIX_CTL 0x0b5a |
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| 356 | #define WCD934X_CDC_RX1_RX_PATH_MIX_CFG 0x0b5b |
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| 357 | #define WCD934X_CDC_RX1_RX_VOL_MIX_CTL 0x0b5c |
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| 358 | #define WCD934X_CDC_RX1_RX_PATH_SEC0 0x0b5d |
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| 359 | #define WCD934X_CDC_RX1_RX_PATH_SEC3 0x0b60 |
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| 360 | #define WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK GENMASK(5, 2) |
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| 361 | #define WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125 0x14 |
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| 362 | #define WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000 0 |
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| 363 | #define WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL 0x0b67 |
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| 364 | #define WCD934X_CDC_RX2_RX_PATH_CTL 0x0b69 |
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| 365 | #define WCD934X_CDC_RX2_RX_PATH_CFG0 0x0b6a |
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| 366 | #define WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK BIT(2) |
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| 367 | #define WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE BIT(2) |
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| 368 | #define WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE 0 |
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| 369 | #define WCD934X_CDC_RX2_RX_PATH_CFG2 0x0b6c |
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| 370 | #define WCD934X_CDC_RX2_RX_VOL_CTL 0x0b6d |
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| 371 | #define WCD934X_CDC_RX2_RX_PATH_MIX_CTL 0x0b6e |
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| 372 | #define WCD934X_CDC_RX2_RX_PATH_MIX_CFG 0x0b6f |
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| 373 | #define WCD934X_CDC_RX2_RX_VOL_MIX_CTL 0x0b70 |
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| 374 | #define WCD934X_CDC_RX2_RX_PATH_SEC0 0x0b71 |
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| 375 | #define WCD934X_CDC_RX2_RX_PATH_SEC3 0x0b74 |
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| 376 | #define WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL 0x0b7b |
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| 377 | #define WCD934X_CDC_RX3_RX_PATH_CTL 0x0b7d |
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| 378 | #define WCD934X_CDC_RX3_RX_PATH_CFG0 0x0b6e |
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| 379 | #define WCD934X_CDC_RX3_RX_PATH_CFG2 0x0b80 |
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| 380 | #define WCD934X_CDC_RX3_RX_VOL_CTL 0x0b81 |
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| 381 | #define WCD934X_CDC_RX3_RX_PATH_MIX_CTL 0x0b82 |
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| 382 | #define WCD934X_CDC_RX3_RX_PATH_MIX_CFG 0x0b83 |
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| 383 | #define WCD934X_CDC_RX3_RX_VOL_MIX_CTL 0x0b84 |
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| 384 | #define WCD934X_CDC_RX3_RX_PATH_SEC0 0x0b85 |
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| 385 | #define WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL 0x0b8f |
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| 386 | #define WCD934X_CDC_RX4_RX_PATH_CTL 0x0b91 |
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| 387 | #define WCD934X_CDC_RX4_RX_PATH_CFG0 0x0b92 |
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| 388 | #define WCD934X_CDC_RX4_RX_PATH_CFG2 0x0b94 |
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| 389 | #define WCD934X_CDC_RX4_RX_VOL_CTL 0x0b95 |
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| 390 | #define WCD934X_CDC_RX4_RX_PATH_MIX_CTL 0x0b96 |
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| 391 | #define WCD934X_CDC_RX4_RX_PATH_MIX_CFG 0x0b97 |
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| 392 | #define WCD934X_CDC_RX4_RX_VOL_MIX_CTL 0x0b98 |
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| 393 | #define WCD934X_CDC_RX4_RX_PATH_SEC0 0x0b99 |
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| 394 | #define WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL 0x0ba3 |
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| 395 | #define WCD934X_CDC_RX7_RX_PATH_CTL 0x0bcd |
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| 396 | #define WCD934X_CDC_RX7_RX_PATH_CFG0 0x0bce |
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| 397 | #define WCD934X_CDC_RX7_RX_PATH_CFG1 0x0bcf |
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| 398 | #define WCD934X_CDC_RX7_RX_PATH_CFG2 0x0bd0 |
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| 399 | #define WCD934X_CDC_RX7_RX_VOL_CTL 0x0bd1 |
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| 400 | #define WCD934X_CDC_RX7_RX_PATH_MIX_CTL 0x0bd2 |
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| 401 | #define WCD934X_CDC_RX7_RX_PATH_MIX_CFG 0x0bd3 |
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| 402 | #define WCD934X_CDC_RX7_RX_VOL_MIX_CTL 0x0bd4 |
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| 403 | #define WCD934X_CDC_RX7_RX_PATH_SEC1 0x0bd6 |
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| 404 | #define WCD934X_CDC_RX7_RX_PATH_MIX_SEC0 0x0bdd |
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| 405 | #define WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL 0x0bdf |
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| 406 | #define WCD934X_CDC_RX8_RX_PATH_CTL 0x0be1 |
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| 407 | #define WCD934X_CDC_RX8_RX_PATH_CFG0 0x0be2 |
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| 408 | #define WCD934X_CDC_RX8_RX_PATH_CFG1 0x0be3 |
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| 409 | #define WCD934X_RX_SMART_BOOST_EN_MASK BIT(0) |
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| 410 | #define WCD934X_RX_SMART_BOOST_ENABLE BIT(0) |
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| 411 | #define WCD934X_RX_SMART_BOOST_DISABLE 0 |
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| 412 | #define WCD934X_CDC_RX8_RX_PATH_CFG2 0x0be4 |
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| 413 | #define WCD934X_CDC_RX8_RX_VOL_CTL 0x0be5 |
|---|
| 414 | #define WCD934X_CDC_RX8_RX_PATH_MIX_CTL 0x0be6 |
|---|
| 415 | #define WCD934X_CDC_RX8_RX_PATH_MIX_CFG 0x0be7 |
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| 416 | #define WCD934X_CDC_RX8_RX_VOL_MIX_CTL 0x0be8 |
|---|
| 417 | #define WCD934X_CDC_RX8_RX_PATH_SEC1 0x0bea |
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| 418 | #define WCD934X_CDC_RX8_RX_PATH_MIX_SEC0 0x0bf1 |
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| 419 | #define WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL 0x0bf3 |
|---|
| 420 | #define WCD934X_CDC_CLSH_DECAY_CTRL 0x0c03 |
|---|
| 421 | #define WCD934X_CDC_CLSH_K2_MSB 0x0c0a |
|---|
| 422 | #define WCD934X_CDC_CLSH_K2_LSB 0x0c0b |
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| 423 | #define WCD934X_CDC_CLSH_TEST0 0x0c0f |
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| 424 | #define WCD934X_CDC_BOOST0_BOOST_PATH_CTL 0x0c19 |
|---|
| 425 | #define WCD934X_BOOST_PATH_CLK_EN_MASK BIT(4) |
|---|
| 426 | #define WCD934X_BOOST_PATH_CLK_ENABLE BIT(4) |
|---|
| 427 | #define WCD934X_BOOST_PATH_CLK_DISABLE 0 |
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| 428 | #define WCD934X_CDC_BOOST0_BOOST_CTL 0x0c1a |
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| 429 | #define WCD934X_CDC_BOOST0_BOOST_CFG1 0x0c1b |
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| 430 | #define WCD934X_CDC_BOOST0_BOOST_CFG2 0x0c1c |
|---|
| 431 | #define WCD934X_CDC_BOOST1_BOOST_PATH_CTL 0x0c21 |
|---|
| 432 | #define WCD934X_CDC_BOOST1_BOOST_CTL 0x0c22 |
|---|
| 433 | #define WCD934X_CDC_BOOST1_BOOST_CFG1 0x0c23 |
|---|
| 434 | #define WCD934X_CDC_BOOST1_BOOST_CFG2 0x0c24 |
|---|
| 435 | #define WCD934X_SWR_AHB_BRIDGE_RD_DATA_0 0x0c91 |
|---|
| 436 | #define WCD934X_SWR_AHB_BRIDGE_RD_DATA_1 0x0c92 |
|---|
| 437 | #define WCD934X_SWR_AHB_BRIDGE_RD_DATA_2 0x0c93 |
|---|
| 438 | #define WCD934X_SWR_AHB_BRIDGE_RD_DATA_3 0x0c94 |
|---|
| 439 | #define WCD934X_SWR_AHB_BRIDGE_ACCESS_STATUS 0x0c96 |
|---|
| 440 | #define WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL 0x0cb5 |
|---|
| 441 | #define WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL 0x0cb9 |
|---|
| 442 | #define WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0 0x0d01 |
|---|
| 443 | #define WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(i) (0xd01 + i * 0x2) |
|---|
| 444 | #define WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK GENMASK(3, 0) |
|---|
| 445 | #define WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1 0x0d02 |
|---|
| 446 | #define WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(i) (0xd02 + i * 0x2) |
|---|
| 447 | #define WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0 0x0d03 |
|---|
| 448 | #define WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1 0x0d04 |
|---|
| 449 | #define WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0 0x0d05 |
|---|
| 450 | #define WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1 0x0d06 |
|---|
| 451 | #define WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0 0x0d07 |
|---|
| 452 | #define WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1 0x0d08 |
|---|
| 453 | #define WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0 0x0d09 |
|---|
| 454 | #define WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1 0x0d0a |
|---|
| 455 | #define WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0 0x0d0f |
|---|
| 456 | #define WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1 0x0d10 |
|---|
| 457 | #define WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0 0x0d11 |
|---|
| 458 | #define WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1 0x0d12 |
|---|
| 459 | #define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG0 0x0d13 |
|---|
| 460 | #define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG1 0x0d14 |
|---|
| 461 | #define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG2 0x0d15 |
|---|
| 462 | #define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG3 0x0d16 |
|---|
| 463 | #define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG4 0x0d17 |
|---|
| 464 | #define WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 0x0d18 |
|---|
| 465 | #define WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1 0x0d19 |
|---|
| 466 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 0x0d1d |
|---|
| 467 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 0x0d1e |
|---|
| 468 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0 0x0d1f |
|---|
| 469 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1 0x0d20 |
|---|
| 470 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0 0x0d21 |
|---|
| 471 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1 0x0d22 |
|---|
| 472 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0 0x0d23 |
|---|
| 473 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1 0x0d25 |
|---|
| 474 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 0x0d26 |
|---|
| 475 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0 0x0d27 |
|---|
| 476 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0 0x0d28 |
|---|
| 477 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0 0x0d29 |
|---|
| 478 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0 0x0d2a |
|---|
| 479 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX10_CFG0 0x0d2b |
|---|
| 480 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX11_CFG0 0x0d2c |
|---|
| 481 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX12_CFG0 0x0d2d |
|---|
| 482 | #define WCD934X_CDC_TX_INP_MUX_ADC_MUX13_CFG0 0x0d2e |
|---|
| 483 | #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0 0x0d31 |
|---|
| 484 | #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1 0x0d32 |
|---|
| 485 | #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2 0x0d33 |
|---|
| 486 | #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3 0x0d34 |
|---|
| 487 | #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0 0x0d35 |
|---|
| 488 | #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1 0x0d36 |
|---|
| 489 | #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2 0x0d37 |
|---|
| 490 | #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3 0x0d38 |
|---|
| 491 | #define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0 0x0d3a |
|---|
| 492 | #define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1 0x0d3b |
|---|
| 493 | #define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2 0x0d3c |
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| 494 | #define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3 0x0d3d |
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| 495 | #define WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL 0x0d41 |
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| 496 | #define WCD934X_CDC_MCLK_EN_MASK BIT(0) |
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| 497 | #define WCD934X_CDC_MCLK_EN_ENABLE BIT(0) |
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| 498 | #define WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL 0x0d42 |
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| 499 | #define WCD934X_CDC_FS_MCLK_CNT_EN_MASK BIT(0) |
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| 500 | #define WCD934X_CDC_FS_MCLK_CNT_ENABLE BIT(0) |
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| 501 | #define WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL 0x0d43 |
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| 502 | #define WCD934X_CDC_SWR_CLK_EN_MASK BIT(0) |
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| 503 | #define WCD934X_CDC_SWR_CLK_ENABLE BIT(0) |
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| 504 | #define WCD934X_CDC_CLK_RST_CTRL_DSD_CONTROL 0x0d44 |
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| 505 | #define WCD934X_CDC_CLK_RST_CTRL_ASRC_SHARE_CONTROL 0x0d45 |
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| 506 | #define WCD934X_CDC_CLK_RST_CTRL_GFM_CONTROL 0x0d46 |
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| 507 | #define WCD934X_CDC_SIDETONE_IIR0_IIR_PATH_CTL 0x0d55 |
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| 508 | #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL 0x0d56 |
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| 509 | #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL 0x0d57 |
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| 510 | #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL 0x0d58 |
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| 511 | #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL 0x0d59 |
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| 512 | #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B5_CTL 0x0d5a |
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| 513 | #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B6_CTL 0x0d5b |
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| 514 | #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B7_CTL 0x0d5c |
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| 515 | #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B8_CTL 0x0d5d |
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| 516 | #define WCD934X_CDC_SIDETONE_IIR0_IIR_CTL 0x0d5e |
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| 517 | #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL 0x0d5f |
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| 518 | #define WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL 0x0d60 |
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| 519 | #define WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL 0x0d61 |
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| 520 | #define WCD934X_CDC_SIDETONE_IIR1_IIR_PATH_CTL 0x0d65 |
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| 521 | #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL 0x0d66 |
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| 522 | #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL 0x0d67 |
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| 523 | #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL 0x0d68 |
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| 524 | #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL 0x0d69 |
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| 525 | #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B5_CTL 0x0d6a |
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| 526 | #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B6_CTL 0x0d6b |
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| 527 | #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B7_CTL 0x0d6c |
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| 528 | #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B8_CTL 0x0d6d |
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| 529 | #define WCD934X_CDC_SIDETONE_IIR1_IIR_CTL 0x0d6e |
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| 530 | #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL 0x0d6f |
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| 531 | #define WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B1_CTL 0x0d70 |
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| 532 | #define WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL 0x0d71 |
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| 533 | #define WCD934X_CDC_TOP_TOP_CFG1 0x0d82 |
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| 534 | #define WCD934X_CDC_TOP_TOP_CFG7 0x0d88 |
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| 535 | #define WCD934X_CDC_TOP_HPHL_COMP_LUT 0x0d8b |
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| 536 | #define WCD934X_CDC_TOP_HPHR_COMP_LUT 0x0d90 |
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| 537 | #define WCD934X_HPH_LUT_BYPASS_MASK BIT(7) |
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| 538 | #define WCD934X_HPH_LUT_BYPASS_ENABLE BIT(7) |
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| 539 | #define WCD934X_HPH_LUT_BYPASS_DISABLE 0 |
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| 540 | #define WCD934X_CODEC_CPR_WR_DATA_0 0x5001 |
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| 541 | #define WCD934X_CODEC_CPR_WR_ADDR_0 0x5005 |
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| 542 | #define WCD934X_CODEC_CPR_SVS_CX_VDD 0x5022 |
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| 543 | #define WCD934X_CODEC_CPR_SVS2_CX_VDD 0x5023 |
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| 544 | #define WCD934X_CODEC_CPR_SVS2_MIN_CX_VDD 0x5027 |
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| 545 | #define WCD934X_TLMM_DMIC1_CLK_PINCFG 0x8015 |
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| 546 | #define WCD934X_TLMM_DMIC1_DATA_PINCFG 0x8016 |
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| 547 | #define WCD934X_TLMM_DMIC2_CLK_PINCFG 0x8017 |
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| 548 | #define WCD934X_TLMM_DMIC2_DATA_PINCFG 0x8018 |
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| 549 | #define WCD934X_TLMM_DMIC3_CLK_PINCFG 0x8019 |
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| 550 | #define WCD934X_TLMM_DMIC3_DATA_PINCFG 0x801a |
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| 551 | #define WCD934X_TEST_DEBUG_PAD_DRVCTL_0 0x803b |
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| 552 | #define WCD934X_TEST_DEBUG_NPL_DLY_TEST_1 0x803e |
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| 553 | |
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| 554 | #define WCD934X_MAX_REGISTER 0xffff |
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| 555 | #define WCD934X_SEL_REGISTER 0x800 |
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| 556 | #define WCD934X_SEL_MASK 0xff |
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| 557 | #define WCD934X_SEL_SHIFT 0x0 |
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| 558 | #define WCD934X_WINDOW_START 0x800 |
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| 559 | #define WCD934X_WINDOW_LENGTH 0x100 |
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| 560 | |
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| 561 | /* SLIMBUS Slave Registers */ |
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| 562 | #define WCD934X_SLIM_PGD_PORT_INT_EN0 0x30 |
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| 563 | #define WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0 0x34 |
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| 564 | #define WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_1 0x35 |
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| 565 | #define WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_0 0x36 |
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| 566 | #define WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1 0x37 |
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| 567 | #define WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 0x38 |
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| 568 | #define WCD934X_SLIM_PGD_PORT_INT_CLR_RX_1 0x39 |
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| 569 | #define WCD934X_SLIM_PGD_PORT_INT_CLR_TX_0 0x3A |
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| 570 | #define WCD934X_SLIM_PGD_PORT_INT_CLR_TX_1 0x3B |
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| 571 | #define WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 0x60 |
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| 572 | #define WCD934X_SLIM_PGD_PORT_INT_TX_SOURCE0 0x70 |
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| 573 | #define WCD934X_SLIM_PGD_RX_PORT_CFG(p) (0x30 + p) |
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| 574 | #define WCD934X_SLIM_PGD_PORT_CFG(p) (0x40 + p) |
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| 575 | #define WCD934X_SLIM_PGD_TX_PORT_CFG(p) (0x50 + p) |
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| 576 | #define WCD934X_SLIM_PGD_PORT_INT_SRC(p) (0x60 + p) |
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| 577 | #define WCD934X_SLIM_PGD_PORT_INT_STATUS(p) (0x80 + p) |
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| 578 | #define WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(p) (0x100 + 4 * p) |
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| 579 | /* ports range from 10-16 */ |
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| 580 | #define WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(p) (0x101 + 4 * p) |
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| 581 | #define WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(p) (0x140 + 4 * p) |
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| 582 | |
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| 583 | #define SLIM_MANF_ID_QCOM 0x217 |
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| 584 | #define SLIM_PROD_CODE_WCD9340 0x250 |
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| 585 | #define SLIM_DEV_IDX_WCD9340 0x1 |
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| 586 | #define SLIM_DEV_INSTANCE_ID_WCD9340 0 |
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| 587 | |
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| 588 | #endif |
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| 589 | |
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